Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.ast_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	137075	1			T77	5		T78	26		T79	9
values[2]	11997	1			T78	2		T553	1		T490	161
values[3]	5271	1			T490	27		T555	1		T449	9
values[4]	3037	1			T490	4		T555	1		T449	3
values[5]	1836	1			T490	1		T555	1		T449	4
values[6]	1108	1			T555	1		T844	17		T455	5
values[7]	782	1			T555	1		T844	3		T455	14
values[8]	597	1			T555	1		T844	2		T455	11
values[9]	481	1			T555	1		T455	8		T475	1
values[10]	439	1			T555	1		T455	6		T475	3
values[11]	387	1			T555	1		T455	4		T475	4
values[12]	321	1			T555	1		T455	5		T475	5
values[13]	303	1			T555	1		T455	11		T475	2
values[14]	313	1			T555	1		T455	4		T475	7
values[15]	316	1			T555	1		T455	3		T475	1
values[16]	279	1			T555	1		T455	4		T475	1
values[17]	269	1			T555	1		T455	8		T475	1
values[18]	309	1			T555	1		T455	19		T475	2
values[19]	299	1			T555	1		T455	15		T475	3
values[20]	327	1			T555	1		T455	9		T475	2
values[21]	331	1			T555	1		T455	8		T475	3
values[22]	273	1			T555	1		T455	5		T475	6
values[23]	298	1			T555	1		T455	4		T475	7
values[24]	319	1			T555	1		T455	3		T475	3
values[25]	312	1			T555	1		T455	5		T475	2
values[26]	277	1			T555	1		T455	5		T475	2
values[27]	304	1			T555	1		T455	5		T475	3
values[28]	313	1			T555	1		T455	7		T475	2
values[29]	268	1			T555	1		T455	5		T475	1
values[30]	278	1			T555	1		T455	21		T475	2
values[31]	320	1			T555	1		T455	8		T475	3
values[32]	324	1			T555	1		T455	3		T475	1
values[33]	280	1			T555	1		T455	6		T475	1
values[34]	298	1			T555	1		T455	7		T475	4
values[35]	305	1			T555	1		T455	5		T475	3
values[36]	293	1			T555	1		T455	5		T475	2
values[37]	297	1			T555	1		T455	4		T475	1
values[38]	301	1			T555	1		T455	3		T475	1
values[39]	311	1			T555	1		T455	3		T475	3
values[40]	257	1			T555	1		T455	2		T475	5
values[41]	282	1			T555	1		T455	4		T475	3
values[42]	262	1			T555	1		T455	6		T475	8
values[43]	265	1			T555	1		T455	7		T475	1
values[44]	308	1			T555	1		T455	11		T475	2
values[45]	279	1			T555	1		T455	8		T475	2
values[46]	263	1			T555	1		T455	10		T475	3
values[47]	320	1			T555	1		T455	30		T475	2
values[48]	270	1			T555	1		T455	11		T475	3
values[49]	270	1			T555	1		T455	19		T475	3
values[50]	244	1			T555	1		T455	6		T475	4
values[51]	254	1			T555	1		T455	8		T475	2
values[52]	273	1			T555	1		T455	8		T475	1
values[53]	212	1			T555	1		T455	2		T475	3
values[54]	220	1			T555	1		T475	3		T703	7
values[55]	218	1			T555	1		T475	1		T703	3
values[56]	199	1			T555	1		T475	1		T703	10
values[57]	243	1			T555	1		T475	1		T703	15
values[58]	206	1			T555	1		T475	2		T703	3
values[59]	195	1			T555	1		T475	2		T703	2
values[60]	177	1			T555	1		T475	4		T700	3
values[61]	162	1			T555	1		T475	1		T700	6
values[62]	146	1			T555	1		T475	1		T700	5
values[63]	145	1			T555	1		T475	2		T700	2
values[64]	134	1			T555	1		T475	4		T700	1
values[65]	161	1			T555	1		T475	5		T700	2
values[66]	119	1			T555	1		T475	3		T700	3
values[67]	119	1			T555	1		T475	3		T700	3
values[68]	137	1			T555	2		T475	1		T700	2
values[69]	137	1			T555	1		T475	5		T700	3
values[70]	121	1			T555	1		T475	3		T700	4
values[71]	125	1			T555	1		T475	1		T700	6
values[72]	90	1			T555	1		T475	2		T700	5
values[73]	113	1			T555	1		T475	9		T700	4
values[74]	100	1			T555	1		T475	4		T700	4
values[75]	84	1			T555	1		T475	3		T700	2
values[76]	114	1			T555	1		T475	3		T700	6
values[77]	98	1			T555	1		T475	3		T700	3
values[78]	117	1			T555	1		T475	2		T700	2
values[79]	101	1			T555	1		T475	3		T700	3
values[80]	75	1			T555	2		T475	1		T700	1
values[81]	81	1			T555	1		T475	1		T700	4
values[82]	74	1			T555	1		T475	2		T700	4
values[83]	71	1			T555	1		T475	2		T700	4
values[84]	59	1			T555	1		T475	2		T700	2
values[85]	82	1			T555	1		T475	1		T700	1
values[86]	65	1			T555	1		T475	1		T700	3
values[87]	76	1			T555	1		T475	1		T700	3
values[88]	103	1			T555	1		T475	5		T700	12
values[89]	91	1			T555	1		T475	1		T700	16
values[90]	72	1			T555	1		T475	6		T700	5
values[91]	69	1			T555	1		T475	2		T700	6
values[92]	71	1			T555	1		T475	2		T700	6
values[93]	79	1			T555	1		T475	4		T700	14
values[94]	77	1			T555	1		T475	2		T700	6
values[95]	69	1			T555	1		T475	4		T700	2
values[96]	55	1			T555	1		T475	3		T700	2
values[97]	76	1			T555	1		T475	3		T700	3
values[98]	62	1			T555	1		T475	8		T700	2
values[99]	61	1			T555	1		T475	1		T700	2
values[100]	75	1			T555	1		T475	2		T700	3
values[101]	89	1			T555	1		T475	4		T700	10
values[102]	70	1			T555	1		T475	4		T700	4
values[103]	59	1			T555	2		T475	3		T700	1
values[104]	67	1			T555	1		T475	5		T700	4
values[105]	62	1			T555	1		T475	2		T700	1
values[106]	66	1			T555	1		T475	4		T700	3
values[107]	68	1			T555	1		T475	5		T700	4
values[108]	51	1			T555	1		T475	2		T700	4
values[109]	62	1			T555	1		T475	5		T700	9
values[110]	75	1			T555	1		T475	7		T700	8
values[111]	59	1			T555	1		T475	3		T700	8
values[112]	71	1			T555	1		T475	2		T700	10
values[113]	71	1			T555	1		T475	3		T700	6
values[114]	54	1			T555	1		T475	2		T700	5
values[115]	59	1			T555	1		T475	4		T700	4
values[116]	63	1			T555	1		T475	8		T700	3
values[117]	67	1			T555	3		T475	7		T700	2
values[118]	78	1			T555	1		T475	7		T700	8
values[119]	84	1			T555	2		T475	8		T700	13
values[120]	75	1			T555	2		T475	5		T700	6
values[121]	88	1			T555	1		T475	3		T700	4
values[122]	66	1			T555	1		T475	4		T700	8
values[123]	58	1			T555	2		T475	2		T700	3
values[124]	62	1			T555	3		T475	4		T845	4
values[125]	67	1			T555	1		T475	6		T845	1
values[126]	143	1			T555	3		T475	34		T845	5
values[127]	793	1			T555	31		T475	84		T845	30
values[128]	6340	1			T555	299		T475	32		T845	334