Unified Coverage Report :: Group Instance : sensor_ctrl

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T77	1	T123	1	T553	1
small_delay	637	1		T78	1	T79	1	T266	1
zero	663	1		T84	1	T447	1	T254	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T123	1	T766	1	T551	1
small_delay	937	1		T77	1	T78	1	T79	1
zero	663	1		T84	1	T447	1	T254	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T77	1	T123	1	T553	1
small_delay	637	1		T78	1	T79	1	T266	1
zero	663	1		T84	1	T447	1	T254	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T123	1	T766	1	T551	1
small_delay	937	1		T77	1	T78	1	T79	1
zero	663	1		T84	1	T447	1	T254	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T77	1	T123	1	T553	1
small_delay	637	1		T78	1	T79	1	T266	1
zero	663	1		T84	1	T447	1	T254	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T123	1	T766	1	T551	1
small_delay	937	1		T77	1	T78	1	T79	1
zero	663	1		T84	1	T447	1	T254	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T77	1	T123	1	T553	1
small_delay	637	1		T78	1	T79	1	T266	1
zero	663	1		T84	1	T447	1	T254	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T123	1	T766	1	T551	1
small_delay	937	1		T77	1	T78	1	T79	1
zero	663	1		T84	1	T447	1	T254	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T77	1	T123	1	T553	1
small_delay	637	1		T78	1	T79	1	T266	1
zero	663	1		T84	1	T447	1	T254	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T123	1	T766	1	T551	1
small_delay	937	1		T77	1	T78	1	T79	1
zero	663	1		T84	1	T447	1	T254	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T77	1	T123	1	T553	1
small_delay	637	1		T78	1	T79	1	T266	1
zero	663	1		T84	1	T447	1	T254	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T123	1	T766	1	T551	1
small_delay	937	1		T77	1	T78	1	T79	1
zero	663	1		T84	1	T447	1	T254	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T77	1	T123	1	T553	1
small_delay	637	1		T78	1	T79	1	T266	1
zero	663	1		T84	1	T447	1	T254	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T123	1	T766	1	T551	1
small_delay	937	1		T77	1	T78	1	T79	1
zero	663	1		T84	1	T447	1	T254	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T77	1	T123	1	T553	1
small_delay	637	1		T78	1	T79	1	T266	1
zero	663	1		T84	1	T447	1	T254	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T123	1	T766	1	T551	1
small_delay	937	1		T77	1	T78	1	T79	1
zero	663	1		T84	1	T447	1	T254	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T77	1	T123	1	T553	1
small_delay	637	1		T78	1	T79	1	T266	1
zero	663	1		T84	1	T447	1	T254	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T123	1	T766	1	T551	1
small_delay	937	1		T77	1	T78	1	T79	1
zero	663	1		T84	1	T447	1	T254	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T77	1	T123	1	T553	1
small_delay	637	1		T78	1	T79	1	T266	1
zero	663	1		T84	1	T447	1	T254	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T123	1	T766	1	T551	1
small_delay	937	1		T77	1	T78	1	T79	1
zero	663	1		T84	1	T447	1	T254	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T77	1	T123	1	T553	1
small_delay	637	1		T78	1	T79	1	T266	1
zero	663	1		T84	1	T447	1	T254	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T123	1	T766	1	T551	1
small_delay	937	1		T77	1	T78	1	T79	1
zero	663	1		T84	1	T447	1	T254	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T77	1	T123	1	T553	1
small_delay	637	1		T78	1	T79	1	T266	1
zero	663	1		T84	1	T447	1	T254	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T123	1	T766	1	T551	1
small_delay	937	1		T77	1	T78	1	T79	1
zero	663	1		T84	1	T447	1	T254	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T77	1	T123	1	T553	1
small_delay	637	1		T78	1	T79	1	T266	1
zero	663	1		T84	1	T447	1	T254	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T123	1	T766	1	T551	1
small_delay	937	1		T77	1	T78	1	T79	1
zero	663	1		T84	1	T447	1	T254	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T77	1	T123	1	T553	1
small_delay	637	1		T78	1	T79	1	T266	1
zero	663	1		T84	1	T447	1	T254	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T123	1	T766	1	T551	1
small_delay	937	1		T77	1	T78	1	T79	1
zero	663	1		T84	1	T447	1	T254	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T77	1	T123	1	T553	1
small_delay	637	1		T78	1	T79	1	T266	1
zero	663	1		T84	1	T447	1	T254	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T123	1	T766	1	T551	1
small_delay	937	1		T77	1	T78	1	T79	1
zero	663	1		T84	1	T447	1	T254	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T77	1	T123	1	T553	1
small_delay	637	1		T78	1	T79	1	T266	1
zero	663	1		T84	1	T447	1	T254	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T123	1	T766	1	T551	1
small_delay	937	1		T77	1	T78	1	T79	1
zero	663	1		T84	1	T447	1	T254	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T77	1	T123	1	T553	1
small_delay	637	1		T78	1	T79	1	T266	1
zero	663	1		T84	1	T447	1	T254	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T123	1	T766	1	T551	1
small_delay	937	1		T77	1	T78	1	T79	1
zero	663	1		T84	1	T447	1	T254	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T77	1	T123	1	T553	1
small_delay	637	1		T78	1	T79	1	T266	1
zero	663	1		T84	1	T447	1	T254	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T123	1	T766	1	T551	1
small_delay	937	1		T77	1	T78	1	T79	1
zero	663	1		T84	1	T447	1	T254	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T77	1	T123	1	T553	1
small_delay	637	1		T78	1	T79	1	T266	1
zero	663	1		T84	1	T447	1	T254	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T123	1	T766	1	T551	1
small_delay	937	1		T77	1	T78	1	T79	1
zero	663	1		T84	1	T447	1	T254	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T77	1	T123	1	T553	1
small_delay	637	1		T78	1	T79	1	T266	1
zero	663	1		T84	1	T447	1	T254	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T123	1	T766	1	T551	1
small_delay	937	1		T77	1	T78	1	T79	1
zero	663	1		T84	1	T447	1	T254	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T77	1	T123	1	T553	1
small_delay	637	1		T78	1	T79	1	T266	1
zero	663	1		T84	1	T447	1	T254	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T123	1	T766	1	T551	1
small_delay	937	1		T77	1	T78	1	T79	1
zero	663	1		T84	1	T447	1	T254	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T77	1	T123	1	T553	1
small_delay	637	1		T78	1	T79	1	T266	1
zero	663	1		T84	1	T447	1	T254	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T123	1	T766	1	T551	1
small_delay	937	1		T77	1	T78	1	T79	1
zero	663	1		T84	1	T447	1	T254	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T77	1	T123	1	T553	1
small_delay	637	1		T78	1	T79	1	T266	1
zero	663	1		T84	1	T447	1	T254	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T123	1	T766	1	T551	1
small_delay	937	1		T77	1	T78	1	T79	1
zero	663	1		T84	1	T447	1	T254	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T77	1	T123	1	T553	1
small_delay	637	1		T78	1	T79	1	T266	1
zero	663	1		T84	1	T447	1	T254	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T123	1	T766	1	T551	1
small_delay	937	1		T77	1	T78	1	T79	1
zero	663	1		T84	1	T447	1	T254	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T77	1	T123	1	T553	1
small_delay	637	1		T78	1	T79	1	T266	1
zero	663	1		T84	1	T447	1	T254	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T123	1	T766	1	T551	1
small_delay	937	1		T77	1	T78	1	T79	1
zero	663	1		T84	1	T447	1	T254	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T77	1	T123	1	T553	1
small_delay	637	1		T78	1	T79	1	T266	1
zero	663	1		T84	1	T447	1	T254	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T123	1	T766	1	T551	1
small_delay	937	1		T77	1	T78	1	T79	1
zero	663	1		T84	1	T447	1	T254	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T77	1	T123	1	T553	1
small_delay	637	1		T78	1	T79	1	T266	1
zero	663	1		T84	1	T447	1	T254	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T123	1	T766	1	T551	1
small_delay	937	1		T77	1	T78	1	T79	1
zero	663	1		T84	1	T447	1	T254	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T77	1	T123	1	T553	1
small_delay	637	1		T78	1	T79	1	T266	1
zero	663	1		T84	1	T447	1	T254	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T123	1	T766	1	T551	1
small_delay	937	1		T77	1	T78	1	T79	1
zero	663	1		T84	1	T447	1	T254	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T77	1	T123	1	T553	1
small_delay	637	1		T78	1	T79	1	T266	1
zero	663	1		T84	1	T447	1	T254	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T123	1	T766	1	T551	1
small_delay	937	1		T77	1	T78	1	T79	1
zero	663	1		T84	1	T447	1	T254	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T77	1	T123	1	T553	1
small_delay	637	1		T78	1	T79	1	T266	1
zero	663	1		T84	1	T447	1	T254	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T123	1	T766	1	T551	1
small_delay	937	1		T77	1	T78	1	T79	1
zero	663	1		T84	1	T447	1	T254	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T77	1	T123	1	T553	1
small_delay	637	1		T78	1	T79	1	T266	1
zero	663	1		T84	1	T447	1	T254	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T123	1	T766	1	T551	1
small_delay	937	1		T77	1	T78	1	T79	1
zero	663	1		T84	1	T447	1	T254	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T77	1	T123	1	T553	1
small_delay	637	1		T78	1	T79	1	T266	1
zero	663	1		T84	1	T447	1	T254	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T123	1	T766	1	T551	1
small_delay	937	1		T77	1	T78	1	T79	1
zero	663	1		T84	1	T447	1	T254	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T123	1	T766	1	T551	1
small_delay	937	1		T77	1	T78	1	T79	1
zero	663	1		T84	1	T447	1	T254	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T77	1	T123	1	T553	1
small_delay	637	1		T78	1	T79	1	T266	1
zero	663	1		T84	1	T447	1	T254	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T123	1	T766	1	T551	1
small_delay	937	1		T77	1	T78	1	T79	1
zero	663	1		T84	1	T447	1	T254	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T77	1	T123	1	T553	1
small_delay	637	1		T78	1	T79	1	T266	1
zero	663	1		T84	1	T447	1	T254	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T77	1	T123	1	T553	1
small_delay	637	1		T78	1	T79	1	T266	1
zero	663	1		T84	1	T447	1	T254	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T123	1	T766	1	T551	1
small_delay	937	1		T77	1	T78	1	T79	1
zero	663	1		T84	1	T447	1	T254	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T77	1	T123	1	T553	1
small_delay	637	1		T78	1	T79	1	T266	1
zero	663	1		T84	1	T447	1	T254	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T123	1	T766	1	T551	1
small_delay	937	1		T77	1	T78	1	T79	1
zero	663	1		T84	1	T447	1	T254	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T123	1	T766	1	T551	1
small_delay	937	1		T77	1	T78	1	T79	1
zero	663	1		T84	1	T447	1	T254	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T77	1	T123	1	T553	1
small_delay	637	1		T78	1	T79	1	T266	1
zero	663	1		T84	1	T447	1	T254	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T77	1	T123	1	T553	1
small_delay	637	1		T78	1	T79	1	T266	1
zero	663	1		T84	1	T447	1	T254	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T123	1	T766	1	T551	1
small_delay	937	1		T77	1	T78	1	T79	1
zero	663	1		T84	1	T447	1	T254	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T77	1	T123	1	T553	1
small_delay	637	1		T78	1	T79	1	T266	1
zero	663	1		T84	1	T447	1	T254	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T123	1	T766	1	T551	1
small_delay	937	1		T77	1	T78	1	T79	1
zero	663	1		T84	1	T447	1	T254	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T77	1	T123	1	T553	1
small_delay	637	1		T78	1	T79	1	T266	1
zero	663	1		T84	1	T447	1	T254	1