Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	50	0	50	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	50	0	50	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	50	0	50	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	468	1			T79	1		T555	1		T767	1
all_values[1]	481	1			T79	1		T490	1		T555	1
all_values[2]	456	1			T899	1		T455	1		T475	1
all_values[3]	460	1			T79	1		T254	1		T490	2
all_values[4]	508	1			T490	1		T455	1		T703	2
all_values[5]	472	1			T490	1		T550	1		T767	1
all_values[6]	474	1			T79	1		T449	1		T899	1
all_values[7]	429	1			T254	1		T449	1		T844	1
all_values[8]	479	1			T556	1		T840	1		T701	7
all_values[9]	442	1			T79	1		T555	1		T701	5
all_values[10]	462	1			T254	2		T455	2		T701	3
all_values[11]	488	1			T79	3		T550	1		T908	1
all_values[12]	489	1			T79	1		T254	1		T490	1
all_values[13]	475	1			T555	1		T899	1		T455	2
all_values[14]	469	1			T490	1		T455	2		T837	1
all_values[15]	471	1			T254	2		T490	1		T449	1
all_values[16]	471	1			T547	2		T556	1		T767	1
all_values[17]	445	1			T79	2		T490	1		T832	1
all_values[18]	455	1			T79	3		T490	1		T556	1
all_values[19]	451	1			T254	1		T547	1		T556	1
all_values[20]	449	1			T79	3		T547	1		T556	1
all_values[21]	450	1			T79	1		T254	1		T490	1
all_values[22]	467	1			T79	1		T254	1		T550	1
all_values[23]	466	1			T550	2		T899	1		T455	1
all_values[24]	455	1			T79	1		T490	1		T556	1
all_values[25]	486	1			T490	1		T556	1		T550	1
all_values[26]	510	1			T254	1		T550	1		T767	1
all_values[27]	465	1			T490	2		T556	1		T449	1
all_values[28]	491	1			T547	2		T490	2		T555	1
all_values[29]	468	1			T547	1		T490	1		T556	3
all_values[30]	484	1			T254	1		T556	1		T455	3
all_values[31]	420	1			T79	1		T490	1		T550	1
all_values[32]	468	1			T254	1		T547	1		T490	1
all_values[33]	439	1			T254	1		T490	1		T550	1
all_values[34]	448	1			T79	2		T254	1		T490	2
all_values[35]	487	1			T79	1		T449	1		T455	1
all_values[36]	491	1			T455	3		T475	1		T703	1
all_values[37]	466	1			T254	1		T556	1		T767	1
all_values[38]	471	1			T79	1		T449	1		T899	2
all_values[39]	474	1			T490	1		T908	1		T455	1
all_values[40]	477	1			T79	3		T449	1		T844	1
all_values[41]	461	1			T547	1		T550	1		T844	1
all_values[42]	428	1			T79	1		T556	1		T455	3
all_values[43]	475	1			T79	2		T547	2		T455	1
all_values[44]	462	1			T547	1		T550	1		T899	1
all_values[45]	463	1			T79	1		T490	1		T449	1
all_values[46]	457	1			T547	2		T449	1		T475	1
all_values[47]	483	1			T79	1		T490	1		T556	1
all_values[48]	448	1			T455	2		T832	2		T833	1
all_values[49]	522	1			T490	2		T555	1		T449	1