Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	3553	1			T79	21		T266	6		T490	10
all_values[1]	3606	1			T79	19		T266	14		T254	1
all_values[2]	3557	1			T78	1		T79	19		T266	14
all_values[3]	3642	1			T79	21		T266	5		T490	12
all_values[4]	3585	1			T79	15		T266	8		T254	1
all_values[5]	3640	1			T79	16		T266	8		T254	1
all_values[6]	3535	1			T79	27		T266	14		T490	8
all_values[7]	3632	1			T78	1		T79	27		T266	14
all_values[8]	3588	1			T78	1		T79	19		T266	7
all_values[9]	3590	1			T79	14		T266	12		T254	1
all_values[10]	3523	1			T78	1		T79	17		T266	4
all_values[11]	3526	1			T78	2		T79	16		T266	12
all_values[12]	3544	1			T78	1		T79	19		T266	8
all_values[13]	3605	1			T79	23		T266	10		T254	1
all_values[14]	3595	1			T78	1		T79	16		T266	12
all_values[15]	3674	1			T78	1		T79	18		T266	7
all_values[16]	3589	1			T79	19		T266	13		T490	5
all_values[17]	3653	1			T79	18		T266	8		T254	1
all_values[18]	3638	1			T78	3		T79	18		T266	7
all_values[19]	3680	1			T78	1		T79	18		T266	11
all_values[20]	3709	1			T78	1		T79	25		T266	6
all_values[21]	3705	1			T79	26		T266	11		T254	2
all_values[22]	3551	1			T78	2		T79	25		T266	10
all_values[23]	3613	1			T79	24		T266	15		T490	5
all_values[24]	3626	1			T79	13		T266	11		T254	1
all_values[25]	3593	1			T78	1		T79	17		T266	8
all_values[26]	3709	1			T79	24		T266	6		T254	1
all_values[27]	3594	1			T79	24		T266	11		T254	1
all_values[28]	3493	1			T78	1		T79	17		T266	11
all_values[29]	3585	1			T79	30		T266	11		T490	12
all_values[30]	3595	1			T79	19		T266	10		T254	3
all_values[31]	3559	1			T79	22		T266	6		T254	2
all_values[32]	3656	1			T78	1		T79	27		T266	14
all_values[33]	3599	1			T79	21		T266	8		T254	2
all_values[34]	3609	1			T78	3		T79	22		T266	10
all_values[35]	3581	1			T78	1		T79	20		T266	12
all_values[36]	3627	1			T78	1		T79	19		T266	9
all_values[37]	3732	1			T79	22		T266	11		T254	1
all_values[38]	3643	1			T78	3		T79	16		T266	10
all_values[39]	3629	1			T78	3		T79	16		T266	7
all_values[40]	3650	1			T79	26		T266	6		T490	8
all_values[41]	3441	1			T79	25		T266	8		T490	19
all_values[42]	3611	1			T78	3		T79	15		T266	7
all_values[43]	3641	1			T79	24		T266	5		T254	2
all_values[44]	3634	1			T78	1		T79	21		T266	10
all_values[45]	3602	1			T78	4		T79	18		T266	7
all_values[46]	3658	1			T78	1		T79	19		T266	7
all_values[47]	3623	1			T79	27		T266	5		T254	2
all_values[48]	3525	1			T79	26		T266	9		T490	13
all_values[49]	3676	1			T78	2		T79	24		T266	11
all_values[50]	3653	1			T78	1		T79	26		T266	15
all_values[51]	3620	1			T78	1		T79	35		T266	6
all_values[52]	3586	1			T78	1		T79	26		T266	12
all_values[53]	3604	1			T79	20		T266	10		T490	14
all_values[54]	3581	1			T78	1		T79	16		T266	12
all_values[55]	3676	1			T79	15		T266	14		T490	16
all_values[56]	3637	1			T79	18		T266	7		T490	7
all_values[57]	3693	1			T78	1		T79	22		T266	4
all_values[58]	3625	1			T79	29		T266	12		T490	10
all_values[59]	3528	1			T78	3		T79	21		T266	4
all_values[60]	3597	1			T79	29		T266	4		T254	1
all_values[61]	3641	1			T79	15		T266	12		T254	1
all_values[62]	3557	1			T79	24		T266	10		T254	3
all_values[63]	3683	1			T78	1		T79	11		T266	7