c8985d6745| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | chip_sw_example_tests | chip_sw_example_flash | 3.883m | 3.576ms | 3 | 3 | 100.00 |
| chip_sw_example_rom | 2.351m | 2.480ms | 3 | 3 | 100.00 | ||
| chip_sw_example_manufacturer | 4.447m | 2.729ms | 3 | 3 | 100.00 | ||
| chip_sw_example_concurrency | 5.127m | 3.496ms | 3 | 3 | 100.00 | ||
| V1 | csr_hw_reset | chip_csr_hw_reset | 0 | 5 | 0.00 | ||
| V1 | csr_rw | chip_csr_rw | 0 | 20 | 0.00 | ||
| V1 | csr_bit_bash | chip_csr_bit_bash | 0 | 5 | 0.00 | ||
| V1 | csr_aliasing | chip_csr_aliasing | 0 | 5 | 0.00 | ||
| V1 | csr_mem_rw_with_rand_reset | chip_csr_mem_rw_with_rand_reset | 0 | 20 | 0.00 | ||
| V1 | regwen_csr_and_corresponding_lockable_csr | chip_csr_aliasing | 0 | 5 | 0.00 | ||
| chip_csr_rw | 0 | 20 | 0.00 | ||||
| V1 | xbar_smoke | xbar_smoke | 0 | 100 | 0.00 | ||
| V1 | chip_sw_gpio_out | chip_sw_gpio | 8.441m | 4.543ms | 3 | 3 | 100.00 |
| V1 | chip_sw_gpio_in | chip_sw_gpio | 8.441m | 4.543ms | 3 | 3 | 100.00 |
| V1 | chip_sw_gpio_irq | chip_sw_gpio | 8.441m | 4.543ms | 3 | 3 | 100.00 |
| V1 | chip_sw_uart_tx_rx | chip_sw_uart_tx_rx | 11.944m | 4.505ms | 5 | 5 | 100.00 |
| V1 | chip_sw_uart_rx_overflow | chip_sw_uart_tx_rx | 11.944m | 4.505ms | 5 | 5 | 100.00 |
| chip_sw_uart_tx_rx_idx1 | 12.055m | 4.110ms | 5 | 5 | 100.00 | ||
| chip_sw_uart_tx_rx_idx2 | 12.459m | 3.974ms | 5 | 5 | 100.00 | ||
| chip_sw_uart_tx_rx_idx3 | 13.341m | 3.857ms | 5 | 5 | 100.00 | ||
| V1 | chip_sw_uart_baud_rate | chip_sw_uart_rand_baudrate | 48.373m | 13.881ms | 20 | 20 | 100.00 |
| V1 | chip_sw_uart_tx_rx_alt_clk_freq | chip_sw_uart_tx_rx_alt_clk_freq | 41.870m | 13.378ms | 5 | 5 | 100.00 |
| chip_sw_uart_tx_rx_alt_clk_freq_low_speed | 13.127m | 8.644ms | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 65 | 220 | 29.55 | |||
| V2 | chip_pin_mux | chip_padctrl_attributes | 6.131m | 6.197ms | 10 | 10 | 100.00 |
| V2 | chip_padctrl_attributes | chip_padctrl_attributes | 6.131m | 6.197ms | 10 | 10 | 100.00 |
| V2 | chip_sw_sleep_pin_mio_dio_val | chip_sw_sleep_pin_mio_dio_val | 5.581m | 3.437ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sleep_pin_wake | chip_sw_sleep_pin_wake | 6.729m | 5.680ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sleep_pin_retention | chip_sw_sleep_pin_retention | 4.932m | 3.005ms | 3 | 3 | 100.00 |
| V2 | chip_sw_tap_strap_sampling | chip_tap_straps_dev | 18.132m | 9.328ms | 5 | 5 | 100.00 |
| chip_tap_straps_testunlock0 | 11.620m | 7.155ms | 5 | 5 | 100.00 | ||
| chip_tap_straps_rma | 1.594h | 60.000ms | 4 | 5 | 80.00 | ||
| chip_tap_straps_prod | 28.542m | 13.813ms | 5 | 5 | 100.00 | ||
| V2 | chip_sw_pattgen_ios | chip_sw_pattgen_ios | 5.072m | 3.864ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sleep_pwm_pulses | chip_sw_sleep_pwm_pulses | 21.402m | 8.945ms | 3 | 3 | 100.00 |
| V2 | chip_sw_data_integrity | chip_sw_data_integrity_escalation | 13.666m | 5.572ms | 6 | 6 | 100.00 |
| V2 | chip_sw_instruction_integrity | chip_sw_data_integrity_escalation | 13.666m | 5.572ms | 6 | 6 | 100.00 |
| V2 | chip_sw_ast_clk_outputs | chip_sw_ast_clk_outputs | 16.081m | 8.565ms | 3 | 3 | 100.00 |
| V2 | chip_sw_ast_clk_rst_inputs | chip_sw_ast_clk_rst_inputs | 1.230h | 23.773ms | 3 | 3 | 100.00 |
| V2 | chip_sw_ast_sys_clk_jitter | chip_sw_flash_ctrl_ops_jitter_en | 13.946m | 4.562ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_access_jitter_en | 17.079m | 6.286ms | 3 | 3 | 100.00 | ||
| chip_sw_otbn_ecdsa_op_irq_jitter_en | 1.157h | 18.994ms | 3 | 3 | 100.00 | ||
| chip_sw_aes_enc_jitter_en | 6.139m | 2.996ms | 3 | 3 | 100.00 | ||
| chip_sw_edn_entropy_reqs_jitter | 18.755m | 7.751ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_enc_jitter_en | 5.682m | 3.017ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation_jitter_en | 46.414m | 13.341ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en | 5.450m | 3.506ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 8.586m | 3.860ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_jitter | 5.635m | 2.728ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_ast_usb_clk_calib | chip_sw_usb_ast_clk_calib | 4.972m | 3.059ms | 1 | 1 | 100.00 |
| V2 | chip_sw_sensor_ctrl_ast_alerts | chip_sw_sensor_ctrl_alert | 19.591m | 6.956ms | 5 | 5 | 100.00 |
| chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup | 9.575m | 5.094ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_sensor_ctrl_ast_status | chip_sw_sensor_ctrl_status | 5.394m | 2.822ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup | chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup | 9.575m | 5.094ms | 3 | 3 | 100.00 |
| V2 | chip_sw_smoketest | chip_sw_flash_scrambling_smoketest | 4.942m | 3.176ms | 3 | 3 | 100.00 |
| chip_sw_aes_smoketest | 5.764m | 2.819ms | 3 | 3 | 100.00 | ||
| chip_sw_aon_timer_smoketest | 5.606m | 2.961ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_smoketest | 6.326m | 3.293ms | 3 | 3 | 100.00 | ||
| chip_sw_csrng_smoketest | 4.160m | 2.700ms | 3 | 3 | 100.00 | ||
| chip_sw_entropy_src_smoketest | 9.369m | 3.880ms | 3 | 3 | 100.00 | ||
| chip_sw_gpio_smoketest | 4.672m | 3.409ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_smoketest | 7.799m | 3.851ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_smoketest | 5.874m | 3.298ms | 3 | 3 | 100.00 | ||
| chip_sw_otbn_smoketest | 38.818m | 9.652ms | 3 | 3 | 100.00 | ||
| chip_sw_pwrmgr_smoketest | 8.629m | 5.873ms | 3 | 3 | 100.00 | ||
| chip_sw_pwrmgr_usbdev_smoketest | 7.800m | 6.078ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_plic_smoketest | 4.332m | 3.190ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_timer_smoketest | 6.294m | 3.788ms | 3 | 3 | 100.00 | ||
| chip_sw_rstmgr_smoketest | 5.479m | 2.742ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_smoketest | 4.723m | 2.753ms | 3 | 3 | 100.00 | ||
| chip_sw_uart_smoketest | 5.043m | 2.641ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_otp_smoketest | chip_sw_otp_ctrl_smoketest | 5.055m | 3.165ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rom_functests | rom_keymgr_functest | 9.202m | 5.581ms | 3 | 3 | 100.00 |
| V2 | chip_sw_boot | chip_sw_uart_tx_rx_bootstrap | 4.280h | 77.303ms | 3 | 3 | 100.00 |
| V2 | chip_sw_secure_boot | rom_e2e_smoke | 1.038h | 14.732ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rom_raw_unlock | rom_raw_unlock | 4.308m | 5.143ms | 3 | 3 | 100.00 |
| V2 | chip_sw_power_idle_load | chip_sw_power_idle_load | 13.131m | 4.328ms | 3 | 3 | 100.00 |
| V2 | chip_sw_power_sleep_load | chip_sw_power_sleep_load | 10.597m | 10.199ms | 3 | 3 | 100.00 |
| V2 | chip_sw_exit_test_unlocked_bootstrap | chip_sw_exit_test_unlocked_bootstrap | 3.307h | 58.052ms | 3 | 3 | 100.00 |
| V2 | chip_sw_inject_scramble_seed | chip_sw_inject_scramble_seed | 3.372h | 64.335ms | 3 | 3 | 100.00 |
| V2 | tl_d_oob_addr_access | chip_tl_errors | 0 | 30 | 0.00 | ||
| V2 | tl_d_illegal_access | chip_tl_errors | 0 | 30 | 0.00 | ||
| V2 | tl_d_outstanding_access | chip_csr_aliasing | 0 | 5 | 0.00 | ||
| chip_same_csr_outstanding | 0 | 20 | 0.00 | ||||
| chip_csr_hw_reset | 0 | 5 | 0.00 | ||||
| chip_csr_rw | 0 | 20 | 0.00 | ||||
| V2 | tl_d_partial_access | chip_csr_aliasing | 0 | 5 | 0.00 | ||
| chip_same_csr_outstanding | 0 | 20 | 0.00 | ||||
| chip_csr_hw_reset | 0 | 5 | 0.00 | ||||
| chip_csr_rw | 0 | 20 | 0.00 | ||||
| V2 | xbar_base_random_sequence | xbar_random | 0 | 100 | 0.00 | ||
| V2 | xbar_random_delay | xbar_smoke_zero_delays | 0 | 100 | 0.00 | ||
| xbar_smoke_large_delays | 0 | 100 | 0.00 | ||||
| xbar_smoke_slow_rsp | 0 | 100 | 0.00 | ||||
| xbar_random_zero_delays | 0 | 100 | 0.00 | ||||
| xbar_random_large_delays | 0 | 100 | 0.00 | ||||
| xbar_random_slow_rsp | 0 | 100 | 0.00 | ||||
| V2 | xbar_unmapped_address | xbar_unmapped_addr | 0 | 100 | 0.00 | ||
| xbar_error_and_unmapped_addr | 0 | 100 | 0.00 | ||||
| V2 | xbar_error_cases | xbar_error_random | 0 | 100 | 0.00 | ||
| xbar_error_and_unmapped_addr | 0 | 100 | 0.00 | ||||
| V2 | xbar_all_access_same_device | xbar_access_same_device | 0 | 100 | 0.00 | ||
| xbar_access_same_device_slow_rsp | 0 | 100 | 0.00 | ||||
| V2 | xbar_all_hosts_use_same_source_id | xbar_same_source | 0 | 100 | 0.00 | ||
| V2 | xbar_stress_all | xbar_stress_all | 0 | 100 | 0.00 | ||
| xbar_stress_all_with_error | 0 | 100 | 0.00 | ||||
| V2 | xbar_stress_with_reset | xbar_stress_all_with_rand_reset | 0 | 100 | 0.00 | ||
| xbar_stress_all_with_reset_error | 0 | 100 | 0.00 | ||||
| V2 | rom_e2e_smoke | rom_e2e_smoke | 1.038h | 14.732ms | 3 | 3 | 100.00 |
| V2 | rom_e2e_shutdown_output | rom_e2e_shutdown_output | 1.067h | 26.445ms | 3 | 3 | 100.00 |
| V2 | rom_e2e_shutdown_exception_c | rom_e2e_shutdown_exception_c | 1.135h | 14.384ms | 3 | 3 | 100.00 |
| V2 | rom_e2e_boot_policy_valid | rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 | 53.420m | 11.606ms | 1 | 1 | 100.00 |
| rom_e2e_boot_policy_valid_a_good_b_good_dev | 1.178h | 15.264ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_good_prod | 1.184h | 16.195ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_good_prod_end | 1.123h | 15.725ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_good_rma | 1.121h | 15.562ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 | 51.410m | 11.363ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_dev | 1.041h | 15.419ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_prod | 1.116h | 15.397ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_prod_end | 1.178h | 15.349ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_rma | 58.530m | 15.230ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 | 1.529h | 18.776ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_dev | 1.939h | 24.413ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_prod | 1.762h | 24.055ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_prod_end | 1.775h | 24.154ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_rma | 1.588h | 23.119ms | 1 | 1 | 100.00 | ||
| V2 | rom_e2e_sigverify_always | rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 | 1.221h | 17.556ms | 1 | 1 | 100.00 |
| rom_e2e_sigverify_always_a_bad_b_bad_dev | 1.554h | 23.443ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_bad_prod | 1.555h | 23.213ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_bad_prod_end | 1.817h | 23.217ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_bad_rma | 1.556h | 22.277ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 | 49.164m | 11.544ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_dev | 1.033h | 14.461ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_prod | 1.049h | 15.272ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_prod_end | 1.143h | 14.791ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_rma | 1.210h | 14.372ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 | 51.343m | 11.598ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_dev | 57.106m | 14.417ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_prod | 1.111h | 15.209ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_prod_end | 1.135h | 14.263ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_rma | 1.030h | 13.703ms | 1 | 1 | 100.00 | ||
| V2 | rom_e2e_asm_init | rom_e2e_asm_init_test_unlocked0 | 55.055m | 11.985ms | 3 | 3 | 100.00 |
| rom_e2e_asm_init_dev | 1.353h | 16.157ms | 3 | 3 | 100.00 | ||
| rom_e2e_asm_init_prod | 1.048h | 14.931ms | 3 | 3 | 100.00 | ||
| rom_e2e_asm_init_prod_end | 1.209h | 15.627ms | 3 | 3 | 100.00 | ||
| rom_e2e_asm_init_rma | 1.010h | 14.889ms | 3 | 3 | 100.00 | ||
| V2 | rom_e2e_keymgr_init | rom_e2e_keymgr_init_rom_ext_meas | 1.117h | 14.994ms | 3 | 3 | 100.00 |
| rom_e2e_keymgr_init_rom_ext_no_meas | 1.131h | 15.401ms | 3 | 3 | 100.00 | ||
| rom_e2e_keymgr_init_rom_ext_invalid_meas | 1.085h | 14.876ms | 3 | 3 | 100.00 | ||
| V2 | rom_e2e_static_critical | rom_e2e_static_critical | 1.347h | 17.925ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aes_enc | chip_sw_aes_enc | 4.241m | 2.742ms | 3 | 3 | 100.00 |
| chip_sw_aes_enc_jitter_en | 6.139m | 2.996ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_aes_multi_block | chip_sw_aes_multi_block | 0 | 0 | -- | ||
| V2 | chip_sw_aes_interrupt_encryption | chip_sw_aes_interrupt_encryption | 0 | 0 | -- | ||
| V2 | chip_sw_aes_entropy | chip_sw_aes_entropy | 5.163m | 3.189ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aes_prng_reseed | chip_sw_aes_prng_reseed | 0 | 0 | -- | ||
| V2 | chip_sw_aes_force_prng_reseed | chip_sw_aes_force_prng_reseed | 0 | 0 | -- | ||
| V2 | chip_sw_aes_idle | chip_sw_aes_idle | 5.447m | 3.510ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aes_sideload | chip_sw_keymgr_sideload_aes | 45.271m | 14.252ms | 3 | 3 | 100.00 |
| V2 | chip_sw_adc_ctrl_debug_cable_irq | chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 7.847m | 19.104ms | 3 | 3 | 100.00 |
| V2 | chip_sw_adc_ctrl_sleep_debug_cable_wakeup | chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 7.847m | 19.104ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_wakeup_irq | chip_sw_aon_timer_irq | 6.520m | 3.330ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_sleep_wakeup | chip_sw_pwrmgr_smoketest | 8.629m | 5.873ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_wdog_bark_irq | chip_sw_aon_timer_irq | 6.520m | 3.330ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_wdog_bite_reset | chip_sw_aon_timer_wdog_bite_reset | 15.299m | 8.022ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_sleep_wdog_bite_reset | chip_sw_aon_timer_wdog_bite_reset | 15.299m | 8.022ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_sleep_wdog_sleep_pause | chip_sw_aon_timer_sleep_wdog_sleep_pause | 8.893m | 8.300ms | 5 | 5 | 100.00 |
| V2 | chip_sw_aon_timer_wdog_lc_escalate | chip_sw_aon_timer_wdog_lc_escalate | 12.772m | 5.029ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_idle_trans | chip_sw_otbn_randomness | 17.118m | 5.694ms | 3 | 3 | 100.00 |
| chip_sw_aes_idle | 5.447m | 3.510ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_enc_idle | 5.445m | 3.268ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_idle | 4.638m | 2.732ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_off_trans | chip_sw_clkmgr_off_aes_trans | 9.567m | 5.196ms | 3 | 3 | 100.00 |
| chip_sw_clkmgr_off_hmac_trans | 9.152m | 4.361ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_off_kmac_trans | 7.919m | 5.274ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_off_otbn_trans | 8.755m | 5.099ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_off_peri | chip_sw_clkmgr_off_peri | 28.190m | 11.141ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_div | chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 | 13.074m | 4.810ms | 3 | 3 | 100.00 |
| chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 | 12.368m | 5.036ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_dev | 10.872m | 3.753ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_dev | 11.643m | 4.900ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_rma | 12.848m | 4.473ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_rma | 10.653m | 4.731ms | 3 | 3 | 100.00 | ||
| chip_sw_ast_clk_outputs | 16.081m | 8.565ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_external_clk_src_for_lc | chip_sw_clkmgr_external_clk_src_for_lc | 16.315m | 12.153ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_external_clk_src_for_sw | chip_sw_clkmgr_external_clk_src_for_sw_fast_dev | 10.872m | 3.753ms | 3 | 3 | 100.00 |
| chip_sw_clkmgr_external_clk_src_for_sw_slow_dev | 11.643m | 4.900ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_jitter | chip_sw_flash_ctrl_ops_jitter_en | 13.946m | 4.562ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_access_jitter_en | 17.079m | 6.286ms | 3 | 3 | 100.00 | ||
| chip_sw_otbn_ecdsa_op_irq_jitter_en | 1.157h | 18.994ms | 3 | 3 | 100.00 | ||
| chip_sw_aes_enc_jitter_en | 6.139m | 2.996ms | 3 | 3 | 100.00 | ||
| chip_sw_edn_entropy_reqs_jitter | 18.755m | 7.751ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_enc_jitter_en | 5.682m | 3.017ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation_jitter_en | 46.414m | 13.341ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en | 5.450m | 3.506ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 8.586m | 3.860ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_jitter | 5.635m | 2.728ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_extended_range | chip_sw_clkmgr_jitter_reduced_freq | 4.844m | 2.996ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_ops_jitter_en_reduced_freq | 13.904m | 5.129ms | 3 | 3 | 100.00 | ||
| chip_sw_flash_ctrl_access_jitter_en_reduced_freq | 22.458m | 7.919ms | 3 | 3 | 100.00 | ||
| chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq | 1.200h | 25.059ms | 3 | 3 | 100.00 | ||
| chip_sw_aes_enc_jitter_en_reduced_freq | 5.083m | 2.578ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_enc_jitter_en_reduced_freq | 4.822m | 3.826ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation_jitter_en_reduced_freq | 36.304m | 11.724ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en_reduced_freq | 5.973m | 3.447ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq | 12.588m | 5.376ms | 3 | 3 | 100.00 | ||
| chip_sw_flash_init_reduced_freq | 31.580m | 25.986ms | 3 | 3 | 100.00 | ||
| chip_sw_csrng_edn_concurrency_reduced_freq | 1.645h | 31.250ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_deep_sleep_frequency | chip_sw_ast_clk_outputs | 16.081m | 8.565ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_sleep_frequency | chip_sw_clkmgr_sleep_frequency | 12.012m | 4.207ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_reset_frequency | chip_sw_clkmgr_reset_frequency | 10.362m | 3.134ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_escalation_reset | chip_sw_all_escalation_resets | 14.330m | 5.914ms | 99 | 100 | 99.00 |
| V2 | chip_sw_clkmgr_alert_handler_clock_enables | chip_sw_alert_handler_lpg_clkoff | 26.837m | 7.158ms | 3 | 3 | 100.00 |
| V2 | chip_sw_csrng_edn_cmd | chip_sw_entropy_src_csrng | 33.073m | 8.449ms | 3 | 3 | 100.00 |
| V2 | chip_sw_csrng_fuse_en_sw_app_read | chip_sw_csrng_fuse_en_sw_app_read_test | 8.718m | 3.859ms | 3 | 3 | 100.00 |
| V2 | chip_sw_csrng_lc_hw_debug_en | chip_sw_csrng_lc_hw_debug_en_test | 14.134m | 7.652ms | 3 | 3 | 100.00 |
| V2 | chip_sw_csrng_known_answer_tests | chip_sw_csrng_kat_test | 5.658m | 2.761ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_reset | chip_sw_pwrmgr_sysrst_ctrl_reset | 21.193m | 7.887ms | 3 | 3 | 100.00 |
| chip_sw_sysrst_ctrl_reset | 32.913m | 24.894ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_sysrst_ctrl_inputs | chip_sw_sysrst_ctrl_inputs | 6.307m | 3.453ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_outputs | chip_sw_sysrst_ctrl_outputs | 7.392m | 3.502ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_in_irq | chip_sw_sysrst_ctrl_in_irq | 12.081m | 5.041ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_sleep_wakeup | chip_sw_sysrst_ctrl_reset | 32.913m | 24.894ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_sleep_reset | chip_sw_sysrst_ctrl_reset | 32.913m | 24.894ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_ec_rst_l | chip_sw_sysrst_ctrl_ec_rst_l | 1.102h | 20.593ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_flash_wp_l | chip_sw_sysrst_ctrl_ec_rst_l | 1.102h | 20.593ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_ulp_z3_wakeup | chip_sw_sysrst_ctrl_ulp_z3_wakeup | 7.781m | 5.760ms | 3 | 3 | 100.00 |
| chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 7.847m | 19.104ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_edn_entropy_reqs | chip_sw_csrng_edn_concurrency | 2.505h | 41.088ms | 10 | 10 | 100.00 |
| chip_sw_entropy_src_ast_rng_req | 5.163m | 3.324ms | 3 | 3 | 100.00 | ||
| chip_sw_edn_entropy_reqs | 23.709m | 7.812ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_entropy_src_ast_rng_req | chip_sw_entropy_src_ast_rng_req | 5.163m | 3.324ms | 3 | 3 | 100.00 |
| V2 | chip_sw_entropy_src_csrng | chip_sw_entropy_src_csrng | 33.073m | 8.449ms | 3 | 3 | 100.00 |
| V2 | chip_sw_entropy_src_fuse_en_fw_read | chip_sw_entropy_src_fuse_en_fw_read_test | 0 | 0 | -- | ||
| V2 | chip_sw_entropy_src_known_answer_tests | chip_sw_entropy_src_kat_test | 3.392m | 2.863ms | 3 | 3 | 100.00 |
| V2 | chip_sw_entropy_src_fw_observe_many_contiguous | chip_sw_entropy_src_fw_observe_many_contiguous | 0 | 0 | -- | ||
| V2 | chip_sw_entropy_src_fw_extract_and_insert | chip_sw_entropy_src_fw_extract_and_insert | 0 | 0 | -- | ||
| V2 | chip_sw_flash_init | chip_sw_flash_init | 34.697m | 23.899ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_host_access | chip_sw_flash_ctrl_access | 20.105m | 5.571ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_access_jitter_en | 17.079m | 6.286ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_flash_ctrl_ops | chip_sw_flash_ctrl_ops | 12.703m | 4.626ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_ops_jitter_en | 13.946m | 4.562ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_flash_rma_unlocked | chip_sw_flash_rma_unlocked | 1.535h | 44.001ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_scramble | chip_sw_flash_init | 34.697m | 23.899ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_idle_low_power | chip_sw_flash_ctrl_idle_low_power | 7.135m | 3.561ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_keymgr_seeds | chip_sw_keymgr_key_derivation | 37.146m | 11.376ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_creator_seed_sw_rw_en | chip_sw_flash_ctrl_lc_rw_en | 9.057m | 4.829ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_creator_seed_wipe_on_rma | chip_sw_flash_rma_unlocked | 1.535h | 44.001ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_owner_seed_sw_rw_en | chip_sw_flash_ctrl_lc_rw_en | 9.057m | 4.829ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_iso_part_sw_rd_en | chip_sw_flash_ctrl_lc_rw_en | 9.057m | 4.829ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_iso_part_sw_wr_en | chip_sw_flash_ctrl_lc_rw_en | 9.057m | 4.829ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_seed_hw_rd_en | chip_sw_flash_ctrl_lc_rw_en | 9.057m | 4.829ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_escalate_en | chip_sw_all_escalation_resets | 14.330m | 5.914ms | 99 | 100 | 99.00 |
| V2 | chip_sw_flash_prim_tl_access | chip_prim_tl_access | 0 | 3 | 0.00 | ||
| V2 | chip_sw_flash_ctrl_clock_freqs | chip_sw_flash_ctrl_clock_freqs | 18.371m | 6.258ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_ctrl_escalation_reset | chip_sw_flash_crash_alert | 12.815m | 5.748ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_ctrl_write_clear | chip_sw_flash_crash_alert | 12.815m | 5.748ms | 3 | 3 | 100.00 |
| V2 | chip_sw_hmac_enc | chip_sw_hmac_enc | 4.730m | 2.910ms | 3 | 3 | 100.00 |
| chip_sw_hmac_enc_jitter_en | 5.682m | 3.017ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_hmac_idle | chip_sw_hmac_enc_idle | 5.445m | 3.268ms | 3 | 3 | 100.00 |
| V2 | chip_sw_hmac_all_configurations | chip_sw_hmac_oneshot | 5.915m | 3.166ms | 3 | 3 | 100.00 |
| V2 | chip_sw_hmac_multistream_mode | chip_sw_hmac_multistream | 24.983m | 6.992ms | 3 | 3 | 100.00 |
| V2 | chip_sw_i2c_host_tx_rx | chip_sw_i2c_host_tx_rx | 16.105m | 5.521ms | 3 | 3 | 100.00 |
| chip_sw_i2c_host_tx_rx_idx1 | 14.049m | 4.666ms | 3 | 3 | 100.00 | ||
| chip_sw_i2c_host_tx_rx_idx2 | 17.310m | 6.135ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_i2c_device_tx_rx | chip_sw_i2c_device_tx_rx | 8.977m | 3.460ms | 3 | 3 | 100.00 |
| V2 | chip_sw_keymgr_key_derivation | chip_sw_keymgr_key_derivation | 37.146m | 11.376ms | 3 | 3 | 100.00 |
| chip_sw_keymgr_key_derivation_jitter_en | 46.414m | 13.341ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_keymgr_sideload_kmac | chip_sw_keymgr_sideload_kmac | 41.672m | 11.203ms | 3 | 3 | 100.00 |
| V2 | chip_sw_keymgr_sideload_aes | chip_sw_keymgr_sideload_aes | 45.271m | 14.252ms | 3 | 3 | 100.00 |
| V2 | chip_sw_keymgr_sideload_otbn | chip_sw_keymgr_sideload_otbn | 1.144h | 14.575ms | 3 | 3 | 100.00 |
| V2 | chip_sw_kmac_enc | chip_sw_kmac_mode_cshake | 4.512m | 2.823ms | 3 | 3 | 100.00 |
| chip_sw_kmac_mode_kmac | 5.424m | 3.019ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en | 5.450m | 3.506ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_kmac_app_keymgr | chip_sw_keymgr_key_derivation | 37.146m | 11.376ms | 3 | 3 | 100.00 |
| V2 | chip_sw_kmac_app_lc | chip_sw_lc_ctrl_transition | 19.086m | 11.550ms | 15 | 15 | 100.00 |
| V2 | chip_sw_kmac_app_rom | chip_sw_kmac_app_rom | 4.430m | 2.746ms | 3 | 3 | 100.00 |
| V2 | chip_sw_kmac_entropy | chip_sw_kmac_entropy | 6.201m | 3.579ms | 3 | 3 | 100.00 |
| V2 | chip_sw_kmac_idle | chip_sw_kmac_idle | 4.638m | 2.732ms | 3 | 3 | 100.00 |
| V2 | chip_sw_lc_ctrl_alert_handler_escalation | chip_sw_alert_handler_escalation | 9.350m | 5.437ms | 3 | 3 | 100.00 |
| V2 | chip_sw_lc_ctrl_jtag_access | chip_tap_straps_dev | 18.132m | 9.328ms | 5 | 5 | 100.00 |
| chip_tap_straps_rma | 1.594h | 60.000ms | 4 | 5 | 80.00 | ||
| chip_tap_straps_prod | 28.542m | 13.813ms | 5 | 5 | 100.00 | ||
| V2 | chip_sw_lc_ctrl_otp_hw_cfg0 | chip_sw_lc_ctrl_otp_hw_cfg0 | 5.611m | 3.166ms | 3 | 3 | 100.00 |
| V2 | chip_sw_lc_ctrl_init | chip_sw_lc_ctrl_transition | 19.086m | 11.550ms | 15 | 15 | 100.00 |
| V2 | chip_sw_lc_ctrl_transitions | chip_sw_lc_ctrl_transition | 19.086m | 11.550ms | 15 | 15 | 100.00 |
| V2 | chip_sw_lc_ctrl_kmac_req | chip_sw_lc_ctrl_transition | 19.086m | 11.550ms | 15 | 15 | 100.00 |
| V2 | chip_sw_lc_ctrl_key_div | chip_sw_keymgr_key_derivation_prod | 33.307m | 12.340ms | 3 | 3 | 100.00 |
| V2 | chip_sw_lc_ctrl_broadcast | chip_sw_flash_ctrl_lc_rw_en | 9.057m | 4.829ms | 3 | 3 | 100.00 |
| chip_sw_flash_rma_unlocked | 1.535h | 44.001ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_test_unlocked0 | 12.482m | 4.544ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_dev | 23.730m | 9.408ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_prod | 25.645m | 8.462ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_rma | 24.692m | 7.536ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_ctrl_transition | 19.086m | 11.550ms | 15 | 15 | 100.00 | ||
| chip_sw_keymgr_key_derivation | 37.146m | 11.376ms | 3 | 3 | 100.00 | ||
| chip_sw_rom_ctrl_integrity_check | 10.505m | 9.402ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_execution_main | 15.463m | 9.041ms | 3 | 3 | 100.00 | ||
| chip_prim_tl_access | 0 | 3 | 0.00 | ||||
| chip_sw_clkmgr_external_clk_src_for_lc | 16.315m | 12.153ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 | 13.074m | 4.810ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 | 12.368m | 5.036ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_dev | 10.872m | 3.753ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_dev | 11.643m | 4.900ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_rma | 12.848m | 4.473ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_rma | 10.653m | 4.731ms | 3 | 3 | 100.00 | ||
| chip_tap_straps_dev | 18.132m | 9.328ms | 5 | 5 | 100.00 | ||
| chip_tap_straps_rma | 1.594h | 60.000ms | 4 | 5 | 80.00 | ||
| chip_tap_straps_prod | 28.542m | 13.813ms | 5 | 5 | 100.00 | ||
| chip_rv_dm_lc_disabled | 0 | 3 | 0.00 | ||||
| V2 | chip_lc_scrap | chip_sw_lc_ctrl_rma_to_scrap | 4.812m | 4.115ms | 1 | 1 | 100.00 |
| chip_sw_lc_ctrl_raw_to_scrap | 2.176m | 3.601ms | 1 | 1 | 100.00 | ||
| chip_sw_lc_ctrl_test_locked0_to_scrap | 1.881m | 3.266ms | 1 | 1 | 100.00 | ||
| chip_sw_lc_ctrl_rand_to_scrap | 2.574m | 3.607ms | 3 | 3 | 100.00 | ||
| V2 | chip_lc_test_locked | chip_sw_lc_walkthrough_testunlocks | 38.904m | 28.844ms | 3 | 3 | 100.00 |
| chip_rv_dm_lc_disabled | 0 | 3 | 0.00 | ||||
| V2 | chip_sw_lc_walkthrough | chip_sw_lc_walkthrough_dev | 1.689h | 50.716ms | 3 | 3 | 100.00 |
| chip_sw_lc_walkthrough_prod | 1.612h | 49.475ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_walkthrough_prodend | 19.041m | 10.927ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_walkthrough_rma | 1.816h | 48.774ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_walkthrough_testunlocks | 38.904m | 28.844ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_lc_ctrl_volatile_raw_unlock | chip_sw_lc_ctrl_volatile_raw_unlock | 2.358m | 2.727ms | 3 | 3 | 100.00 |
| chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz | 1.945m | 2.123ms | 3 | 3 | 100.00 | ||
| rom_volatile_raw_unlock | 1.877m | 2.981ms | 3 | 3 | 100.00 | ||
| V2 | chip_otp_ctrl_init | chip_sw_lc_ctrl_transition | 19.086m | 11.550ms | 15 | 15 | 100.00 |
| V2 | chip_sw_otp_ctrl_keys | chip_sw_flash_init | 34.697m | 23.899ms | 3 | 3 | 100.00 |
| chip_sw_otbn_mem_scramble | 9.476m | 3.369ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation | 37.146m | 11.376ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access | 13.133m | 5.513ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_icache_invalidate | 4.518m | 2.823ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_otp_ctrl_entropy | chip_sw_flash_init | 34.697m | 23.899ms | 3 | 3 | 100.00 |
| chip_sw_otbn_mem_scramble | 9.476m | 3.369ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation | 37.146m | 11.376ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access | 13.133m | 5.513ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_icache_invalidate | 4.518m | 2.823ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_otp_ctrl_program | chip_sw_lc_ctrl_transition | 19.086m | 11.550ms | 15 | 15 | 100.00 |
| V2 | chip_sw_otp_ctrl_program_error | chip_sw_lc_ctrl_program_error | 10.968m | 5.239ms | 3 | 3 | 100.00 |
| V2 | chip_sw_otp_ctrl_hw_cfg0 | chip_sw_lc_ctrl_otp_hw_cfg0 | 5.611m | 3.166ms | 3 | 3 | 100.00 |
| V2 | chip_sw_otp_ctrl_lc_signals | chip_sw_otp_ctrl_lc_signals_test_unlocked0 | 12.482m | 4.544ms | 3 | 3 | 100.00 |
| chip_sw_otp_ctrl_lc_signals_dev | 23.730m | 9.408ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_prod | 25.645m | 8.462ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_rma | 24.692m | 7.536ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_ctrl_transition | 19.086m | 11.550ms | 15 | 15 | 100.00 | ||
| chip_prim_tl_access | 0 | 3 | 0.00 | ||||
| V2 | chip_sw_otp_prim_tl_access | chip_prim_tl_access | 0 | 3 | 0.00 | ||
| V2 | chip_sw_otp_ctrl_dai_lock | chip_sw_otp_ctrl_dai_lock | 1.466h | 28.350ms | 1 | 1 | 100.00 |
| V2 | chip_sw_pwrmgr_external_full_reset | chip_sw_pwrmgr_full_aon_reset | 9.153m | 6.213ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_random_sleep_all_wake_ups | chip_sw_pwrmgr_random_sleep_all_wake_ups | 28.089m | 24.983ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_normal_sleep_all_wake_ups | chip_sw_pwrmgr_normal_sleep_all_wake_ups | 7.224m | 7.235ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_deep_sleep_por_reset | chip_sw_pwrmgr_deep_sleep_por_reset | 16.460m | 8.811ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_normal_sleep_por_reset | chip_sw_pwrmgr_normal_sleep_por_reset | 13.293m | 7.995ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_deep_sleep_all_wake_ups | chip_sw_pwrmgr_deep_sleep_all_wake_ups | 33.048m | 25.363ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_deep_sleep_all_reset_reqs | chip_sw_pwrmgr_deep_sleep_all_reset_reqs | 22.681m | 13.965ms | 2 | 3 | 66.67 |
| chip_sw_aon_timer_wdog_bite_reset | 15.299m | 8.022ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_pwrmgr_normal_sleep_all_reset_reqs | chip_sw_pwrmgr_normal_sleep_all_reset_reqs | 23.236m | 9.976ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_wdog_reset | chip_sw_pwrmgr_wdog_reset | 10.383m | 5.224ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_aon_power_glitch_reset | chip_sw_pwrmgr_full_aon_reset | 9.153m | 6.213ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_main_power_glitch_reset | chip_sw_pwrmgr_main_power_glitch_reset | 7.582m | 4.066ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_random_sleep_power_glitch_reset | chip_sw_pwrmgr_random_sleep_power_glitch_reset | 54.548m | 39.092ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_deep_sleep_power_glitch_reset | chip_sw_pwrmgr_deep_sleep_power_glitch_reset | 9.026m | 5.372ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_sleep_power_glitch_reset | chip_sw_pwrmgr_sleep_power_glitch_reset | 11.788m | 6.124ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_random_sleep_all_reset_reqs | chip_sw_pwrmgr_random_sleep_all_reset_reqs | 40.139m | 24.481ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_sysrst_ctrl_reset | chip_sw_pwrmgr_sysrst_ctrl_reset | 21.193m | 7.887ms | 3 | 3 | 100.00 |
| chip_sw_pwrmgr_all_reset_reqs | 30.969m | 9.493ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_pwrmgr_b2b_sleep_reset_req | chip_sw_pwrmgr_b2b_sleep_reset_req | 40.651m | 28.721ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_sleep_disabled | chip_sw_pwrmgr_sleep_disabled | 3.928m | 3.126ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_escalation_reset | chip_sw_all_escalation_resets | 14.330m | 5.914ms | 99 | 100 | 99.00 |
| V2 | chip_sw_rom_access | chip_sw_rom_ctrl_integrity_check | 10.505m | 9.402ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rom_ctrl_integrity_check | chip_sw_rom_ctrl_integrity_check | 10.505m | 9.402ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_non_sys_reset_info | chip_sw_pwrmgr_all_reset_reqs | 30.969m | 9.493ms | 3 | 3 | 100.00 |
| chip_sw_pwrmgr_random_sleep_all_reset_reqs | 40.139m | 24.481ms | 3 | 3 | 100.00 | ||
| chip_sw_pwrmgr_wdog_reset | 10.383m | 5.224ms | 3 | 3 | 100.00 | ||
| chip_sw_pwrmgr_smoketest | 8.629m | 5.873ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_rstmgr_sys_reset_info | chip_rv_dm_ndm_reset_req | 9.332m | 4.401ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_cpu_info | chip_sw_rstmgr_cpu_info | 11.735m | 6.374ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_sw_req_reset | chip_sw_rstmgr_sw_req | 6.823m | 3.538ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_alert_info | chip_sw_rstmgr_alert_info | 38.773m | 14.969ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_sw_rst | chip_sw_rstmgr_sw_rst | 4.864m | 2.547ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_escalation_reset | chip_sw_all_escalation_resets | 14.330m | 5.914ms | 99 | 100 | 99.00 |
| V2 | chip_sw_rstmgr_alert_handler_reset_enables | chip_sw_alert_handler_lpg_reset_toggle | 41.487m | 8.388ms | 3 | 3 | 100.00 |
| V2 | chip_sw_plic_all_irqs | chip_plic_all_irqs_0 | 21.858m | 5.878ms | 3 | 3 | 100.00 |
| chip_plic_all_irqs_10 | 11.069m | 4.544ms | 3 | 3 | 100.00 | ||
| chip_plic_all_irqs_20 | 13.638m | 5.589ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_plic_sw_irq | chip_sw_plic_sw_irq | 6.523m | 3.163ms | 3 | 3 | 100.00 |
| V2 | chip_sw_timer | chip_sw_rv_timer_irq | 4.787m | 3.100ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_device_flash_mode | rom_e2e_smoke | 1.038h | 14.732ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_device_pass_through | chip_sw_spi_device_pass_through | 12.809m | 6.868ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_device_pass_through_collision | chip_sw_spi_device_pass_through_collision | 9.943m | 3.793ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_device_tpm | chip_sw_spi_device_tpm | 6.282m | 3.080ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_host_tx_rx | chip_sw_spi_host_tx_rx | 5.150m | 3.449ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sram_scrambled_access | chip_sw_sram_ctrl_scrambled_access | 13.133m | 5.513ms | 3 | 3 | 100.00 |
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 8.586m | 3.860ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_sleep_sram_ret_contents | chip_sw_sleep_sram_ret_contents_no_scramble | 12.961m | 7.731ms | 3 | 3 | 100.00 |
| chip_sw_sleep_sram_ret_contents_scramble | 12.747m | 8.858ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_sram_execution | chip_sw_sram_ctrl_execution_main | 15.463m | 9.041ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sram_lc_escalation | chip_sw_all_escalation_resets | 14.330m | 5.914ms | 99 | 100 | 99.00 |
| chip_sw_data_integrity_escalation | 13.666m | 5.572ms | 6 | 6 | 100.00 | ||
| V2 | chip_sw_usbdev_mem | chip_sw_usbdev_mem | 0 | 0 | -- | ||
| V2 | chip_sw_usbdev_vbus | chip_sw_usbdev_vbus | 2.885m | 3.354ms | 1 | 1 | 100.00 |
| V2 | chip_sw_usbdev_pullup | chip_sw_usbdev_pullup | 4.808m | 2.984ms | 1 | 1 | 100.00 |
| V2 | chip_sw_usbdev_aon_pullup | chip_sw_usbdev_aon_pullup | 6.580m | 3.905ms | 1 | 1 | 100.00 |
| V2 | chip_sw_usbdev_sof | chip_sw_usbdev_sof | 0 | 0 | -- | ||
| V2 | chip_sw_usbdev_setup_rx | chip_sw_usbdev_setuprx | 11.767m | 4.128ms | 1 | 1 | 100.00 |
| V2 | chip_sw_usbdev_config_host | chip_sw_usbdev_config_host | 34.410m | 7.920ms | 1 | 1 | 100.00 |
| V2 | chip_sw_usbdev_pincfg | chip_sw_usbdev_pincfg | 2.226h | 31.206ms | 1 | 1 | 100.00 |
| V2 | chip_sw_usbdev_tx_rx | chip_sw_usbdev_dpi | 49.809m | 11.314ms | 1 | 1 | 100.00 |
| V2 | chip_sw_alert_handler_alerts | chip_sw_alert_test | 5.133m | 2.500ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_escalations | chip_sw_alert_handler_escalation | 9.350m | 5.437ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_escalation_nmi_reset | chip_sw_alert_handler_escalation_nmi_reset | 0 | 0 | -- | ||
| V2 | chip_sw_alert_handler_escalation_methods | chip_sw_alert_handler_escalation_methods | 0 | 0 | -- | ||
| V2 | chip_sw_all_escalation_resets | chip_sw_all_escalation_resets | 14.330m | 5.914ms | 99 | 100 | 99.00 |
| V2 | chip_sw_alert_handler_irqs | chip_plic_all_irqs | 0 | 0 | -- | ||
| V2 | chip_sw_alert_handler_entropy | chip_sw_alert_handler_entropy | 7.096m | 2.890ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_crashdump | chip_sw_rstmgr_alert_info | 38.773m | 14.969ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_ping_timeout | chip_sw_alert_handler_ping_timeout | 7.057m | 4.260ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_lpg_sleep_mode_alerts | chip_sw_alert_handler_lpg_sleep_mode_alerts | 9.678m | 3.377ms | 87 | 90 | 96.67 |
| V2 | chip_sw_alert_handler_lpg_sleep_mode_pings | chip_sw_alert_handler_lpg_sleep_mode_pings | 30.866m | 12.842ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_lpg_clock_off | chip_sw_alert_handler_lpg_clkoff | 26.837m | 7.158ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_lpg_reset_toggle | chip_sw_alert_handler_lpg_reset_toggle | 41.487m | 8.388ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_ping_ok | chip_sw_alert_handler_ping_ok | 25.674m | 7.822ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_reverse_ping_in_deep_sleep | chip_sw_alert_handler_reverse_ping_in_deep_sleep | 3.675h | 254.934ms | 3 | 3 | 100.00 |
| V2 | chip_jtag_csr_rw | chip_jtag_csr_rw | 31.981m | 18.181ms | 3 | 3 | 100.00 |
| V2 | chip_jtag_mem_access | chip_jtag_mem_access | 28.530m | 14.152ms | 3 | 3 | 100.00 |
| V2 | chip_rv_dm_ndm_reset_req | chip_rv_dm_ndm_reset_req | 9.332m | 4.401ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rv_dm_ndm_reset_req_when_cpu_halted | chip_sw_rv_dm_ndm_reset_req_when_cpu_halted | 10.256m | 4.589ms | 3 | 3 | 100.00 |
| V2 | chip_rv_dm_access_after_wakeup | chip_sw_rv_dm_access_after_wakeup | 8.758m | 6.025ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rv_dm_jtag_tap_sel | chip_tap_straps_rma | 1.594h | 60.000ms | 4 | 5 | 80.00 |
| V2 | chip_rv_dm_lc_disabled | chip_rv_dm_lc_disabled | 0 | 3 | 0.00 | ||
| V2 | chip_rv_dm_jtag | chip_rv_dm_jtag | 0 | 0 | -- | ||
| V2 | chip_rv_dm_dtm | chip_rv_dm_dtm | 0 | 0 | -- | ||
| V2 | chip_rv_dm_control_status | chip_rv_dm_control_status | 0 | 0 | -- | ||
| V2 | TOTAL | 882 | 2644 | 33.36 | |||
| V2S | chip_sw_aes_masking_off | chip_sw_aes_masking_off | 4.800m | 2.947ms | 3 | 3 | 100.00 |
| V2S | TOTAL | 3 | 3 | 100.00 | |||
| V3 | chip_sw_usb_suspend | chip_sw_usb_suspend | 0 | 0 | -- | ||
| V3 | chip_sw_coremark | chip_sw_coremark | 3.825h | 71.407ms | 1 | 1 | 100.00 |
| V3 | chip_sw_power_max_load | chip_sw_power_virus | 24.849m | 5.946ms | 3 | 3 | 100.00 |
| V3 | rom_e2e_debug | rom_e2e_jtag_debug_test_unlocked0 | 36.005m | 10.837ms | 1 | 1 | 100.00 |
| rom_e2e_jtag_debug_dev | 41.473m | 10.966ms | 1 | 1 | 100.00 | ||
| rom_e2e_jtag_debug_rma | 32.557m | 11.461ms | 1 | 1 | 100.00 | ||
| V3 | rom_e2e_jtag_inject | rom_e2e_jtag_inject_test_unlocked0 | 37.607m | 26.151ms | 1 | 1 | 100.00 |
| rom_e2e_jtag_inject_dev | 41.745m | 32.054ms | 1 | 1 | 100.00 | ||
| rom_e2e_jtag_inject_rma | 37.426m | 25.236ms | 1 | 1 | 100.00 | ||
| V3 | rom_bootstrap_rma | rom_bootstrap_rma | 0 | 0 | -- | ||
| V3 | rom_e2e_weak_straps | rom_e2e_weak_straps | 0 | 0 | -- | ||
| V3 | rom_e2e_self_hash | rom_e2e_self_hash | 1.827h | 26.754ms | 3 | 3 | 100.00 |
| V3 | manuf_cp_unlock_raw | manuf_cp_unlock_raw | 0 | 0 | -- | ||
| V3 | manuf_scrap | manuf_scrap | 0 | 0 | -- | ||
| V3 | manuf_cp_yield_test | manuf_cp_yield_test | 0 | 0 | -- | ||
| V3 | manuf_cp_ast_test_execution | manuf_cp_ast_test_execution | 0 | 0 | -- | ||
| V3 | manuf_cp_device_info_flash_wr | manuf_cp_device_info_flash_wr | 0 | 0 | -- | ||
| V3 | manuf_cp_test_lock | manuf_cp_test_lock | 0 | 0 | -- | ||
| V3 | manuf_ft_exit_token | manuf_ft_exit_token | 0 | 0 | -- | ||
| V3 | manuf_ft_sku_individualization_preop | manuf_ft_sku_individualization_preop | 0 | 0 | -- | ||
| V3 | manuf_ft_sku_individualization | manuf_ft_sku_individualization | 0 | 0 | -- | ||
| V3 | manuf_ft_provision_rma_token_and_personalization | manuf_ft_provision_rma_token_and_personalization | 0 | 0 | -- | ||
| V3 | manuf_ft_load_transport_image | manuf_ft_load_transport_image | 0 | 0 | -- | ||
| V3 | manuf_ft_load_certificates | manuf_ft_load_certificates | 0 | 0 | -- | ||
| V3 | manuf_ft_eom | manuf_ft_eom | 0 | 0 | -- | ||
| V3 | manuf_rma_entry | manuf_rma_entry | 0 | 0 | -- | ||
| V3 | manuf_sram_program_crc_functest | manuf_sram_program_crc_functest | 0 | 0 | -- | ||
| V3 | chip_sw_adc_ctrl_normal | chip_sw_adc_ctrl_normal | 0 | 0 | -- | ||
| V3 | chip_sw_adc_ctrl_oneshot | chip_sw_adc_ctrl_oneshot | 0 | 0 | -- | ||
| V3 | chip_sw_clkmgr_jitter_cycle_measurements | chip_sw_clkmgr_jitter_frequency | 8.418m | 3.704ms | 3 | 3 | 100.00 |
| V3 | chip_sw_edn_boot_mode | chip_sw_edn_boot_mode | 12.129m | 3.295ms | 3 | 3 | 100.00 |
| V3 | chip_sw_edn_auto_mode | chip_sw_edn_auto_mode | 25.411m | 6.008ms | 3 | 3 | 100.00 |
| V3 | chip_sw_edn_sw_mode | chip_sw_edn_sw_mode | 43.082m | 10.799ms | 3 | 3 | 100.00 |
| V3 | chip_sw_edn_kat | chip_sw_edn_kat | 9.595m | 3.420ms | 3 | 3 | 100.00 |
| V3 | chip_sw_entropy_src_bypass_mode_health_tests | chip_sw_entropy_src_bypass_mode_health_tests | 0 | 0 | -- | ||
| V3 | chip_sw_entropy_src_fips_mode_health_tests | chip_sw_entropy_src_fips_mode_health_tests | 0 | 0 | -- | ||
| V3 | chip_sw_entropy_src_validation | chip_sw_entropy_src_validation | 0 | 0 | -- | ||
| V3 | chip_sw_flash_memory_protection | chip_sw_flash_ctrl_mem_protection | 23.029m | 5.718ms | 3 | 3 | 100.00 |
| V3 | chip_sw_hmac_sha2_stress | chip_sw_hmac_sha2_stress | 0 | 0 | -- | ||
| V3 | chip_sw_hmac_stress | chip_sw_hmac_stress | 0 | 0 | -- | ||
| V3 | chip_sw_hmac_endianness | chip_sw_hmac_endianness | 0 | 0 | -- | ||
| V3 | chip_sw_hmac_secure_wipe | chip_sw_hmac_secure_wipe | 0 | 0 | -- | ||
| V3 | chip_sw_hmac_error_conditions | chip_sw_hmac_error_conditions | 0 | 0 | -- | ||
| V3 | chip_sw_i2c_speed | chip_sw_i2c_speed | 0 | 0 | -- | ||
| V3 | chip_sw_i2c_override | chip_sw_i2c_override | 0 | 0 | -- | ||
| V3 | chip_sw_i2c_clockstretching | chip_sw_i2c_clockstretching | 0 | 0 | -- | ||
| V3 | chip_sw_i2c_nack | chip_sw_i2c_nack | 0 | 0 | -- | ||
| V3 | chip_sw_i2c_repeatedstart | chip_sw_i2c_repeatedstart | 0 | 0 | -- | ||
| V3 | chip_sw_keymgr_sideload_kmac_error | chip_sw_keymgr_sideload_kmac_error | 0 | 0 | -- | ||
| V3 | chip_sw_keymgr_derive_attestation | chip_sw_keymgr_derive_attestation | 0 | 0 | -- | ||
| V3 | chip_sw_keymgr_derive_sealing | chip_sw_keymgr_derive_sealing | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_sha3_stress | chip_sw_kmac_sha3_stress | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_shake_stress | chip_sw_kmac_shake_stress | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_cshake_stress | chip_sw_kmac_cshake_stress | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_kmac_stress | chip_sw_kmac_kmac_stress | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_kmac_key_sideload | chip_sw_kmac_kmac_key_sideload | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_endianess | chip_sw_kmac_endianess | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_entropy_stress | chip_sw_kmac_entropy_stress | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_error_conditions | chip_sw_kmac_error_conditions | 0 | 0 | -- | ||
| V3 | chip_sw_lc_ctrl_kmac_error | chip_sw_lc_ctrl_kmac_error | 0 | 0 | -- | ||
| V3 | chip_sw_lc_ctrl_debug_access | chip_sw_lc_ctrl_debug_access | 0 | 0 | -- | ||
| V3 | chip_sw_otp_ctrl_vendor_test_csr_access | chip_sw_otp_ctrl_vendor_test_csr_access | 4.150m | 3.580ms | 3 | 3 | 100.00 |
| V3 | chip_sw_otp_ctrl_escalation | chip_sw_otp_ctrl_escalation | 8.974m | 4.228ms | 1 | 1 | 100.00 |
| V3 | otp_ctrl_calibration | otp_ctrl_calibration | 0 | 0 | -- | ||
| V3 | otp_ctrl_partition_access_locked | otp_ctrl_partition_access_locked | 0 | 0 | -- | ||
| V3 | otp_ctrl_check_timeout | otp_ctrl_check_timeout | 0 | 0 | -- | ||
| V3 | chip_sw_sensor_ctrl_deep_sleep_wake_up | chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up | 9.611m | 5.730ms | 3 | 3 | 100.00 |
| V3 | chip_sw_pwrmgr_usb_clk_disabled_when_active | chip_sw_pwrmgr_usb_clk_disabled_when_active | 8.658m | 4.462ms | 3 | 3 | 100.00 |
| V3 | chip_sw_all_resets | chip_sw_pwrmgr_all_reset_reqs | 30.969m | 9.493ms | 3 | 3 | 100.00 |
| V3 | chip_sw_rom_ctrl_kmac_error | chip_sw_rom_ctrl_kmac_error | 0 | 0 | -- | ||
| V3 | chip_sw_rom_ctrl_digests | chip_sw_rom_ctrl_digests | 0 | 0 | -- | ||
| V3 | chip_sw_plic_alerts | chip_sw_all_escalation_resets | 14.330m | 5.914ms | 99 | 100 | 99.00 |
| V3 | tick_configuration | chip_sw_rv_timer_systick_test | 0 | 3 | 0.00 | ||
| V3 | counter_wrap | chip_sw_rv_timer_systick_test | 0 | 3 | 0.00 | ||
| V3 | chip_sw_spi_device_pass_through_flash_model | //sw/device/tests:spi_passthru_test | 0 | 0 | -- | ||
| V3 | chip_sw_spi_device_output_when_disabled_or_sleeping | chip_sw_spi_device_pinmux_sleep_retention | 5.614m | 3.979ms | 3 | 3 | 100.00 |
| V3 | chip_sw_spi_host_pass_through | //sw/device/tests:spi_passthru_test | 0 | 0 | -- | ||
| V3 | chip_sw_spi_host_configuration | //sw/device/tests:spi_host_config_test | 0 | 0 | -- | ||
| V3 | chip_sw_spi_host_events | chip_sw_spi_host_events | 0 | 0 | -- | ||
| V3 | chip_sw_sram_memset | chip_sw_sram_memset | 0 | 0 | -- | ||
| V3 | chip_sw_sram_readback | chip_sw_sram_readback | 0 | 0 | -- | ||
| V3 | chip_sw_sram_subword_access | chip_sw_sram_subword_access | 0 | 0 | -- | ||
| V3 | chip_sw_uart_parity | chip_sw_uart_parity | 0 | 0 | -- | ||
| V3 | chip_sw_uart_line_loopback | chip_sw_uart_line_loopback | 0 | 0 | -- | ||
| V3 | chip_sw_uart_system_loopback | chip_sw_uart_system_loopback | 0 | 0 | -- | ||
| V3 | chip_sw_uart_line_break | chip_sw_uart_line_break | 0 | 0 | -- | ||
| V3 | chip_sw_uart_watermarks | chip_sw_uart_tx_rx | 11.944m | 4.505ms | 5 | 5 | 100.00 |
| V3 | chip_sw_usbdev_stream | chip_sw_usbdev_stream | 1.245h | 18.235ms | 1 | 1 | 100.00 |
| V3 | chip_sw_usbdev_iso | chip_sw_usbdev_iso | 0 | 0 | -- | ||
| V3 | chip_sw_usbdev_mixed | chip_sw_usbdev_mixed | 0 | 0 | -- | ||
| V3 | chip_sw_usbdev_suspend_resume | chip_sw_usbdev_suspend_resume | 0 | 0 | -- | ||
| V3 | chip_sw_usbdev_aon_wake_reset | chip_sw_usbdev_aon_wake_reset | 0 | 0 | -- | ||
| V3 | chip_sw_usbdev_aon_wake_disconnect | chip_sw_usbdev_aon_wake_disconnect | 0 | 0 | -- | ||
| V3 | chip_sw_usbdev_toggle_restore | chip_sw_usbdev_toggle_restore | 0 | 0 | -- | ||
| V3 | chip_rv_dm_perform_debug | rom_e2e_jtag_debug_test_unlocked0 | 36.005m | 10.837ms | 1 | 1 | 100.00 |
| rom_e2e_jtag_debug_dev | 41.473m | 10.966ms | 1 | 1 | 100.00 | ||
| rom_e2e_jtag_debug_rma | 32.557m | 11.461ms | 1 | 1 | 100.00 | ||
| V3 | chip_sw_rv_dm_access_after_hw_reset | chip_sw_rv_dm_access_after_escalation_reset | 10.011m | 4.829ms | 3 | 3 | 100.00 |
| V3 | TOTAL | 48 | 51 | 94.12 | |||
| Unmapped tests | chip_sival_flash_info_access | 5.806m | 3.181ms | 3 | 3 | 100.00 | |
| chip_sw_rstmgr_rst_cnsty_escalation | 15.819m | 4.753ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_ecc_error_vendor_test | 5.015m | 3.773ms | 3 | 3 | 100.00 | ||
| chip_sw_otbn_ecdsa_op_irq | 1.042h | 17.721ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_rnd | 17.150m | 5.579ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_nmi_irq | 14.868m | 5.105ms | 3 | 3 | 100.00 | ||
| chip_sw_pwrmgr_lowpower_cancel | 7.867m | 3.885ms | 2 | 3 | 66.67 | ||
| chip_sw_pwrmgr_sleep_wake_5_bug | 10.479m | 6.739ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_address_translation | 6.011m | 3.192ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_lockstep_glitch | 4.327m | 2.403ms | 0 | 3 | 0.00 | ||
| chip_sw_flash_ctrl_write_clear | 7.118m | 3.128ms | 3 | 3 | 100.00 | ||
| TOTAL | 1027 | 2951 | 34.80 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| N.A. | 11 | 11 | 9 | 81.82 |
| V1 | 18 | 18 | 12 | 66.67 |
| V2 | 285 | 270 | 245 | 85.96 |
| V2S | 1 | 1 | 1 | 100.00 |
| V3 | 90 | 23 | 22 | 24.44 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 90.45 | 92.87 | 82.58 | 90.73 | -- | 94.73 | 97.35 | 84.43 |
launch_task.returncode != *, err: * *:*:* * lswatcher.go:*] Failed to connect to Watcher service in the Envelope (you probably need to import _ "google3/tech/env/go/envelope"): generic::unimplemented: envrpc: no envelope available for service "chubby.googleapis.com" Failure to submit jobs: rpc error: code = Unavailable desc = The service is currently unavailable. has 956 failures:
Test chip_csr_bit_bash has 3 failures.
0.chip_csr_bit_bash.95740431632190367448240804833684234623301378001569493533580514219998017032504
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_csr_bit_bash/latest/run.log
2.chip_csr_bit_bash.99284994002039628636224886231632757029287732353759744977302748383757527879478
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_csr_bit_bash/latest/run.log
... and 1 more failures.
Test chip_same_csr_outstanding has 3 failures.
0.chip_same_csr_outstanding.9125959766489860317821151504663917242894783175816251234374478752190655919750
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_same_csr_outstanding/latest/run.log
2.chip_same_csr_outstanding.91511394384033400307530253973214054590672235757822904440351773262437530508079
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_same_csr_outstanding/latest/run.log
... and 1 more failures.
Test chip_prim_tl_access has 2 failures.
0.chip_prim_tl_access.36194525153551435943130047950223134844978700249482784940400620134157562953627
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_prim_tl_access/latest/run.log
2.chip_prim_tl_access.91013931358979661004684571936786621755682450002812773491717296445872741694887
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_prim_tl_access/latest/run.log
Test xbar_smoke has 8 failures.
0.xbar_smoke.107349010242893741794492264867206002823064251908768759502588591358015597669357
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.xbar_smoke/latest/run.log
2.xbar_smoke.110417556913855965339580668005667337877041224850362269421923621464449210521576
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.xbar_smoke/latest/run.log
... and 6 more failures.
Test xbar_smoke_large_delays has 8 failures.
0.xbar_smoke_large_delays.10615627621067385253280512910902716627722780840674798492229906796436654901853
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.xbar_smoke_large_delays/latest/run.log
2.xbar_smoke_large_delays.43299115247449664690250906698893275101615698637617302001609494347687956906830
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.xbar_smoke_large_delays/latest/run.log
... and 6 more failures.
... and 22 more tests.
Job killed most likely because its dependent job failed. has 955 failures:
Test chip_csr_aliasing has 3 failures.
0.chip_csr_aliasing.30127950685013243631454325540400571476164158018353764123244920590165412952254
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_csr_aliasing/latest/run.log
2.chip_csr_aliasing.57269339066533720009081287262012556920200980234478902873112030246915973409236
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_csr_aliasing/latest/run.log
... and 1 more failures.
Test chip_tl_errors has 8 failures.
0.chip_tl_errors.107334479113821426615950333640189051588877814503601455152129583089146930854530
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_tl_errors/latest/run.log
2.chip_tl_errors.74547230009309195121122100450729137068832082933989944128811764776818696719232
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_tl_errors/latest/run.log
... and 6 more failures.
Test chip_rv_dm_lc_disabled has 2 failures.
0.chip_rv_dm_lc_disabled.8190200110375723867932026134059311358152044480720221296436992219278301846399
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_rv_dm_lc_disabled/latest/run.log
2.chip_rv_dm_lc_disabled.77333796184381745845968751314643697038697413746605765838622098545541562066675
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_rv_dm_lc_disabled/latest/run.log
Test xbar_smoke_zero_delays has 8 failures.
0.xbar_smoke_zero_delays.77398589365709734776516076383075128108239030354575592117733627100730591209593
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.xbar_smoke_zero_delays/latest/run.log
2.xbar_smoke_zero_delays.46529393579038160415844614134479690322041996628307436860753654876083341603921
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.xbar_smoke_zero_delays/latest/run.log
... and 6 more failures.
Test xbar_smoke_slow_rsp has 8 failures.
0.xbar_smoke_slow_rsp.81757140098801770239377504206475925708697767255243805698164176149530005710913
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.xbar_smoke_slow_rsp/latest/run.log
2.xbar_smoke_slow_rsp.99918088006926367195655704496018158318994521100861619396177595592873000529886
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.xbar_smoke_slow_rsp/latest/run.log
... and 6 more failures.
... and 22 more tests.
Job chip_earlgrey_asic-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 3 failures:
0.chip_sw_rv_timer_systick_test.71568995275558450707140217894398869001801379317984585084842569128145521341124
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_timer_systick_test/latest/run.log
Job ID: smart:21ce6369-a371-4ccd-b0f8-935f56c15135
1.chip_sw_rv_timer_systick_test.8671697796381777112283241238374132094580459361202411549769061664607772498846
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_timer_systick_test/latest/run.log
Job ID: smart:47138017-82be-415c-854f-8136f44d1b4c
... and 1 more failures.
UVM_FATAL @ * us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (* [*] vs * [*]) Major alert did not match expectation. has 3 failures:
0.chip_sw_rv_core_ibex_lockstep_glitch.54908553015487717446452391710130328201443128839178874339735947390374492485865
Line 739, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_core_ibex_lockstep_glitch/latest/run.log
UVM_FATAL @ 2425.732000 us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (0 [0x0] vs 1 [0x1]) Major alert did not match expectation.
UVM_INFO @ 2425.732000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_rv_core_ibex_lockstep_glitch.32281967739756384017763000771265460765977315729828518629930567251723059492177
Line 761, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_core_ibex_lockstep_glitch/latest/run.log
UVM_FATAL @ 2402.699980 us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (0 [0x0] vs 1 [0x1]) Major alert did not match expectation.
UVM_INFO @ 2402.699980 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=* MEPC=* MTVAL=* has 3 failures:
10.chip_sw_alert_handler_lpg_sleep_mode_alerts.12670769014464771507130684395120357082263736262623773646690701363048685485746
Line 794, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/10.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
UVM_ERROR @ 3907.531344 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=00000005 MEPC=2000371c MTVAL=40600800
UVM_INFO @ 3907.531344 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
38.chip_sw_alert_handler_lpg_sleep_mode_alerts.108852470514476138092564878873231917552431785221903948440349012583168566499733
Line 811, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/38.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
UVM_ERROR @ 3376.502840 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=00000005 MEPC=2000371c MTVAL=40600800
UVM_INFO @ 3376.502840 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Offending '(pend_req[h2d.a_source].pend == *)' has 1 failures:
0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.89800691169685322234299237094842493160105962877928790600290478861656358302145
Line 778, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest/run.log
Offending '(pend_req[h2d.a_source].pend == 0)'
UVM_ERROR @ 12652.793160 us: (tlul_assert.sv:268) [ASSERT FAILED] pendingReqPerSrc_M
UVM_INFO @ 12652.793160 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [pwrmgr_lowpower_cancel_test_sim_dv(sw/device/tests/pwrmgr_lowpower_cancel_test.c:84)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for !get_wakeup_status() has 1 failures:
1.chip_sw_pwrmgr_lowpower_cancel.13097811192942552380948190105815401714814061611366778944937745943803680119935
Line 756, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_lowpower_cancel/latest/run.log
UVM_ERROR @ 3542.126280 us: (sw_logger_if.sv:526) [pwrmgr_lowpower_cancel_test_sim_dv(sw/device/tests/pwrmgr_lowpower_cancel_test.c:84)] CHECK-fail: Timed out after 100 usec (10000 CPU cycles) waiting for !get_wakeup_status()
UVM_INFO @ 3542.126280 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * us hit, indicating a probable testbench issue has 1 failures:
2.chip_tap_straps_rma.84575336693728147164288814171065852145528545872860479158808366796673637789057
Line 5992, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_tap_straps_rma/latest/run.log
UVM_FATAL @ 60000.000000 us: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 60000.000000 us hit, indicating a probable testbench issue
UVM_INFO @ 60000.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected *, got * has 1 failures:
26.chip_sw_all_escalation_resets.42860548442272342400676396641803975011277305817572019169801331332102373857195
Line 806, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/26.chip_sw_all_escalation_resets/latest/run.log
UVM_ERROR @ 2774.709500 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected 0x40600000, got 0x40600804
UVM_INFO @ 2774.709500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---