Unified Coverage Report :: Group :: tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

Group : tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	3570229	1			T77	111		T78	1282		T79	32
values[2]	718745	1			T77	39		T78	312		T79	59
values[3]	96683	1			T77	23		T78	2		T79	71
values[4]	50463	1			T77	2		T79	45		T217	78
values[5]	34589	1			T79	48		T217	38		T506	41
values[6]	26116	1			T79	26		T217	51		T506	43
values[7]	21426	1			T79	18		T217	39		T506	18
values[8]	18788	1			T79	9		T217	30		T506	19
values[9]	16905	1			T79	8		T217	35		T506	15
values[10]	15296	1			T79	7		T217	35		T506	24
values[11]	14536	1			T79	15		T217	32		T506	26
values[12]	13922	1			T79	25		T217	24		T506	25
values[13]	13049	1			T79	16		T217	28		T506	27
values[14]	12711	1			T79	14		T217	46		T506	9
values[15]	11933	1			T79	11		T217	24		T506	14
values[16]	11672	1			T79	9		T217	19		T506	9
values[17]	11145	1			T79	6		T217	24		T506	12
values[18]	10625	1			T79	9		T217	37		T506	8
values[19]	10435	1			T79	4		T217	22		T506	5
values[20]	10168	1			T79	2		T217	15		T506	9
values[21]	9801	1			T79	2		T217	16		T506	5
values[22]	9377	1			T79	4		T217	22		T506	6
values[23]	9370	1			T79	4		T217	26		T506	7
values[24]	8999	1			T79	7		T217	23		T506	16
values[25]	8363	1			T79	16		T217	28		T506	25
values[26]	8047	1			T79	14		T217	16		T506	23
values[27]	7635	1			T79	12		T217	17		T506	28
values[28]	7633	1			T79	2		T217	15		T506	10
values[29]	7025	1			T79	1		T217	15		T506	2
values[30]	6519	1			T79	1		T217	15		T506	2
values[31]	6074	1			T79	1		T217	19		T506	6
values[32]	5623	1			T79	1		T217	20		T506	5
values[33]	5328	1			T79	1		T217	3		T506	2
values[34]	4914	1			T79	1		T217	3		T506	5
values[35]	4371	1			T79	1		T217	4		T506	2
values[36]	4141	1			T79	2		T217	2		T506	4
values[37]	3919	1			T79	1		T217	4		T506	5
values[38]	3868	1			T79	1		T217	4		T506	4
values[39]	3730	1			T79	2		T217	3		T506	7
values[40]	3598	1			T79	2		T217	1		T506	6
values[41]	3490	1			T79	2		T217	5		T506	7
values[42]	3430	1			T79	3		T506	9		T507	14
values[43]	3368	1			T79	3		T506	2		T507	13
values[44]	3181	1			T79	1		T506	4		T507	13
values[45]	3199	1			T79	2		T506	7		T507	14
values[46]	3142	1			T79	1		T506	11		T507	13
values[47]	3101	1			T79	1		T506	4		T507	13
values[48]	3014	1			T79	1		T506	4		T507	13
values[49]	2951	1			T79	3		T506	2		T507	13
values[50]	2925	1			T79	1		T506	9		T507	14
values[51]	2866	1			T79	1		T506	3		T507	14
values[52]	2818	1			T79	1		T506	4		T507	13
values[53]	2815	1			T79	2		T506	7		T507	13
values[54]	2736	1			T79	2		T506	9		T507	13
values[55]	2673	1			T79	2		T506	4		T507	13
values[56]	2652	1			T79	1		T506	3		T507	13
values[57]	2559	1			T79	2		T506	8		T507	13
values[58]	2584	1			T79	3		T506	5		T507	13
values[59]	2537	1			T79	2		T506	6		T507	13
values[60]	2472	1			T79	3		T506	3		T507	13
values[61]	2813	1			T79	2		T506	2		T507	13
values[62]	4070	1			T79	2		T506	14		T507	13
values[63]	10944	1			T79	7		T506	54		T507	14
values[64]	249694	1			T79	97		T506	144		T507	2497

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	4607480	1			T77	80		T78	1205		T79	661
values[2]	790979	1			T77	19		T78	314		T79	176
values[3]	82419	1			T77	6		T78	7		T79	22
values[4]	14221	1			T77	2		T79	2		T217	5
values[5]	5186	1			T506	18		T507	12		T423	2
values[6]	3279	1			T506	13		T507	5		T423	2
values[7]	2407	1			T506	14		T507	1		T423	2
values[8]	1960	1			T506	24		T423	2		T510	6
values[9]	1681	1			T506	12		T423	2		T510	4
values[10]	1520	1			T506	13		T423	2		T510	2
values[11]	1441	1			T506	5		T423	2		T510	3
values[12]	1386	1			T506	14		T423	2		T510	1
values[13]	1298	1			T506	13		T423	3		T510	2
values[14]	1148	1			T506	14		T423	2		T510	1
values[15]	1080	1			T506	15		T423	2		T510	4
values[16]	1015	1			T506	10		T423	2		T510	4
values[17]	954	1			T506	5		T423	1		T510	2
values[18]	816	1			T506	6		T423	1		T510	3
values[19]	824	1			T506	3		T423	2		T510	1
values[20]	727	1			T506	1		T423	2		T510	2
values[21]	683	1			T506	1		T423	2		T510	3
values[22]	667	1			T506	4		T423	2		T510	1
values[23]	643	1			T506	5		T423	2		T510	1
values[24]	626	1			T506	2		T423	2		T510	1
values[25]	699	1			T506	3		T423	2		T510	1
values[26]	648	1			T506	1		T423	2		T510	3
values[27]	579	1			T506	1		T423	2		T510	4
values[28]	549	1			T506	2		T423	2		T510	2
values[29]	549	1			T506	2		T423	2		T510	3
values[30]	506	1			T506	1		T423	3		T510	4
values[31]	563	1			T506	1		T423	2		T510	3
values[32]	526	1			T506	1		T423	2		T510	4
values[33]	490	1			T506	1		T423	2		T510	5
values[34]	503	1			T506	1		T423	2		T510	3
values[35]	496	1			T506	3		T423	2		T510	4
values[36]	490	1			T506	2		T423	2		T510	1
values[37]	481	1			T506	1		T423	2		T510	2
values[38]	457	1			T506	2		T423	2		T510	1
values[39]	426	1			T506	1		T423	1		T510	2
values[40]	461	1			T506	1		T423	2		T510	2
values[41]	441	1			T506	3		T423	2		T510	1
values[42]	454	1			T506	4		T423	2		T510	1
values[43]	422	1			T506	1		T423	2		T510	6
values[44]	412	1			T506	1		T423	2		T510	6
values[45]	427	1			T506	2		T423	2		T510	5
values[46]	444	1			T506	1		T423	2		T510	5
values[47]	442	1			T506	1		T423	2		T510	1
values[48]	395	1			T506	1		T423	2		T510	2
values[49]	391	1			T506	1		T423	3		T510	3
values[50]	382	1			T506	1		T423	2		T510	2
values[51]	351	1			T506	2		T423	2		T510	1
values[52]	337	1			T506	1		T423	2		T510	4
values[53]	374	1			T506	1		T423	2		T510	5
values[54]	371	1			T506	5		T423	2		T510	1
values[55]	421	1			T506	1		T423	2		T510	1
values[56]	374	1			T506	1		T423	2		T510	4
values[57]	360	1			T506	1		T423	2		T510	3
values[58]	367	1			T506	1		T423	2		T510	6
values[59]	355	1			T506	1		T423	2		T510	3
values[60]	350	1			T506	1		T423	2		T510	2
values[61]	402	1			T506	1		T423	2		T510	7
values[62]	667	1			T506	7		T423	2		T510	11
values[63]	2565	1			T506	42		T423	4		T510	16
values[64]	27994	1			T506	124		T423	157		T510	6

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	532851	1			T77	1		T78	12		T79	3
values[2]	2579258	1			T77	77		T78	1308		T79	7
values[3]	1127423	1			T77	22		T78	323		T79	79
values[4]	135674	1			T77	1		T78	1		T79	96
values[5]	69271	1			T77	1		T79	52		T217	106
values[6]	45436	1			T79	30		T217	36		T506	87
values[7]	33012	1			T79	27		T217	26		T506	37
values[8]	26552	1			T79	35		T217	22		T506	31
values[9]	22877	1			T79	28		T217	22		T506	21
values[10]	20412	1			T79	20		T217	38		T506	24
values[11]	18047	1			T79	18		T217	28		T506	16
values[12]	16470	1			T79	15		T217	27		T506	16
values[13]	15396	1			T79	10		T217	20		T506	10
values[14]	14745	1			T79	10		T217	17		T506	16
values[15]	14287	1			T79	14		T217	30		T506	17
values[16]	13971	1			T79	6		T217	44		T506	12
values[17]	13255	1			T79	5		T217	28		T506	14
values[18]	12461	1			T79	10		T217	16		T506	20
values[19]	12031	1			T79	7		T217	28		T506	5
values[20]	11653	1			T79	10		T217	26		T506	6
values[21]	10873	1			T79	9		T217	23		T506	3
values[22]	10751	1			T79	14		T217	17		T506	5
values[23]	10198	1			T79	17		T217	23		T506	5
values[24]	9755	1			T79	14		T217	28		T506	7
values[25]	9536	1			T79	8		T217	18		T506	3
values[26]	9091	1			T79	14		T217	9		T506	2
values[27]	8835	1			T79	10		T217	7		T506	4
values[28]	8560	1			T79	14		T217	5		T506	4
values[29]	8050	1			T79	5		T217	12		T506	3
values[30]	7398	1			T79	3		T217	18		T506	5
values[31]	6650	1			T79	1		T217	12		T506	2
values[32]	6207	1			T79	2		T217	12		T506	6
values[33]	5682	1			T79	2		T217	6		T506	5
values[34]	5397	1			T79	1		T217	7		T506	4
values[35]	4973	1			T79	1		T217	4		T506	4
values[36]	4623	1			T79	2		T217	6		T506	3
values[37]	4508	1			T79	2		T506	6		T507	13
values[38]	4326	1			T79	1		T506	5		T507	13
values[39]	4131	1			T79	3		T506	10		T507	14
values[40]	3930	1			T79	1		T506	8		T507	14
values[41]	3790	1			T79	1		T506	4		T507	13
values[42]	3810	1			T79	1		T506	5		T507	13
values[43]	3574	1			T79	4		T506	5		T507	13
values[44]	3495	1			T79	3		T506	7		T507	13
values[45]	3459	1			T79	3		T506	4		T507	13
values[46]	3357	1			T79	4		T506	5		T507	13
values[47]	3398	1			T79	2		T506	4		T507	14
values[48]	3406	1			T79	3		T506	6		T507	13
values[49]	3282	1			T79	2		T506	6		T507	13
values[50]	3229	1			T79	2		T506	2		T507	13
values[51]	3072	1			T79	3		T506	2		T507	13
values[52]	3049	1			T79	4		T506	2		T507	13
values[53]	2987	1			T79	2		T506	4		T507	13
values[54]	3010	1			T79	7		T506	4		T507	13
values[55]	2949	1			T79	9		T506	3		T507	13
values[56]	2855	1			T79	5		T506	3		T507	13
values[57]	2817	1			T79	1		T506	5		T507	13
values[58]	2834	1			T79	4		T506	4		T507	13
values[59]	2812	1			T79	2		T506	2		T507	13
values[60]	2684	1			T79	2		T506	2		T507	13
values[61]	2859	1			T79	2		T506	2		T507	13
values[62]	3744	1			T79	2		T506	9		T507	13
values[63]	9163	1			T79	11		T506	53		T507	16
values[64]	242582	1			T79	20		T506	210		T507	2505