Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

4 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1872275	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

37346687

1

T1

57740

T2

10988

T3

6833

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	27341311	1			T1	35515		T2	2708		T3	2920
values[0x0]	10392918	1			T1	22225		T2	8280		T3	3913
values[0x1]	1484733	1			T2	230		T3	275		T27	653

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	553248	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

38665714

1

T1

57740

T2

11218

T3

7108

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	18572357	1			T1	28870		T2	5610		T3	3554
valid_sources[0x01]	18570028	1			T1	28870		T2	5608		T3	3554
valid_sources[0x02]	33019	1			T68	14		T50	1		T204	1
valid_sources[0x03]	33185	1			T50	1		T204	23		T205	2
valid_sources[0x04]	33476	1			T68	2		T50	2		T205	1
valid_sources[0x05]	34806	1			T205	2		T242	111		T132	164
valid_sources[0x06]	33028	1			T242	66		T132	124		T147	3077
valid_sources[0x07]	33936	1			T50	1		T242	72		T132	211
valid_sources[0x08]	33538	1			T205	1		T242	86		T132	138
valid_sources[0x09]	33381	1			T205	3		T242	105		T132	241
valid_sources[0x0a]	33377	1			T205	1		T242	116		T132	169
valid_sources[0x0b]	32957	1			T242	54		T132	103		T147	3066
valid_sources[0x0c]	33666	1			T242	88		T132	96		T147	3058
valid_sources[0x0d]	32609	1			T242	106		T132	151		T147	3117
valid_sources[0x0e]	32750	1			T205	1		T242	103		T132	144
valid_sources[0x0f]	34446	1			T205	3		T242	96		T132	123
valid_sources[0x10]	32574	1			T242	115		T132	95		T147	3109
valid_sources[0x11]	33505	1			T68	1		T242	102		T132	176
valid_sources[0x12]	33582	1			T81	3		T242	65		T132	197
valid_sources[0x13]	33926	1			T50	1		T242	70		T132	189
valid_sources[0x14]	33815	1			T68	7		T204	1		T205	1
valid_sources[0x15]	33248	1			T50	1		T205	1		T242	80
valid_sources[0x16]	33334	1			T68	1		T242	104		T132	158
valid_sources[0x17]	33818	1			T50	3		T205	1		T242	53
valid_sources[0x18]	33971	1			T205	1		T242	71		T132	132
valid_sources[0x19]	33323	1			T50	1		T242	82		T132	96
valid_sources[0x1a]	33636	1			T50	1		T204	10		T242	91
valid_sources[0x1b]	32921	1			T68	3		T203	15		T242	93
valid_sources[0x1c]	33824	1			T50	1		T242	92		T132	145
valid_sources[0x1d]	33128	1			T50	1		T203	2		T205	1
valid_sources[0x1e]	33539	1			T68	2		T81	3		T242	112
valid_sources[0x1f]	33415	1			T242	78		T132	129		T147	3075
valid_sources[0x20]	32822	1			T242	71		T132	166		T147	3078

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

26755159

1

T1

35515

T2

2708

T3

2920

values[0x0]

all_enables

biggest_size

10337911

1

T1

22225

T2

8280

T3

3913

values[0x1]

all_enables

biggest_size

253617

1

T68

22

T50

13

T81

25

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2720517	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

429501

1

T77

28

T78

224

T79

89

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1067087	1			T77	45		T78	534		T79	232
values[0x0]	1014395	1			T77	65		T78	548		T79	210
values[0x1]	1068536	1			T77	65		T78	514		T79	213

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2105784	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1044234

1

T77

60

T78

532

T79

218

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	48965	1			T77	3		T78	30		T79	12
valid_sources[0x01]	48049	1			T77	4		T78	23		T79	19
valid_sources[0x02]	50028	1			T77	3		T78	29		T79	12
valid_sources[0x03]	49125	1			T77	6		T78	30		T79	11
valid_sources[0x04]	48696	1			T77	9		T78	34		T79	5
valid_sources[0x05]	49786	1			T78	28		T79	11		T82	9
valid_sources[0x06]	48569	1			T77	7		T78	26		T79	9
valid_sources[0x07]	48600	1			T78	26		T79	9		T82	13
valid_sources[0x08]	48675	1			T77	1		T78	25		T79	6
valid_sources[0x09]	49479	1			T78	33		T79	10		T82	13
valid_sources[0x0a]	49030	1			T78	42		T79	21		T82	14
valid_sources[0x0b]	49256	1			T78	20		T79	1		T82	16
valid_sources[0x0c]	49369	1			T78	19		T79	16		T82	19
valid_sources[0x0d]	51245	1			T77	1		T78	25		T79	6
valid_sources[0x0e]	49258	1			T78	22		T79	9		T82	11
valid_sources[0x0f]	49808	1			T78	22		T79	12		T82	7
valid_sources[0x10]	49320	1			T78	29		T79	8		T82	13
valid_sources[0x11]	49362	1			T77	4		T78	29		T79	15
valid_sources[0x12]	48840	1			T78	20		T79	13		T82	21
valid_sources[0x13]	49283	1			T77	12		T78	25		T79	4
valid_sources[0x14]	49662	1			T77	3		T78	21		T79	20
valid_sources[0x15]	49422	1			T78	25		T79	17		T82	18
valid_sources[0x16]	49231	1			T77	7		T78	25		T79	8
valid_sources[0x17]	50038	1			T77	8		T78	22		T79	9
valid_sources[0x18]	49393	1			T77	3		T78	27		T79	11
valid_sources[0x19]	48922	1			T78	21		T79	6		T82	8
valid_sources[0x1a]	48462	1			T78	17		T79	6		T82	16
valid_sources[0x1b]	50156	1			T78	18		T79	11		T82	15
valid_sources[0x1c]	49364	1			T77	3		T78	24		T79	6
valid_sources[0x1d]	49217	1			T78	22		T79	17		T82	17
valid_sources[0x1e]	48594	1			T77	16		T78	19		T79	9
valid_sources[0x1f]	50148	1			T78	27		T79	15		T82	15
valid_sources[0x20]	49370	1			T77	3		T78	24		T79	6

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

45110

1

T77

1

T78

22

T79

11

values[0x0]

all_enables

biggest_size

339044

1

T77

26

T78

177

T79

69

values[0x1]

all_enables

biggest_size

45347

1

T77

1

T78

25

T79

9

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2909266	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

473660

1

T77

13

T78

215

T79

128

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1158336	1			T77	38		T78	500		T79	277
values[0x0]	1064980	1			T77	34		T78	514		T79	288
values[0x1]	1159610	1			T77	35		T78	512		T79	296

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2232295	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1150631

1

T77

29

T78

507

T79

304

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	52363	1			T77	3		T78	20		T79	11
valid_sources[0x01]	52300	1			T77	1		T78	39		T79	7
valid_sources[0x02]	53147	1			T78	18		T79	13		T153	21
valid_sources[0x03]	53183	1			T77	2		T78	11		T79	14
valid_sources[0x04]	52355	1			T77	2		T78	11		T79	7
valid_sources[0x05]	53917	1			T78	6		T79	12		T82	24
valid_sources[0x06]	52569	1			T78	24		T79	17		T82	34
valid_sources[0x07]	52036	1			T78	25		T79	12		T153	23
valid_sources[0x08]	52875	1			T78	58		T79	14		T153	29
valid_sources[0x09]	53313	1			T78	8		T79	15		T82	9
valid_sources[0x0a]	53113	1			T78	51		T79	12		T82	26
valid_sources[0x0b]	52860	1			T77	1		T78	39		T79	14
valid_sources[0x0c]	53549	1			T77	4		T78	26		T79	11
valid_sources[0x0d]	53152	1			T77	1		T78	7		T79	12
valid_sources[0x0e]	52887	1			T77	2		T78	18		T79	13
valid_sources[0x0f]	53636	1			T77	2		T78	55		T79	19
valid_sources[0x10]	53265	1			T78	34		T79	18		T82	54
valid_sources[0x11]	52286	1			T77	4		T78	25		T79	10
valid_sources[0x12]	52189	1			T77	1		T78	22		T79	17
valid_sources[0x13]	52810	1			T77	3		T78	21		T79	11
valid_sources[0x14]	52588	1			T77	2		T78	21		T79	13
valid_sources[0x15]	52731	1			T78	13		T79	13		T82	47
valid_sources[0x16]	52295	1			T77	3		T78	16		T79	14
valid_sources[0x17]	53391	1			T77	2		T78	9		T79	10
valid_sources[0x18]	53378	1			T77	1		T78	4		T79	12
valid_sources[0x19]	52868	1			T78	10		T79	18		T82	22
valid_sources[0x1a]	52624	1			T78	22		T79	18		T153	23
valid_sources[0x1b]	52598	1			T77	4		T78	29		T79	8
valid_sources[0x1c]	52783	1			T78	23		T79	12		T82	4
valid_sources[0x1d]	53400	1			T77	3		T78	10		T79	17
valid_sources[0x1e]	52675	1			T77	1		T78	17		T79	14
valid_sources[0x1f]	53824	1			T77	1		T78	20		T79	7
valid_sources[0x20]	52934	1			T77	5		T78	45		T79	11

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

49656

1

T77

2

T78

15

T79

16

values[0x0]

all_enables

biggest_size

373431

1

T77

11

T78

182

T79

104

values[0x1]

all_enables

biggest_size

50573

1

T78

18

T79

8

T82

16

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2744869	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

433237

1

T77

7

T78

195

T79

102

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1074959	1			T77	34		T78	540		T79	228
values[0x0]	1026264	1			T77	29		T78	537		T79	224
values[0x1]	1076883	1			T77	39		T78	567		T79	253

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2124922	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1053184

1

T77

26

T78

514

T79

225

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	50275	1			T77	2		T78	28		T79	12
valid_sources[0x01]	49828	1			T77	2		T78	34		T79	13
valid_sources[0x02]	50445	1			T77	8		T78	19		T79	9
valid_sources[0x03]	49538	1			T77	2		T78	24		T79	10
valid_sources[0x04]	50460	1			T77	5		T78	26		T79	7
valid_sources[0x05]	50547	1			T77	2		T78	24		T79	12
valid_sources[0x06]	49945	1			T78	26		T79	15		T82	19
valid_sources[0x07]	49741	1			T77	3		T78	22		T79	4
valid_sources[0x08]	50273	1			T77	2		T78	33		T79	12
valid_sources[0x09]	48886	1			T77	2		T78	32		T79	9
valid_sources[0x0a]	49300	1			T78	31		T79	9		T82	16
valid_sources[0x0b]	50041	1			T77	3		T78	25		T79	13
valid_sources[0x0c]	49798	1			T77	3		T78	24		T79	12
valid_sources[0x0d]	49908	1			T77	1		T78	33		T79	8
valid_sources[0x0e]	48862	1			T77	6		T78	30		T79	5
valid_sources[0x0f]	49595	1			T77	2		T78	26		T79	10
valid_sources[0x10]	49334	1			T77	4		T78	24		T79	8
valid_sources[0x11]	49375	1			T77	3		T78	21		T79	20
valid_sources[0x12]	49303	1			T78	29		T79	14		T82	16
valid_sources[0x13]	48815	1			T77	1		T78	28		T79	10
valid_sources[0x14]	49535	1			T77	2		T78	20		T79	14
valid_sources[0x15]	49581	1			T78	16		T79	7		T82	20
valid_sources[0x16]	50103	1			T77	1		T78	21		T79	10
valid_sources[0x17]	50465	1			T77	3		T78	33		T79	9
valid_sources[0x18]	49714	1			T78	18		T79	16		T82	21
valid_sources[0x19]	49839	1			T78	31		T79	14		T82	13
valid_sources[0x1a]	49392	1			T77	3		T78	25		T79	14
valid_sources[0x1b]	49771	1			T77	3		T78	21		T79	13
valid_sources[0x1c]	49494	1			T78	27		T79	8		T82	9
valid_sources[0x1d]	50100	1			T77	4		T78	28		T79	10
valid_sources[0x1e]	48520	1			T78	34		T79	11		T82	16
valid_sources[0x1f]	50105	1			T78	25		T79	8		T82	16
valid_sources[0x20]	50212	1			T77	1		T78	29		T79	10

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

45542

1

T77

1

T78

19

T79

3

values[0x0]

all_enables

biggest_size

342258

1

T77

4

T78

156

T79

85

values[0x1]

all_enables

biggest_size

45437

1

T77

2

T78

20

T79

14