Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : spi_host
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.21 97.21

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_spi_host_1.0/rtl/spi_host.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_spi_host0 96.59 96.59
tb.dut.top_earlgrey.u_spi_host1 98.77 98.77



Module Instance : tb.dut.top_earlgrey.u_spi_host0

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.59 96.59


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.59 96.59


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.94 92.47 89.34 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.top_earlgrey.u_spi_host1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.77 98.77


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.77 98.77


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.94 92.47 89.34 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Toggle Coverage for Module : spi_host
TotalCoveredPercent
Totals 46 43 93.48
Total Bits 358 348 97.21
Total Bits 0->1 179 174 97.21
Total Bits 1->0 179 174 97.21

Ports 46 43 93.48
Port Bits 358 348 97.21
Port Bits 0->1 179 174 97.21
Port Bits 1->0 179 174 97.21

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T4,T6 Yes T1,T2,T3 INPUT
tl_i.d_ready Yes Yes T28,T11,T154 Yes T28,T11,T154 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T28,T11,T154 Yes T28,T11,T154 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T28,T11,T154 Yes T28,T11,T154 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T28,T11,T154 Yes T28,T11,T154 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T28,T11,T154 Yes T28,T11,T154 INPUT
tl_i.a_mask[3:0] Yes Yes T28,T11,T154 Yes T28,T11,T154 INPUT
tl_i.a_address[5:0] Yes Yes *T77,*T78,*T82 Yes T77,T78,T82 INPUT
tl_i.a_address[15:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[16] Yes Yes *T28,*T154,*T44 Yes T28,T154,T44 INPUT
tl_i.a_address[19:17] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[21:20] Yes Yes T28,T11,T154 Yes T28,T11,T154 INPUT
tl_i.a_address[29:22] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T28,*T11,*T154 Yes T28,T11,T154 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes *T77,*T78,*T82 Yes T77,T78,T82 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T77,T78,T82 Yes T77,T78,T82 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T197,T200,T201 Yes T197,T200,T201 INPUT
tl_i.a_valid Yes Yes T28,T11,T154 Yes T28,T11,T154 INPUT
tl_o.a_ready Yes Yes T28,T11,T154 Yes T28,T11,T154 OUTPUT
tl_o.d_error Yes Yes T77,T78,T79 Yes T77,T78,T82 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T28,T11,T154 Yes T28,T11,T154 OUTPUT
tl_o.d_user.rsp_intg[6:0] Yes Yes T28,T11,T154 Yes T28,T11,T154 OUTPUT
tl_o.d_data[31:0] Yes Yes T28,T11,T154 Yes T28,T11,T154 OUTPUT
tl_o.d_sink Yes Yes T77,T78,T82 Yes T77,T78,T82 OUTPUT
tl_o.d_source[5:0] Yes Yes *T77,*T78,*T82 Yes T77,T78,T79 OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[1:0] Yes Yes T77,T78,T82 Yes T77,T78,T82 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T28,*T11,*T154 Yes T28,T11,T154 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T28,T11,T154 Yes T28,T11,T154 OUTPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T278,T158,T84 Yes T278,T158,T84 INPUT
alert_rx_i[0].ping_n Yes Yes T158,T84,T85 Yes T158,T84,T85 INPUT
alert_rx_i[0].ping_p Yes Yes T158,T84,T85 Yes T158,T84,T85 INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T278,T158,T84 Yes T278,T158,T84 OUTPUT
cio_sck_o Yes Yes T28,T11,T12 Yes T28,T11,T12 OUTPUT
cio_sck_en_o Yes Yes T11,T12,T189 Yes T28,T11,T12 OUTPUT
cio_csb_o Yes Yes T28,T11,T12 Yes T28,T11,T12 OUTPUT
cio_csb_en_o Yes Yes T11,T12,T189 Yes T28,T11,T12 OUTPUT
cio_sd_o[3:0] Yes Yes T28,T11,T12 Yes T28,T11,T12 OUTPUT
cio_sd_en_o[3:0] Yes Yes T28,T11,T12 Yes T28,T11,T12 OUTPUT
cio_sd_i[3:0] Yes Yes T28,T11,T12 Yes T28,T11,T12 INPUT
passthrough_i.s_en[0] Yes Yes *T11,*T12,*T189 Yes T11,T12,T189 INPUT
passthrough_i.s_en[3:1] No No No INPUT
passthrough_i.s[3:0] Yes Yes T48,T11,T12 Yes T48,T11,T12 INPUT
passthrough_i.csb_en No No No INPUT
passthrough_i.csb Yes Yes T48,T11,T12 Yes T48,T11,T12 INPUT
passthrough_i.sck_en No No No INPUT
passthrough_i.sck Yes Yes T48,T11,T12 Yes T48,T11,T12 INPUT
passthrough_i.passthrough_en Yes Yes T197,T200,T201 Yes T11,T12,T189 INPUT
passthrough_o.s[3:0] Yes Yes T28,T11,T12 Yes T28,T11,T12 OUTPUT
intr_error_o Yes Yes T154,T155,T156 Yes T154,T155,T156 OUTPUT
intr_spi_event_o Yes Yes T154,T155,T156 Yes T154,T155,T156 OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.top_earlgrey.u_spi_host0
TotalCoveredPercent
Totals 44 42 95.45
Total Bits 352 340 96.59
Total Bits 0->1 176 170 96.59
Total Bits 1->0 176 170 96.59

Ports 44 42 95.45
Port Bits 352 340 96.59
Port Bits 0->1 176 170 96.59
Port Bits 1->0 176 170 96.59

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T4,T6 Yes T1,T2,T3 INPUT
tl_i.d_ready Yes Yes T11,T154,T12 Yes T11,T154,T12 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T11,T154,T12 Yes T11,T154,T12 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T11,T154,T12 Yes T11,T154,T12 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T11,T154,T12 Yes T11,T154,T12 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T11,T154,T12 Yes T11,T154,T12 INPUT
tl_i.a_mask[3:0] Yes Yes T11,T154,T12 Yes T11,T154,T12 INPUT
tl_i.a_address[5:0] Yes Yes *T77,*T78,*T82 Yes T77,T78,T82 INPUT
tl_i.a_address[19:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[21:20] Yes Yes T11,T154,T12 Yes T11,T154,T12 INPUT
tl_i.a_address[29:22] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T11,*T154,*T12 Yes T11,T154,T12 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes *T78,*T82,*T153 Yes T78,T82,T153 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T77,T78,T82 Yes T77,T78,T82 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T197,T200,T201 Yes T197,T200,T201 INPUT
tl_i.a_valid Yes Yes T11,T154,T12 Yes T11,T154,T12 INPUT
tl_o.a_ready Yes Yes T11,T154,T12 Yes T11,T154,T12 OUTPUT
tl_o.d_error Yes Yes T77,T78,T79 Yes T77,T78,T82 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T11,T154,T12 Yes T11,T154,T12 OUTPUT
tl_o.d_user.rsp_intg[6:0] Yes Yes T11,T154,T12 Yes T11,T154,T12 OUTPUT
tl_o.d_data[31:0] Yes Yes T11,T154,T12 Yes T11,T154,T12 OUTPUT
tl_o.d_sink Yes Yes T77,T78,T82 Yes T77,T78,T82 OUTPUT
tl_o.d_source[5:0] Yes Yes *T78,*T82,*T153 Yes T78,T79,T82 OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[1:0] Yes Yes T77,T78,T82 Yes T77,T78,T82 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T11,*T154,*T12 Yes T11,T154,T12 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T11,T154,T12 Yes T11,T154,T12 OUTPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T278,T158,T84 Yes T278,T158,T84 INPUT
alert_rx_i[0].ping_n Yes Yes T158,T84,T85 Yes T158,T84,T85 INPUT
alert_rx_i[0].ping_p Yes Yes T158,T84,T85 Yes T158,T84,T85 INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T278,T158,T84 Yes T278,T158,T84 OUTPUT
cio_sck_o Yes Yes T11,T12,T13 Yes T11,T12,T13 OUTPUT
cio_sck_en_o Yes Yes T11,T12,T189 Yes T11,T12,T13 OUTPUT
cio_csb_o Yes Yes T11,T12,T13 Yes T11,T12,T13 OUTPUT
cio_csb_en_o Yes Yes T11,T12,T189 Yes T11,T12,T13 OUTPUT
cio_sd_o[3:0] Yes Yes T11,T12,T13 Yes T11,T12,T13 OUTPUT
cio_sd_en_o[0] Yes Yes *T11,*T12,*T13 Yes T11,T12,T13 OUTPUT
cio_sd_en_o[3:1] No No No OUTPUT
cio_sd_i[3:0] Yes Yes T11,T12,T13 Yes T11,T12,T13 INPUT
passthrough_i.s_en[0] Yes Yes *T11,*T12,*T189 Yes T11,T12,T189 INPUT
passthrough_i.s_en[3:1] No No No INPUT
passthrough_i.s[3:0] Yes Yes T48,T11,T12 Yes T48,T11,T12 INPUT
passthrough_i.csb_en[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off.
passthrough_i.csb Yes Yes T48,T11,T12 Yes T48,T11,T12 INPUT
passthrough_i.sck_en[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off.
passthrough_i.sck Yes Yes T48,T11,T12 Yes T48,T11,T12 INPUT
passthrough_i.passthrough_en Yes Yes T197,T200,T201 Yes T11,T12,T189 INPUT
passthrough_o.s[3:0] Yes Yes T11,T12,T13 Yes T11,T12,T13 OUTPUT
intr_error_o Yes Yes T154,T155,T156 Yes T154,T155,T156 OUTPUT
intr_spi_event_o Yes Yes T154,T155,T156 Yes T154,T155,T156 OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.top_earlgrey.u_spi_host1
TotalCoveredPercent
Totals 38 37 97.37
Total Bits 324 320 98.77
Total Bits 0->1 162 161 99.38
Total Bits 1->0 162 159 98.15

Ports 38 37 97.37
Port Bits 324 320 98.77
Port Bits 0->1 162 161 99.38
Port Bits 1->0 162 159 98.15

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T4,T6 Yes T1,T2,T3 INPUT
tl_i.d_ready Yes Yes T28,T154,T44 Yes T28,T154,T44 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T28,T154,T44 Yes T28,T154,T44 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T28,T154,T44 Yes T28,T154,T44 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T28,T154,T44 Yes T28,T154,T44 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T28,T154,T44 Yes T28,T154,T44 INPUT
tl_i.a_mask[3:0] Yes Yes T28,T154,T44 Yes T28,T154,T44 INPUT
tl_i.a_address[5:0] Yes Yes *T77,*T78,*T82 Yes T77,T78,T82 INPUT
tl_i.a_address[15:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[16] Yes Yes *T28,*T154,*T44 Yes T28,T154,T44 INPUT
tl_i.a_address[19:17] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[21:20] Yes Yes T28,T154,T44 Yes T28,T154,T44 INPUT
tl_i.a_address[29:22] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T28,*T154,*T44 Yes T28,T154,T44 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes *T77,*T78,*T82 Yes T77,T78,T82 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T77,T78,T82 Yes T77,T78,T82 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T77,T78,T82 Yes T77,T78,T82 INPUT
tl_i.a_valid Yes Yes T28,T154,T44 Yes T28,T154,T44 INPUT
tl_o.a_ready Yes Yes T28,T154,T44 Yes T28,T154,T44 OUTPUT
tl_o.d_error Yes Yes T77,T78,T82 Yes T77,T78,T82 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T28,T154,T352 Yes T28,T154,T352 OUTPUT
tl_o.d_user.rsp_intg[6:0] Yes Yes T28,T154,T352 Yes T28,T154,T44 OUTPUT
tl_o.d_data[31:0] Yes Yes T28,T154,T352 Yes T28,T154,T352 OUTPUT
tl_o.d_sink Yes Yes T77,T78,T82 Yes T77,T78,T82 OUTPUT
tl_o.d_source[5:0] Yes Yes *T77,*T78,*T82 Yes T77,T78,T82 OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[1:0] Yes Yes T77,T78,T82 Yes T77,T78,T82 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T28,*T154,*T352 Yes T28,T154,T352 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T28,T154,T44 Yes T28,T154,T44 OUTPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T84,T44,T45 Yes T84,T44,T45 INPUT
alert_rx_i[0].ping_n Yes Yes T84,T85,T86 Yes T84,T85,T86 INPUT
alert_rx_i[0].ping_p Yes Yes T84,T85,T86 Yes T84,T85,T86 INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T84,T44,T45 Yes T84,T44,T45 OUTPUT
cio_sck_o Yes Yes T28,T189,T198 Yes T28,T189,T198 OUTPUT
cio_sck_en_o Yes Yes T132,T148,T382 Yes T28,T189,T198 OUTPUT
cio_csb_o Yes Yes T28,T189,T198 Yes T28,T189,T198 OUTPUT
cio_csb_en_o Yes Yes T132,T148,T382 Yes T28,T189,T198 OUTPUT
cio_sd_o[0] Yes Yes *T28 Yes T28 OUTPUT
cio_sd_o[1] No No Yes T189,T198,T202 OUTPUT
cio_sd_o[2] No No No OUTPUT
cio_sd_o[3] No No Yes T189,T198,T202 OUTPUT
cio_sd_en_o[3:0] Yes Yes T28,T189,T198 Yes T28,T189,T198 OUTPUT
cio_sd_i[3:0] Yes Yes T28,T189,T198 Yes T28,T13,T29 INPUT
passthrough_i.s_en[3:0] Unreachable Unreachable Unreachable INPUT
passthrough_i.s[3:0] Unreachable Unreachable Unreachable INPUT
passthrough_i.csb_en Unreachable Unreachable Unreachable INPUT
passthrough_i.csb Unreachable Unreachable Unreachable INPUT
passthrough_i.sck_en Unreachable Unreachable Unreachable INPUT
passthrough_i.sck Unreachable Unreachable Unreachable INPUT
passthrough_i.passthrough_en Unreachable Unreachable Unreachable INPUT
passthrough_o.s[3:0] Unreachable Unreachable Unreachable OUTPUT
intr_error_o Yes Yes T154,T155,T156 Yes T154,T155,T156 OUTPUT
intr_spi_event_o Yes Yes T154,T155,T156 Yes T154,T155,T156 OUTPUT

*Tests covering at least one bit in the range
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%