Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_uart0.uart_core.u_uart_txfifo

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	534068279	62352441	0	0
DepthKnown_A	534068279	533958913	0	0
RvalidKnown_A	534068279	533958913	0	0
WreadyKnown_A	534068279	533958913	0	0
gen_passthru_fifo.paramCheckPass	1035	1035	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	534068279	62352441	0	0
T1	817277	696269	0	0
T2	262926	141208	0	0
T3	135354	18407	0	0
T4	226253	21916	0	0
T5	236292	32062	0	0
T6	413134	209796	0	0
T27	796820	125364	0	0
T39	127996	141758	0	0
T87	151067	54537	0	0
T88	254340	212100	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	534068279	533958913	0	0
T1	817277	817215	0	0
T2	262926	262751	0	0
T3	135354	135299	0	0
T4	226253	226129	0	0
T5	236292	236241	0	0
T6	413134	412853	0	0
T27	796820	796765	0	0
T39	127996	127991	0	0
T87	151067	151061	0	0
T88	254340	254285	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	534068279	533958913	0	0
T1	817277	817215	0	0
T2	262926	262751	0	0
T3	135354	135299	0	0
T4	226253	226129	0	0
T5	236292	236241	0	0
T6	413134	412853	0	0
T27	796820	796765	0	0
T39	127996	127991	0	0
T87	151067	151061	0	0
T88	254340	254285	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	534068279	533958913	0	0
T1	817277	817215	0	0
T2	262926	262751	0	0
T3	135354	135299	0	0
T4	226253	226129	0	0
T5	236292	236241	0	0
T6	413134	412853	0	0
T27	796820	796765	0	0
T39	127996	127991	0	0
T87	151067	151061	0	0
T88	254340	254285	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1035	1035	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T27	1	1	0	0
T39	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	534068279	48010654	0	0
DepthKnown_A	534068279	533958913	0	0
RvalidKnown_A	534068279	533958913	0	0
WreadyKnown_A	534068279	533958913	0	0
gen_passthru_fifo.paramCheckPass	1035	1035	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	534068279	48010654	0	0
T1	817277	293286	0	0
T2	262926	70787	0	0
T3	135354	13226	0	0
T4	226253	15755	0	0
T5	236292	27812	0	0
T6	413134	105249	0	0
T27	796820	112326	0	0
T39	127996	122749	0	0
T87	151067	50516	0	0
T88	254340	105241	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	534068279	533958913	0	0
T1	817277	817215	0	0
T2	262926	262751	0	0
T3	135354	135299	0	0
T4	226253	226129	0	0
T5	236292	236241	0	0
T6	413134	412853	0	0
T27	796820	796765	0	0
T39	127996	127991	0	0
T87	151067	151061	0	0
T88	254340	254285	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	534068279	533958913	0	0
T1	817277	817215	0	0
T2	262926	262751	0	0
T3	135354	135299	0	0
T4	226253	226129	0	0
T5	236292	236241	0	0
T6	413134	412853	0	0
T27	796820	796765	0	0
T39	127996	127991	0	0
T87	151067	151061	0	0
T88	254340	254285	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	534068279	533958913	0	0
T1	817277	817215	0	0
T2	262926	262751	0	0
T3	135354	135299	0	0
T4	226253	226129	0	0
T5	236292	236241	0	0
T6	413134	412853	0	0
T27	796820	796765	0	0
T39	127996	127991	0	0
T87	151067	151061	0	0
T88	254340	254285	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1035	1035	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T27	1	1	0	0
T39	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	534068279	44270055	0	0
DepthKnown_A	534068279	533958913	0	0
RvalidKnown_A	534068279	533958913	0	0
WreadyKnown_A	534068279	533958913	0	0
gen_passthru_fifo.paramCheckPass	1035	1035	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	534068279	44270055	0	0
T1	817277	248364	0	0
T2	262926	11998	0	0
T3	135354	7386	0	0
T4	226253	8507	0	0
T5	236292	13739	0	0
T6	413134	15370	0	0
T27	796820	83715	0	0
T39	127996	180144	0	0
T87	151067	43942	0	0
T88	254340	8886	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	534068279	533958913	0	0
T1	817277	817215	0	0
T2	262926	262751	0	0
T3	135354	135299	0	0
T4	226253	226129	0	0
T5	236292	236241	0	0
T6	413134	412853	0	0
T27	796820	796765	0	0
T39	127996	127991	0	0
T87	151067	151061	0	0
T88	254340	254285	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	534068279	533958913	0	0
T1	817277	817215	0	0
T2	262926	262751	0	0
T3	135354	135299	0	0
T4	226253	226129	0	0
T5	236292	236241	0	0
T6	413134	412853	0	0
T27	796820	796765	0	0
T39	127996	127991	0	0
T87	151067	151061	0	0
T88	254340	254285	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	534068279	533958913	0	0
T1	817277	817215	0	0
T2	262926	262751	0	0
T3	135354	135299	0	0
T4	226253	226129	0	0
T5	236292	236241	0	0
T6	413134	412853	0	0
T27	796820	796765	0	0
T39	127996	127991	0	0
T87	151067	151061	0	0
T88	254340	254285	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1035	1035	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T27	1	1	0	0
T39	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	534068279	37162281	0	0
DepthKnown_A	534068279	533958913	0	0
RvalidKnown_A	534068279	533958913	0	0
WreadyKnown_A	534068279	533958913	0	0
gen_passthru_fifo.paramCheckPass	1035	1035	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	534068279	37162281	0	0
T1	817277	57740	0	0
T2	262926	11218	0	0
T3	135354	7108	0	0
T4	226253	8220	0	0
T5	236292	13484	0	0
T6	413134	14371	0	0
T27	796820	83209	0	0
T39	127996	114362	0	0
T87	151067	43767	0	0
T88	254340	7437	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	534068279	533958913	0	0
T1	817277	817215	0	0
T2	262926	262751	0	0
T3	135354	135299	0	0
T4	226253	226129	0	0
T5	236292	236241	0	0
T6	413134	412853	0	0
T27	796820	796765	0	0
T39	127996	127991	0	0
T87	151067	151061	0	0
T88	254340	254285	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	534068279	533958913	0	0
T1	817277	817215	0	0
T2	262926	262751	0	0
T3	135354	135299	0	0
T4	226253	226129	0	0
T5	236292	236241	0	0
T6	413134	412853	0	0
T27	796820	796765	0	0
T39	127996	127991	0	0
T87	151067	151061	0	0
T88	254340	254285	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	534068279	533958913	0	0
T1	817277	817215	0	0
T2	262926	262751	0	0
T3	135354	135299	0	0
T4	226253	226129	0	0
T5	236292	236241	0	0
T6	413134	412853	0	0
T27	796820	796765	0	0
T39	127996	127991	0	0
T87	151067	151061	0	0
T88	254340	254285	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1035	1035	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T27	1	1	0	0
T39	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	611404890	90336	0	0
DepthKnown_A	611404890	611279509	0	0
RvalidKnown_A	611404890	611279509	0	0
WreadyKnown_A	611404890	611279509	0	0
gen_passthru_fifo.paramCheckPass	2944	2944	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611404890	90336	0	0
T1	817277	2	0	0
T2	262926	44	0	0
T3	135354	26	0	0
T4	226253	35	0	0
T5	236292	30	0	0
T6	413134	73	0	0
T27	796820	75	0	0
T39	127996	34	0	0
T87	151067	29	0	0
T88	254340	27	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611404890	611279509	0	0
T1	817277	817215	0	0
T2	262926	262751	0	0
T3	135354	135299	0	0
T4	226253	226129	0	0
T5	236292	236241	0	0
T6	413134	412853	0	0
T27	796820	796765	0	0
T39	127996	127991	0	0
T87	151067	151061	0	0
T88	254340	254285	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611404890	611279509	0	0
T1	817277	817215	0	0
T2	262926	262751	0	0
T3	135354	135299	0	0
T4	226253	226129	0	0
T5	236292	236241	0	0
T6	413134	412853	0	0
T27	796820	796765	0	0
T39	127996	127991	0	0
T87	151067	151061	0	0
T88	254340	254285	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611404890	611279509	0	0
T1	817277	817215	0	0
T2	262926	262751	0	0
T3	135354	135299	0	0
T4	226253	226129	0	0
T5	236292	236241	0	0
T6	413134	412853	0	0
T27	796820	796765	0	0
T39	127996	127991	0	0
T87	151067	151061	0	0
T88	254340	254285	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2944	2944	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T27	1	1	0	0
T39	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	611404890	91306	0	0
DepthKnown_A	611404890	611279509	0	0
RvalidKnown_A	611404890	611279509	0	0
WreadyKnown_A	611404890	611279509	0	0
gen_passthru_fifo.paramCheckPass	2944	2944	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611404890	91306	0	0
T1	817277	2	0	0
T2	262926	44	0	0
T3	135354	26	0	0
T4	226253	35	0	0
T5	236292	30	0	0
T6	413134	73	0	0
T27	796820	75	0	0
T39	127996	34	0	0
T87	151067	29	0	0
T88	254340	27	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611404890	611279509	0	0
T1	817277	817215	0	0
T2	262926	262751	0	0
T3	135354	135299	0	0
T4	226253	226129	0	0
T5	236292	236241	0	0
T6	413134	412853	0	0
T27	796820	796765	0	0
T39	127996	127991	0	0
T87	151067	151061	0	0
T88	254340	254285	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611404890	611279509	0	0
T1	817277	817215	0	0
T2	262926	262751	0	0
T3	135354	135299	0	0
T4	226253	226129	0	0
T5	236292	236241	0	0
T6	413134	412853	0	0
T27	796820	796765	0	0
T39	127996	127991	0	0
T87	151067	151061	0	0
T88	254340	254285	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611404890	611279509	0	0
T1	817277	817215	0	0
T2	262926	262751	0	0
T3	135354	135299	0	0
T4	226253	226129	0	0
T5	236292	236241	0	0
T6	413134	412853	0	0
T27	796820	796765	0	0
T39	127996	127991	0	0
T87	151067	151061	0	0
T88	254340	254285	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2944	2944	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T27	1	1	0	0
T39	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	611404890	52693	0	0
DepthKnown_A	611404890	611279509	0	0
RvalidKnown_A	611404890	611279509	0	0
WreadyKnown_A	611404890	611279509	0	0
gen_passthru_fifo.paramCheckPass	2944	2944	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611404890	52693	0	0
T1	817277	1	0	0
T2	262926	39	0	0
T3	135354	23	0	0
T4	226253	29	0	0
T5	236292	23	0	0
T6	413134	69	0	0
T27	796820	40	0	0
T39	127996	5	0	0
T87	151067	28	0	0
T88	254340	26	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611404890	611279509	0	0
T1	817277	817215	0	0
T2	262926	262751	0	0
T3	135354	135299	0	0
T4	226253	226129	0	0
T5	236292	236241	0	0
T6	413134	412853	0	0
T27	796820	796765	0	0
T39	127996	127991	0	0
T87	151067	151061	0	0
T88	254340	254285	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611404890	611279509	0	0
T1	817277	817215	0	0
T2	262926	262751	0	0
T3	135354	135299	0	0
T4	226253	226129	0	0
T5	236292	236241	0	0
T6	413134	412853	0	0
T27	796820	796765	0	0
T39	127996	127991	0	0
T87	151067	151061	0	0
T88	254340	254285	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611404890	611279509	0	0
T1	817277	817215	0	0
T2	262926	262751	0	0
T3	135354	135299	0	0
T4	226253	226129	0	0
T5	236292	236241	0	0
T6	413134	412853	0	0
T27	796820	796765	0	0
T39	127996	127991	0	0
T87	151067	151061	0	0
T88	254340	254285	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2944	2944	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T27	1	1	0	0
T39	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	611404890	52693	0	0
DepthKnown_A	611404890	611279509	0	0
RvalidKnown_A	611404890	611279509	0	0
WreadyKnown_A	611404890	611279509	0	0
gen_passthru_fifo.paramCheckPass	2944	2944	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611404890	52693	0	0
T1	817277	1	0	0
T2	262926	39	0	0
T3	135354	23	0	0
T4	226253	29	0	0
T5	236292	23	0	0
T6	413134	69	0	0
T27	796820	40	0	0
T39	127996	5	0	0
T87	151067	28	0	0
T88	254340	26	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611404890	611279509	0	0
T1	817277	817215	0	0
T2	262926	262751	0	0
T3	135354	135299	0	0
T4	226253	226129	0	0
T5	236292	236241	0	0
T6	413134	412853	0	0
T27	796820	796765	0	0
T39	127996	127991	0	0
T87	151067	151061	0	0
T88	254340	254285	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611404890	611279509	0	0
T1	817277	817215	0	0
T2	262926	262751	0	0
T3	135354	135299	0	0
T4	226253	226129	0	0
T5	236292	236241	0	0
T6	413134	412853	0	0
T27	796820	796765	0	0
T39	127996	127991	0	0
T87	151067	151061	0	0
T88	254340	254285	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611404890	611279509	0	0
T1	817277	817215	0	0
T2	262926	262751	0	0
T3	135354	135299	0	0
T4	226253	226129	0	0
T5	236292	236241	0	0
T6	413134	412853	0	0
T27	796820	796765	0	0
T39	127996	127991	0	0
T87	151067	151061	0	0
T88	254340	254285	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2944	2944	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T27	1	1	0	0
T39	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	611404890	37643	0	0
DepthKnown_A	611404890	611279509	0	0
RvalidKnown_A	611404890	611279509	0	0
WreadyKnown_A	611404890	611279509	0	0
gen_passthru_fifo.paramCheckPass	2944	2944	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611404890	37643	0	0
T1	817277	1	0	0
T2	262926	5	0	0
T3	135354	3	0	0
T4	226253	6	0	0
T5	236292	7	0	0
T6	413134	4	0	0
T27	796820	35	0	0
T39	127996	29	0	0
T87	151067	1	0	0
T88	254340	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611404890	611279509	0	0
T1	817277	817215	0	0
T2	262926	262751	0	0
T3	135354	135299	0	0
T4	226253	226129	0	0
T5	236292	236241	0	0
T6	413134	412853	0	0
T27	796820	796765	0	0
T39	127996	127991	0	0
T87	151067	151061	0	0
T88	254340	254285	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611404890	611279509	0	0
T1	817277	817215	0	0
T2	262926	262751	0	0
T3	135354	135299	0	0
T4	226253	226129	0	0
T5	236292	236241	0	0
T6	413134	412853	0	0
T27	796820	796765	0	0
T39	127996	127991	0	0
T87	151067	151061	0	0
T88	254340	254285	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611404890	611279509	0	0
T1	817277	817215	0	0
T2	262926	262751	0	0
T3	135354	135299	0	0
T4	226253	226129	0	0
T5	236292	236241	0	0
T6	413134	412853	0	0
T27	796820	796765	0	0
T39	127996	127991	0	0
T87	151067	151061	0	0
T88	254340	254285	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2944	2944	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T27	1	1	0	0
T39	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	611404890	38613	0	0
DepthKnown_A	611404890	611279509	0	0
RvalidKnown_A	611404890	611279509	0	0
WreadyKnown_A	611404890	611279509	0	0
gen_passthru_fifo.paramCheckPass	2944	2944	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611404890	38613	0	0
T1	817277	1	0	0
T2	262926	5	0	0
T3	135354	3	0	0
T4	226253	6	0	0
T5	236292	7	0	0
T6	413134	4	0	0
T27	796820	35	0	0
T39	127996	29	0	0
T87	151067	1	0	0
T88	254340	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611404890	611279509	0	0
T1	817277	817215	0	0
T2	262926	262751	0	0
T3	135354	135299	0	0
T4	226253	226129	0	0
T5	236292	236241	0	0
T6	413134	412853	0	0
T27	796820	796765	0	0
T39	127996	127991	0	0
T87	151067	151061	0	0
T88	254340	254285	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611404890	611279509	0	0
T1	817277	817215	0	0
T2	262926	262751	0	0
T3	135354	135299	0	0
T4	226253	226129	0	0
T5	236292	236241	0	0
T6	413134	412853	0	0
T27	796820	796765	0	0
T39	127996	127991	0	0
T87	151067	151061	0	0
T88	254340	254285	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611404890	611279509	0	0
T1	817277	817215	0	0
T2	262926	262751	0	0
T3	135354	135299	0	0
T4	226253	226129	0	0
T5	236292	236241	0	0
T6	413134	412853	0	0
T27	796820	796765	0	0
T39	127996	127991	0	0
T87	151067	151061	0	0
T88	254340	254285	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2944	2944	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T27	1	1	0	0
T39	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0