Unified Coverage Report :: Module :: uart

Module : uart

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_uart_0.1/rtl/uart.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_uart0	100.00			100.00
tb.dut.top_earlgrey.u_uart1	100.00			100.00
tb.dut.top_earlgrey.u_uart2	100.00			100.00
tb.dut.top_earlgrey.u_uart3	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_uart0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	92.47		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	92.47		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	92.47		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart3

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	92.47		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : uart

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	308	308	100.00
Total Bits 0->1	154	154	100.00
Total Bits 1->0	154	154	100.00

Ports	40	40	100.00
Port Bits	308	308	100.00
Port Bits 0->1	154	154	100.00
Port Bits 1->0	154	154	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T4,T6	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T39,T40	Yes	T1,T39,T40	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T39,T40	Yes	T1,T39,T40	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T77,*T78,*T79	Yes	T77,T78,T79	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T1,*T65,*T80	Yes	T1,T65,T80	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T68,T50,T81	Yes	T68,T50,T81	INPUT
tl_i.a_valid	Yes	Yes	T1,T39,T40	Yes	T1,T39,T40	INPUT
tl_o.a_ready	Yes	Yes	T1,T39,T40	Yes	T1,T39,T40	OUTPUT
tl_o.d_error	Yes	Yes	T77,T78,T82	Yes	T77,T78,T82	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T39,T40,T123	Yes	T39,T40,T123	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T1,T39,T40	Yes	T1,T39,T40	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T39,T40	Yes	T1,T39,T40	OUTPUT
tl_o.d_sink	Yes	Yes	T77,T78,T82	Yes	T77,T78,T79	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T1,*T65,*T68	Yes	T1,T65,T68	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T77,T78,T82	Yes	T77,T78,T79	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T39,*T40	Yes	T1,T39,T40	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T39,T40	Yes	T1,T39,T40	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T3,T267,T158	Yes	T3,T267,T158	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T158,T84,T85	Yes	T158,T84,T85	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T158,T84,T85	Yes	T158,T84,T85	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T3,T267,T158	Yes	T3,T267,T158	OUTPUT
cio_rx_i	Yes	Yes	T2,T4,T6	Yes	T1,T2,T3	INPUT
cio_tx_o	Yes	Yes	T1,T39,T40	Yes	T1,T39,T40	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T123,T95,T281	Yes	T123,T95,T281	OUTPUT
intr_tx_empty_o	Yes	Yes	T123,T95,T281	Yes	T123,T95,T281	OUTPUT
intr_rx_watermark_o	Yes	Yes	T123,T95,T281	Yes	T123,T95,T281	OUTPUT
intr_tx_done_o	Yes	Yes	T123,T95,T281	Yes	T123,T95,T281	OUTPUT
intr_rx_overflow_o	Yes	Yes	T123,T95,T281	Yes	T123,T95,T281	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T95,T297,T298	Yes	T95,T297,T298	OUTPUT
intr_rx_break_err_o	Yes	Yes	T95,T297,T298	Yes	T95,T297,T298	OUTPUT
intr_rx_timeout_o	Yes	Yes	T95,T297,T298	Yes	T95,T297,T298	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T95,T297,T298	Yes	T95,T297,T298	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart0

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	304	304	100.00
Total Bits 0->1	152	152	100.00
Total Bits 1->0	152	152	100.00

Ports	40	40	100.00
Port Bits	304	304	100.00
Port Bits 0->1	152	152	100.00
Port Bits 1->0	152	152	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T4,T6	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T39,T40	Yes	T1,T39,T40	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T39,T40	Yes	T1,T39,T40	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T77,*T78,*T79	Yes	T77,T78,T79	INPUT
tl_i.a_address[29:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T1,*T65,*T80	Yes	T1,T65,T80	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T68,T50,T81	Yes	T68,T50,T81	INPUT
tl_i.a_valid	Yes	Yes	T1,T39,T40	Yes	T1,T39,T40	INPUT
tl_o.a_ready	Yes	Yes	T1,T39,T40	Yes	T1,T39,T40	OUTPUT
tl_o.d_error	Yes	Yes	T77,T78,T82	Yes	T77,T78,T82	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T39,T40,T95	Yes	T39,T40,T95	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T1,T39,T40	Yes	T1,T39,T40	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T39,T40	Yes	T1,T39,T40	OUTPUT
tl_o.d_sink	Yes	Yes	T77,T78,T82	Yes	T77,T78,T79	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T1,*T65,*T68	Yes	T1,T65,T68	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T77,T78,T82	Yes	T77,T78,T79	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T39,*T40	Yes	T1,T39,T40	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T39,T40	Yes	T1,T39,T40	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T84,T159,T44	Yes	T84,T159,T44	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T84,T159,T44	Yes	T84,T159,T44	OUTPUT
cio_rx_i	Yes	Yes	T2,T4,T6	Yes	T1,T2,T3	INPUT
cio_tx_o	Yes	Yes	T1,T39,T40	Yes	T1,T39,T40	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T95,T214,T215	Yes	T95,T214,T215	OUTPUT
intr_tx_empty_o	Yes	Yes	T95,T214,T215	Yes	T95,T214,T215	OUTPUT
intr_rx_watermark_o	Yes	Yes	T95,T214,T215	Yes	T95,T214,T215	OUTPUT
intr_tx_done_o	Yes	Yes	T95,T214,T215	Yes	T95,T214,T215	OUTPUT
intr_rx_overflow_o	Yes	Yes	T95,T214,T215	Yes	T95,T214,T215	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T95,T297,T298	Yes	T95,T297,T298	OUTPUT
intr_rx_break_err_o	Yes	Yes	T95,T297,T298	Yes	T95,T297,T298	OUTPUT
intr_rx_timeout_o	Yes	Yes	T95,T297,T298	Yes	T95,T297,T298	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T95,T297,T298	Yes	T95,T297,T298	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart1

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	306	306	100.00
Total Bits 0->1	153	153	100.00
Total Bits 1->0	153	153	100.00

Ports	40	40	100.00
Port Bits	306	306	100.00
Port Bits 0->1	153	153	100.00
Port Bits 1->0	153	153	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T4,T6	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T95,T68,T206	Yes	T95,T68,T206	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T95,T68,T206	Yes	T95,T68,T206	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T77,*T78,*T79	Yes	T77,T78,T79	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T1,*T65,*T80	Yes	T1,T65,T80	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T68,T50,T81	Yes	T68,T50,T81	INPUT
tl_i.a_valid	Yes	Yes	T95,T159,T44	Yes	T95,T159,T44	INPUT
tl_o.a_ready	Yes	Yes	T95,T159,T44	Yes	T95,T159,T44	OUTPUT
tl_o.d_error	Yes	Yes	T77,T78,T82	Yes	T77,T78,T82	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T95,T68,T206	Yes	T95,T68,T206	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T95,T159,T68	Yes	T95,T159,T44	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T95,T159,T68	Yes	T95,T159,T44	OUTPUT
tl_o.d_sink	Yes	Yes	T78,T82,T153	Yes	T77,T78,T82	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T68,*T77,*T78	Yes	T68,T78,T82	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T77,T78,T82	Yes	T77,T78,T82	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T95,*T68,*T206	Yes	T95,T68,T206	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T95,T159,T44	Yes	T95,T159,T44	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T158,T84,T159	Yes	T158,T84,T159	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T158,T84,T85	Yes	T158,T84,T85	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T158,T84,T85	Yes	T158,T84,T85	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T158,T84,T159	Yes	T158,T84,T159	OUTPUT
cio_rx_i	Yes	Yes	T28,T206,T306	Yes	T28,T206,T13	INPUT
cio_tx_o	Yes	Yes	T68,T206,T306	Yes	T68,T206,T306	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T95,T68,T206	Yes	T95,T68,T206	OUTPUT
intr_tx_empty_o	Yes	Yes	T95,T206,T306	Yes	T95,T206,T306	OUTPUT
intr_rx_watermark_o	Yes	Yes	T95,T206,T306	Yes	T95,T206,T306	OUTPUT
intr_tx_done_o	Yes	Yes	T95,T206,T306	Yes	T95,T206,T306	OUTPUT
intr_rx_overflow_o	Yes	Yes	T95,T206,T306	Yes	T95,T206,T306	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T95,T297,T298	Yes	T95,T297,T298	OUTPUT
intr_rx_break_err_o	Yes	Yes	T95,T297,T298	Yes	T95,T297,T298	OUTPUT
intr_rx_timeout_o	Yes	Yes	T95,T297,T298	Yes	T95,T297,T298	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T95,T297,T298	Yes	T95,T297,T298	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart2

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	306	306	100.00
Total Bits 0->1	153	153	100.00
Total Bits 1->0	153	153	100.00

Ports	40	40	100.00
Port Bits	306	306	100.00
Port Bits 0->1	153	153	100.00
Port Bits 1->0	153	153	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T4,T6	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T123,T95,T281	Yes	T123,T95,T281	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T123,T95,T281	Yes	T123,T95,T281	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T77,*T78,*T79	Yes	T77,T78,T79	INPUT
tl_i.a_address[16:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T1,*T65,*T80	Yes	T1,T65,T80	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T68,T50,T81	Yes	T68,T50,T81	INPUT
tl_i.a_valid	Yes	Yes	T123,T95,T281	Yes	T123,T95,T281	INPUT
tl_o.a_ready	Yes	Yes	T123,T95,T281	Yes	T123,T95,T281	OUTPUT
tl_o.d_error	Yes	Yes	T77,T78,T82	Yes	T77,T78,T82	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T123,T95,T281	Yes	T123,T95,T281	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T123,T95,T281	Yes	T123,T95,T281	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T123,T95,T281	Yes	T123,T95,T281	OUTPUT
tl_o.d_sink	Yes	Yes	T77,T78,T82	Yes	T77,T78,T82	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T68,*T77,*T78	Yes	T68,T77,T78	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T77,T78,T82	Yes	T77,T78,T82	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T123,*T95,*T281	Yes	T123,T95,T281	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T123,T95,T281	Yes	T123,T95,T281	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T3,T158,T84	Yes	T3,T158,T84	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T158,T84,T85	Yes	T158,T85,T86	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T158,T85,T86	Yes	T158,T84,T85	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T3,T158,T84	Yes	T3,T158,T84	OUTPUT
cio_rx_i	Yes	Yes	T123,T281,T309	Yes	T123,T281,T309	INPUT
cio_tx_o	Yes	Yes	T123,T281,T309	Yes	T123,T281,T309	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T123,T95,T281	Yes	T123,T95,T281	OUTPUT
intr_tx_empty_o	Yes	Yes	T123,T95,T281	Yes	T123,T95,T281	OUTPUT
intr_rx_watermark_o	Yes	Yes	T123,T95,T281	Yes	T123,T95,T281	OUTPUT
intr_tx_done_o	Yes	Yes	T123,T95,T281	Yes	T123,T95,T281	OUTPUT
intr_rx_overflow_o	Yes	Yes	T123,T95,T281	Yes	T123,T95,T281	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T95,T297,T298	Yes	T95,T297,T298	OUTPUT
intr_rx_break_err_o	Yes	Yes	T95,T297,T298	Yes	T95,T297,T298	OUTPUT
intr_rx_timeout_o	Yes	Yes	T95,T297,T298	Yes	T95,T297,T298	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T95,T297,T298	Yes	T95,T297,T298	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart3

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	308	308	100.00
Total Bits 0->1	154	154	100.00
Total Bits 1->0	154	154	100.00

Ports	40	40	100.00
Port Bits	308	308	100.00
Port Bits 0->1	154	154	100.00
Port Bits 1->0	154	154	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T4,T6	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T95,T68,T293	Yes	T95,T68,T293	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T95,T68,T293	Yes	T95,T68,T293	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T77,*T78,*T79	Yes	T77,T78,T79	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T1,*T65,*T80	Yes	T1,T65,T80	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T68,T50,T81	Yes	T68,T50,T81	INPUT
tl_i.a_valid	Yes	Yes	T95,T159,T44	Yes	T95,T159,T44	INPUT
tl_o.a_ready	Yes	Yes	T95,T159,T44	Yes	T95,T159,T44	OUTPUT
tl_o.d_error	Yes	Yes	T78,T82,T153	Yes	T78,T82,T153	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T95,T68,T293	Yes	T95,T68,T293	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T95,T159,T68	Yes	T95,T159,T44	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T95,T159,T68	Yes	T95,T159,T44	OUTPUT
tl_o.d_sink	Yes	Yes	T77,T78,T82	Yes	T77,T78,T82	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T68,*T77,*T78	Yes	T68,T78,T82	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T77,T78,T82	Yes	T77,T78,T82	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T95,*T68,*T293	Yes	T95,T68,T293	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T95,T159,T44	Yes	T95,T159,T44	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T267,T84,T159	Yes	T267,T84,T159	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T84,T85,T86	Yes	T84,T85,T418	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T84,T85,T418	Yes	T84,T85,T86	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T267,T84,T159	Yes	T267,T84,T159	OUTPUT
cio_rx_i	Yes	Yes	T293,T294,T295	Yes	T293,T294,T295	INPUT
cio_tx_o	Yes	Yes	T68,T293,T294	Yes	T68,T293,T294	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T95,T68,T293	Yes	T95,T68,T293	OUTPUT
intr_tx_empty_o	Yes	Yes	T95,T293,T294	Yes	T95,T293,T294	OUTPUT
intr_rx_watermark_o	Yes	Yes	T95,T293,T294	Yes	T95,T293,T294	OUTPUT
intr_tx_done_o	Yes	Yes	T95,T293,T294	Yes	T95,T293,T294	OUTPUT
intr_rx_overflow_o	Yes	Yes	T95,T293,T294	Yes	T95,T293,T294	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T95,T297,T298	Yes	T95,T297,T298	OUTPUT
intr_rx_break_err_o	Yes	Yes	T95,T297,T298	Yes	T95,T297,T298	OUTPUT
intr_rx_timeout_o	Yes	Yes	T95,T297,T298	Yes	T95,T297,T298	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T95,T297,T298	Yes	T95,T297,T298	OUTPUT

*Tests covering at least one bit in the range