Unified Coverage Report :: Module :: xbar_main

Module : xbar_main

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_top_earlgrey_xbar_main_0.1/rtl/autogen/xbar_main.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_xbar_main	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_xbar_main

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	92.47		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : xbar_main

	Total	Covered	Percent
Totals	550	550	100.00
Total Bits	6824	6824	100.00
Total Bits 0->1	3412	3412	100.00
Total Bits 1->0	3412	3412	100.00

Ports	550	550	100.00
Port Bits	6824	6824	100.00
Port Bits 0->1	3412	3412	100.00
Port Bits 1->0	3412	3412	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_main_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_fixed_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_usb_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_spi_host0_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_spi_host1_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_main_ni	Yes	Yes	T2,T4,T6	Yes	T1,T2,T3	INPUT
rst_fixed_ni	Yes	Yes	T2,T4,T6	Yes	T1,T2,T3	INPUT
rst_usb_ni	Yes	Yes	T2,T4,T6	Yes	T1,T2,T3	INPUT
rst_spi_host0_ni	Yes	Yes	T2,T4,T6	Yes	T1,T2,T3	INPUT
rst_spi_host1_ni	Yes	Yes	T2,T4,T6	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.d_ready	Yes	Yes	T77,T79,T217	Yes	T77,T78,T79	INPUT
tl_rv_core_ibex__corei_i.a_user.data_intg[6:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_rv_core_ibex__corei_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.a_user.instr_type[3:0]	Yes	Yes	T217,T240,T241	Yes	T217,T240,T241	INPUT
tl_rv_core_ibex__corei_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_data[31:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_rv_core_ibex__corei_i.a_mask[3:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_rv_core_ibex__corei_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_rv_core_ibex__corei_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_opcode[2:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_rv_core_ibex__corei_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_error	Yes	Yes	T1,T65,T60	Yes	T1,T65,T60	OUTPUT
tl_rv_core_ibex__corei_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_user.rsp_intg[6:0]	Yes	Yes	T1,T65,T60	Yes	T1,T65,T60	OUTPUT
tl_rv_core_ibex__corei_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_sink	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_rv_core_ibex__corei_o.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_rv_core_ibex__corei_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_i.d_ready	Yes	Yes	T68,T50,T81	Yes	T68,T50,T81	INPUT
tl_rv_core_ibex__cored_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_user.instr_type[3:0]	Yes	Yes	T81,T77,T242	Yes	T81,T77,T242	INPUT
tl_rv_core_ibex__cored_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_mask[3:0]	Yes	Yes	T2,T3,T27	Yes	T2,T3,T27	INPUT
tl_rv_core_ibex__cored_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_size[1:0]	Yes	Yes	T81,T77,T78	Yes	T81,T77,T78	INPUT
tl_rv_core_ibex__cored_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_opcode[2:0]	Yes	Yes	T2,T3,T27	Yes	T2,T3,T27	INPUT
tl_rv_core_ibex__cored_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_error	Yes	Yes	T1,T4,T59	Yes	T1,T4,T59	OUTPUT
tl_rv_core_ibex__cored_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_sink	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_rv_core_ibex__cored_o.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_rv_core_ibex__cored_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__sba_i.d_ready	Yes	Yes	T2,T4,T6	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_user.data_intg[6:0]	Yes	Yes	T1,T65,T80	Yes	T1,T65,T80	INPUT
tl_rv_dm__sba_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_user.instr_type[3:0]	Yes	Yes	T2,T4,T6	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_data[31:0]	Yes	Yes	T1,T65,T80	Yes	T1,T65,T80	INPUT
tl_rv_dm__sba_i.a_mask[3:0]	Yes	Yes	T2,T4,T6	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_source[5:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_rv_dm__sba_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_rv_dm__sba_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_opcode[2:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_rv_dm__sba_i.a_valid	Yes	Yes	T1,T65,T80	Yes	T1,T65,T80	INPUT
tl_rv_dm__sba_o.a_ready	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__sba_o.d_error	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_rv_dm__sba_o.d_user.data_intg[6:0]	Yes	Yes	T1,T65,T80	Yes	T1,T65,T80	OUTPUT
tl_rv_dm__sba_o.d_user.rsp_intg[6:0]	Yes	Yes	T1,T65,T68	Yes	T1,T65,T68	OUTPUT
tl_rv_dm__sba_o.d_data[31:0]	Yes	Yes	T1,T65,T80	Yes	T1,T65,T80	OUTPUT
tl_rv_dm__sba_o.d_sink	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_rv_dm__sba_o.d_source[5:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_rv_dm__sba_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_rv_dm__sba_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_opcode[0]	Yes	Yes	*T1,*T65,*T80	Yes	T1,T65,T80	OUTPUT
tl_rv_dm__sba_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_valid	Yes	Yes	T1,T65,T80	Yes	T1,T65,T80	OUTPUT
tl_rv_dm__regs_o.d_ready	Yes	Yes	T2,T4,T6	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__regs_o.a_user.data_intg[6:0]	Yes	Yes	T50,T77,T78	Yes	T50,T77,T78	OUTPUT
tl_rv_dm__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T50,T77,T78	Yes	T50,T77,T78	OUTPUT
tl_rv_dm__regs_o.a_user.instr_type[3:0]	Yes	Yes	T50,T77,T78	Yes	T50,T77,T78	OUTPUT
tl_rv_dm__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_data[31:0]	Yes	Yes	T50,T77,T78	Yes	T50,T77,T78	OUTPUT
tl_rv_dm__regs_o.a_mask[3:0]	Yes	Yes	T50,T77,T78	Yes	T50,T77,T78	OUTPUT
tl_rv_dm__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_source[5:0]	Yes	Yes	*T50,T77,T78	Yes	T50,T77,T78	OUTPUT
tl_rv_dm__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_size[1:0]	Yes	Yes	T77,T78,T82	Yes	T77,T78,T82	OUTPUT
tl_rv_dm__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_opcode[2:0]	Yes	Yes	T77,T78,T82	Yes	T77,T78,T82	OUTPUT
tl_rv_dm__regs_o.a_valid	Yes	Yes	T50,T77,T78	Yes	T50,T77,T78	OUTPUT
tl_rv_dm__regs_i.a_ready	Yes	Yes	T50,T77,T79	Yes	T50,T77,T78	INPUT
tl_rv_dm__regs_i.d_error	Yes	Yes	T78,T82,T153	Yes	T78,T82,T153	INPUT
tl_rv_dm__regs_i.d_user.data_intg[6:0]	Yes	Yes	T50,T77,T78	Yes	T50,T77,T78	INPUT
tl_rv_dm__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T50,T77,T78	Yes	T50,T77,T78	INPUT
tl_rv_dm__regs_i.d_data[31:0]	Yes	Yes	T50,T78,T82	Yes	T50,T77,T78	INPUT
tl_rv_dm__regs_i.d_sink	Yes	Yes	T78,T82,T153	Yes	T77,T78,T82	INPUT
tl_rv_dm__regs_i.d_source[5:0]	Yes	Yes	*T50,T77,T78	Yes	T50,T77,T78	INPUT
tl_rv_dm__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_size[1:0]	Yes	Yes	T77,T78,T82	Yes	T77,T78,T82	INPUT
tl_rv_dm__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_opcode[0]	Yes	Yes	*T50,*T77,*T78	Yes	T50,T77,T78	INPUT
tl_rv_dm__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_valid	Yes	Yes	T50,T77,T78	Yes	T50,T77,T78	INPUT
tl_rv_dm__mem_o.d_ready	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__mem_o.a_user.data_intg[6:0]	Yes	Yes	T1,T65,T80	Yes	T1,T65,T80	OUTPUT
tl_rv_dm__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T65,T80	Yes	T1,T65,T80	OUTPUT
tl_rv_dm__mem_o.a_user.instr_type[3:0]	Yes	Yes	T1,T65,T80	Yes	T1,T65,T80	OUTPUT
tl_rv_dm__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_data[31:0]	Yes	Yes	T1,T65,T80	Yes	T1,T65,T80	OUTPUT
tl_rv_dm__mem_o.a_mask[3:0]	Yes	Yes	T1,T65,T80	Yes	T1,T65,T80	OUTPUT
tl_rv_dm__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_source[5:0]	Yes	Yes	*T1,*T65,*T80	Yes	T1,T65,T80	OUTPUT
tl_rv_dm__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_rv_dm__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_opcode[2:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_rv_dm__mem_o.a_valid	Yes	Yes	T1,T65,T80	Yes	T1,T65,T80	OUTPUT
tl_rv_dm__mem_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_dm__mem_i.d_error	Yes	Yes	T1,T2,T3	Yes	T1,T2,T4	INPUT
tl_rv_dm__mem_i.d_user.data_intg[6:0]	Yes	Yes	T1,T65,T80	Yes	T1,T65,T80	INPUT
tl_rv_dm__mem_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T65,T80	Yes	T1,T65,T80	INPUT
tl_rv_dm__mem_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T4	INPUT
tl_rv_dm__mem_i.d_sink	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_rv_dm__mem_i.d_source[5:0]	Yes	Yes	*T1,*T65,*T80	Yes	T1,T65,T80	INPUT
tl_rv_dm__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_rv_dm__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T4	INPUT
tl_rv_dm__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_valid	Yes	Yes	T1,T65,T80	Yes	T1,T65,T80	INPUT
tl_rom_ctrl__rom_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.data_intg[6:0]	Yes	Yes	T39,T40,T368	Yes	T39,T40,T368	OUTPUT
tl_rom_ctrl__rom_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_data[31:0]	Yes	Yes	T39,T40,T368	Yes	T39,T40,T368	OUTPUT
tl_rom_ctrl__rom_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_rom_ctrl__rom_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_opcode[2:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_rom_ctrl__rom_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_error	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_rom_ctrl__rom_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_sink	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_rom_ctrl__rom_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_rom_ctrl__rom_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_opcode[0]	Yes	Yes	*T77,*T78,*T79	Yes	T77,T78,T79	INPUT
tl_rom_ctrl__rom_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__regs_o.d_ready	Yes	Yes	T2,T4,T6	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__regs_o.a_user.data_intg[6:0]	Yes	Yes	T44,T45,T50	Yes	T44,T45,T50	OUTPUT
tl_rom_ctrl__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T224,T379,T44	Yes	T224,T379,T44	OUTPUT
tl_rom_ctrl__regs_o.a_user.instr_type[3:0]	Yes	Yes	T224,T379,T44	Yes	T224,T379,T44	OUTPUT
tl_rom_ctrl__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_data[31:0]	Yes	Yes	T44,T45,T50	Yes	T44,T45,T50	OUTPUT
tl_rom_ctrl__regs_o.a_mask[3:0]	Yes	Yes	T224,T379,T44	Yes	T224,T379,T44	OUTPUT
tl_rom_ctrl__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_source[5:0]	Yes	Yes	*T50,*T77,*T78	Yes	T50,T77,T78	OUTPUT
tl_rom_ctrl__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_size[1:0]	Yes	Yes	T77,T78,T82	Yes	T77,T78,T82	OUTPUT
tl_rom_ctrl__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_opcode[2:0]	Yes	Yes	T77,T78,T82	Yes	T77,T78,T82	OUTPUT
tl_rom_ctrl__regs_o.a_valid	Yes	Yes	T224,T379,T44	Yes	T224,T379,T44	OUTPUT
tl_rom_ctrl__regs_i.a_ready	Yes	Yes	T224,T379,T44	Yes	T224,T379,T44	INPUT
tl_rom_ctrl__regs_i.d_error	Yes	Yes	T78,T82,T153	Yes	T78,T82,T153	INPUT
tl_rom_ctrl__regs_i.d_user.data_intg[6:0]	Yes	Yes	T224,T379,T380	Yes	T224,T379,T380	INPUT
tl_rom_ctrl__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T50,T77,T78	Yes	T44,T45,T50	INPUT
tl_rom_ctrl__regs_i.d_data[31:0]	Yes	Yes	T224,T379,T50	Yes	T224,T379,T44	INPUT
tl_rom_ctrl__regs_i.d_sink	Yes	Yes	T78,T82,T153	Yes	T78,T82,T153	INPUT
tl_rom_ctrl__regs_i.d_source[5:0]	Yes	Yes	*T50,T77,*T78	Yes	T50,T78,T82	INPUT
tl_rom_ctrl__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_size[1:0]	Yes	Yes	T77,T78,T82	Yes	T78,T82,T153	INPUT
tl_rom_ctrl__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_opcode[0]	Yes	Yes	*T224,*T50,*T381	Yes	T224,T379,T50	INPUT
tl_rom_ctrl__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_valid	Yes	Yes	T224,T379,T44	Yes	T224,T379,T44	INPUT
tl_peri_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_source[5:0]	Yes	Yes	*T1,*T65,*T80	Yes	T1,T65,T80	OUTPUT
tl_peri_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_peri_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_opcode[2:0]	Yes	Yes	T68,T50,T81	Yes	T68,T50,T81	OUTPUT
tl_peri_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_error	Yes	Yes	T60,T107,T232	Yes	T60,T107,T232	INPUT
tl_peri_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_sink	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_peri_i.d_source[5:0]	Yes	Yes	*T1,*T65,*T80	Yes	T1,T65,T80	INPUT
tl_peri_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_peri_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_spi_host0_o.d_ready	Yes	Yes	T11,T154,T12	Yes	T11,T154,T12	OUTPUT
tl_spi_host0_o.a_user.data_intg[6:0]	Yes	Yes	T11,T154,T12	Yes	T11,T154,T12	OUTPUT
tl_spi_host0_o.a_user.cmd_intg[6:0]	Yes	Yes	T11,T154,T12	Yes	T11,T154,T12	OUTPUT
tl_spi_host0_o.a_user.instr_type[3:0]	Yes	Yes	T11,T154,T12	Yes	T11,T154,T12	OUTPUT
tl_spi_host0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_data[31:0]	Yes	Yes	T11,T154,T12	Yes	T11,T154,T12	OUTPUT
tl_spi_host0_o.a_mask[3:0]	Yes	Yes	T11,T154,T12	Yes	T11,T154,T12	OUTPUT
tl_spi_host0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_source[5:0]	Yes	Yes	*T78,*T82,*T153	Yes	T78,T82,T153	OUTPUT
tl_spi_host0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_size[1:0]	Yes	Yes	T77,T78,T82	Yes	T77,T78,T82	OUTPUT
tl_spi_host0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_opcode[2:0]	Yes	Yes	T197,T200,T201	Yes	T197,T200,T201	OUTPUT
tl_spi_host0_o.a_valid	Yes	Yes	T11,T154,T12	Yes	T11,T154,T12	OUTPUT
tl_spi_host0_i.a_ready	Yes	Yes	T11,T154,T12	Yes	T11,T154,T12	INPUT
tl_spi_host0_i.d_error	Yes	Yes	T77,T78,T79	Yes	T77,T78,T82	INPUT
tl_spi_host0_i.d_user.data_intg[6:0]	Yes	Yes	T11,T154,T12	Yes	T11,T154,T12	INPUT
tl_spi_host0_i.d_user.rsp_intg[6:0]	Yes	Yes	T11,T154,T12	Yes	T11,T154,T12	INPUT
tl_spi_host0_i.d_data[31:0]	Yes	Yes	T11,T154,T12	Yes	T11,T154,T12	INPUT
tl_spi_host0_i.d_sink	Yes	Yes	T77,T78,T82	Yes	T77,T78,T82	INPUT
tl_spi_host0_i.d_source[5:0]	Yes	Yes	*T78,*T82,*T153	Yes	T78,T79,T82	INPUT
tl_spi_host0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_size[1:0]	Yes	Yes	T77,T78,T82	Yes	T77,T78,T82	INPUT
tl_spi_host0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_opcode[0]	Yes	Yes	*T11,*T154,*T12	Yes	T11,T154,T12	INPUT
tl_spi_host0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_valid	Yes	Yes	T11,T154,T12	Yes	T11,T154,T12	INPUT
tl_spi_host1_o.d_ready	Yes	Yes	T28,T154,T44	Yes	T28,T154,T44	OUTPUT
tl_spi_host1_o.a_user.data_intg[6:0]	Yes	Yes	T28,T154,T44	Yes	T28,T154,T44	OUTPUT
tl_spi_host1_o.a_user.cmd_intg[6:0]	Yes	Yes	T28,T154,T44	Yes	T28,T154,T44	OUTPUT
tl_spi_host1_o.a_user.instr_type[3:0]	Yes	Yes	T28,T154,T44	Yes	T28,T154,T44	OUTPUT
tl_spi_host1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_data[31:0]	Yes	Yes	T28,T154,T44	Yes	T28,T154,T44	OUTPUT
tl_spi_host1_o.a_mask[3:0]	Yes	Yes	T28,T154,T44	Yes	T28,T154,T44	OUTPUT
tl_spi_host1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_source[5:0]	Yes	Yes	*T77,*T78,*T82	Yes	T77,T78,T82	OUTPUT
tl_spi_host1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_size[1:0]	Yes	Yes	T77,T78,T82	Yes	T77,T78,T82	OUTPUT
tl_spi_host1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_opcode[2:0]	Yes	Yes	T77,T78,T82	Yes	T77,T78,T82	OUTPUT
tl_spi_host1_o.a_valid	Yes	Yes	T28,T154,T44	Yes	T28,T154,T44	OUTPUT
tl_spi_host1_i.a_ready	Yes	Yes	T28,T154,T44	Yes	T28,T154,T44	INPUT
tl_spi_host1_i.d_error	Yes	Yes	T77,T78,T82	Yes	T77,T78,T82	INPUT
tl_spi_host1_i.d_user.data_intg[6:0]	Yes	Yes	T28,T154,T352	Yes	T28,T154,T352	INPUT
tl_spi_host1_i.d_user.rsp_intg[6:0]	Yes	Yes	T28,T154,T352	Yes	T28,T154,T44	INPUT
tl_spi_host1_i.d_data[31:0]	Yes	Yes	T28,T154,T352	Yes	T28,T154,T352	INPUT
tl_spi_host1_i.d_sink	Yes	Yes	T77,T78,T82	Yes	T77,T78,T82	INPUT
tl_spi_host1_i.d_source[5:0]	Yes	Yes	*T77,*T78,*T82	Yes	T77,T78,T82	INPUT
tl_spi_host1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_size[1:0]	Yes	Yes	T77,T78,T82	Yes	T77,T78,T82	INPUT
tl_spi_host1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_opcode[0]	Yes	Yes	*T28,*T154,*T352	Yes	T28,T154,T352	INPUT
tl_spi_host1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_valid	Yes	Yes	T28,T154,T44	Yes	T28,T154,T44	INPUT
tl_usbdev_o.d_ready	Yes	Yes	T95,T17,T18	Yes	T95,T17,T18	OUTPUT
tl_usbdev_o.a_user.data_intg[6:0]	Yes	Yes	T95,T17,T18	Yes	T95,T17,T18	OUTPUT
tl_usbdev_o.a_user.cmd_intg[6:0]	Yes	Yes	T95,T17,T18	Yes	T95,T17,T18	OUTPUT
tl_usbdev_o.a_user.instr_type[3:0]	Yes	Yes	T95,T17,T18	Yes	T95,T17,T18	OUTPUT
tl_usbdev_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_data[31:0]	Yes	Yes	T95,T17,T18	Yes	T95,T17,T18	OUTPUT
tl_usbdev_o.a_mask[3:0]	Yes	Yes	T95,T17,T18	Yes	T95,T17,T18	OUTPUT
tl_usbdev_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_source[5:0]	Yes	Yes	*T68,*T77,*T78	Yes	T68,T77,T78	OUTPUT
tl_usbdev_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_size[1:0]	Yes	Yes	T77,T78,T82	Yes	T77,T78,T82	OUTPUT
tl_usbdev_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_opcode[2:0]	Yes	Yes	T77,T78,T82	Yes	T77,T78,T82	OUTPUT
tl_usbdev_o.a_valid	Yes	Yes	T95,T17,T18	Yes	T95,T17,T18	OUTPUT
tl_usbdev_i.a_ready	Yes	Yes	T95,T17,T18	Yes	T95,T17,T18	INPUT
tl_usbdev_i.d_error	Yes	Yes	T78,T82,T153	Yes	T78,T82,T153	INPUT
tl_usbdev_i.d_user.data_intg[6:0]	Yes	Yes	T95,T17,T68	Yes	T95,T17,T68	INPUT
tl_usbdev_i.d_user.rsp_intg[6:0]	Yes	Yes	T95,T17,T68	Yes	T95,T17,T68	INPUT
tl_usbdev_i.d_data[31:0]	Yes	Yes	T95,T17,T18	Yes	T95,T17,T18	INPUT
tl_usbdev_i.d_sink	Yes	Yes	T78,T82,T153	Yes	T77,T78,T82	INPUT
tl_usbdev_i.d_source[5:0]	Yes	Yes	*T68,*T77,*T78	Yes	T68,T78,T82	INPUT
tl_usbdev_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_size[1:0]	Yes	Yes	T78,T82,T153	Yes	T78,T82,T153	INPUT
tl_usbdev_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_opcode[0]	Yes	Yes	*T95,*T17,*T18	Yes	T95,T17,T18	INPUT
tl_usbdev_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_valid	Yes	Yes	T95,T17,T18	Yes	T95,T17,T18	INPUT
tl_flash_ctrl__core_o.d_ready	Yes	Yes	T2,T3,T27	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.data_intg[6:0]	Yes	Yes	T2,T3,T27	Yes	T2,T3,T27	OUTPUT
tl_flash_ctrl__core_o.a_user.cmd_intg[6:0]	Yes	Yes	T2,T3,T27	Yes	T2,T3,T27	OUTPUT
tl_flash_ctrl__core_o.a_user.instr_type[3:0]	Yes	Yes	T2,T3,T27	Yes	T2,T3,T27	OUTPUT
tl_flash_ctrl__core_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_data[31:0]	Yes	Yes	T2,T3,T27	Yes	T2,T3,T27	OUTPUT
tl_flash_ctrl__core_o.a_mask[3:0]	Yes	Yes	T2,T3,T27	Yes	T2,T3,T27	OUTPUT
tl_flash_ctrl__core_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_source[5:0]	Yes	Yes	*T68,*T50,*T81	Yes	T68,T50,T81	OUTPUT
tl_flash_ctrl__core_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_size[1:0]	Yes	Yes	T77,T78,T82	Yes	T77,T78,T82	OUTPUT
tl_flash_ctrl__core_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_opcode[2:0]	Yes	Yes	T78,T82,T153	Yes	T78,T82,T153	OUTPUT
tl_flash_ctrl__core_o.a_valid	Yes	Yes	T2,T3,T27	Yes	T2,T3,T27	OUTPUT
tl_flash_ctrl__core_i.a_ready	Yes	Yes	T2,T3,T27	Yes	T2,T3,T27	INPUT
tl_flash_ctrl__core_i.d_error	Yes	Yes	T1,T2,T3	Yes	T2,T4,T6	INPUT
tl_flash_ctrl__core_i.d_user.data_intg[6:0]	Yes	Yes	T2,T3,T27	Yes	T2,T3,T27	INPUT
tl_flash_ctrl__core_i.d_user.rsp_intg[6:0]	Yes	Yes	T2,T3,T27	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_data[31:0]	Yes	Yes	T2,T3,T27	Yes	T2,T4,T39	INPUT
tl_flash_ctrl__core_i.d_sink	Yes	Yes	T77,T78,T82	Yes	T78,T82,T153	INPUT
tl_flash_ctrl__core_i.d_source[5:0]	Yes	Yes	*T68,*T50,*T81	Yes	T68,T50,T81	INPUT
tl_flash_ctrl__core_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_size[1:0]	Yes	Yes	T77,T78,T82	Yes	T77,T78,T82	INPUT
tl_flash_ctrl__core_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_opcode[0]	Yes	Yes	*T2,*T3,*T27	Yes	T2,T3,T27	INPUT
tl_flash_ctrl__core_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_valid	Yes	Yes	T2,T3,T27	Yes	T2,T3,T27	INPUT
tl_flash_ctrl__prim_o.d_ready	Yes	Yes	T2,T4,T6	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__prim_o.a_user.data_intg[6:0]	Yes	Yes	T68,T50,T81	Yes	T68,T50,T81	OUTPUT
tl_flash_ctrl__prim_o.a_user.cmd_intg[6:0]	Yes	Yes	T68,T50,T81	Yes	T68,T50,T81	OUTPUT
tl_flash_ctrl__prim_o.a_user.instr_type[3:0]	Yes	Yes	T68,T50,T81	Yes	T68,T50,T81	OUTPUT
tl_flash_ctrl__prim_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_data[31:0]	Yes	Yes	T68,T50,T81	Yes	T68,T50,T81	OUTPUT
tl_flash_ctrl__prim_o.a_mask[3:0]	Yes	Yes	T68,T50,T81	Yes	T68,T50,T81	OUTPUT
tl_flash_ctrl__prim_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_source[5:0]	Yes	Yes	*T68,*T50,*T81	Yes	T68,T50,T81	OUTPUT
tl_flash_ctrl__prim_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_size[1:0]	Yes	Yes	T77,T78,T82	Yes	T77,T78,T82	OUTPUT
tl_flash_ctrl__prim_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_opcode[2:0]	Yes	Yes	T77,T78,T82	Yes	T77,T78,T82	OUTPUT
tl_flash_ctrl__prim_o.a_valid	Yes	Yes	T68,T50,T81	Yes	T68,T50,T81	OUTPUT
tl_flash_ctrl__prim_i.a_ready	Yes	Yes	T68,T50,T81	Yes	T68,T50,T81	INPUT
tl_flash_ctrl__prim_i.d_error	Yes	Yes	T78,T79,T82	Yes	T78,T82,T153	INPUT
tl_flash_ctrl__prim_i.d_user.data_intg[6:0]	Yes	Yes	T68,T50,T81	Yes	T68,T50,T81	INPUT
tl_flash_ctrl__prim_i.d_user.rsp_intg[6:0]	Yes	Yes	T68,T50,T81	Yes	T68,T50,T81	INPUT
tl_flash_ctrl__prim_i.d_data[31:0]	Yes	Yes	T68,T50,T81	Yes	T68,T50,T81	INPUT
tl_flash_ctrl__prim_i.d_sink	Yes	Yes	T77,T78,T82	Yes	T77,T78,T82	INPUT
tl_flash_ctrl__prim_i.d_source[5:0]	Yes	Yes	*T68,*T50,*T81	Yes	T68,T50,T81	INPUT
tl_flash_ctrl__prim_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_size[1:0]	Yes	Yes	T77,T78,T82	Yes	T77,T78,T82	INPUT
tl_flash_ctrl__prim_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_opcode[0]	Yes	Yes	*T68,*T50,*T81	Yes	T68,T50,T81	INPUT
tl_flash_ctrl__prim_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_valid	Yes	Yes	T68,T50,T81	Yes	T68,T50,T81	INPUT
tl_flash_ctrl__mem_o.d_ready	Yes	Yes	T2,T3,T27	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_user.data_intg[6:0]	Yes	Yes	T2,T3,T27	Yes	T2,T3,T27	OUTPUT
tl_flash_ctrl__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T2,T3,T27	Yes	T2,T3,T27	OUTPUT
tl_flash_ctrl__mem_o.a_user.instr_type[3:0]	Yes	Yes	T2,T3,T27	Yes	T2,T3,T27	OUTPUT
tl_flash_ctrl__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_data[31:0]	Yes	Yes	T2,T3,T27	Yes	T2,T3,T27	OUTPUT
tl_flash_ctrl__mem_o.a_mask[3:0]	Yes	Yes	T2,T3,T27	Yes	T2,T3,T27	OUTPUT
tl_flash_ctrl__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_source[5:0]	Yes	Yes	*T2,*T3,*T27	Yes	T2,T3,T27	OUTPUT
tl_flash_ctrl__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_flash_ctrl__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_opcode[2:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_flash_ctrl__mem_o.a_valid	Yes	Yes	T2,T3,T27	Yes	T2,T3,T27	OUTPUT
tl_flash_ctrl__mem_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T2,T3,T27	INPUT
tl_flash_ctrl__mem_i.d_error	Yes	Yes	T1,T2,T3	Yes	T2,T4,T6	INPUT
tl_flash_ctrl__mem_i.d_user.data_intg[6:0]	Yes	Yes	T2,T3,T27	Yes	T2,T3,T27	INPUT
tl_flash_ctrl__mem_i.d_user.rsp_intg[6:0]	Yes	Yes	T2,T3,T27	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_data[31:0]	Yes	Yes	T2,T3,T27	Yes	T2,T3,T27	INPUT
tl_flash_ctrl__mem_i.d_sink	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_flash_ctrl__mem_i.d_source[5:0]	Yes	Yes	*T2,*T3,*T27	Yes	T2,T3,T27	INPUT
tl_flash_ctrl__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_flash_ctrl__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_opcode[0]	Yes	Yes	*T77,*T78,*T79	Yes	T77,T78,T79	INPUT
tl_flash_ctrl__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_valid	Yes	Yes	T2,T3,T27	Yes	T2,T3,T27	INPUT
tl_hmac_o.d_ready	Yes	Yes	T2,T4,T39	Yes	T1,T2,T3	OUTPUT
tl_hmac_o.a_user.data_intg[6:0]	Yes	Yes	T39,T40,T120	Yes	T39,T40,T120	OUTPUT
tl_hmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T39,T40,T120	Yes	T39,T40,T120	OUTPUT
tl_hmac_o.a_user.instr_type[3:0]	Yes	Yes	T39,T40,T120	Yes	T39,T40,T120	OUTPUT
tl_hmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_data[31:0]	Yes	Yes	T39,T40,T120	Yes	T39,T40,T120	OUTPUT
tl_hmac_o.a_mask[3:0]	Yes	Yes	T39,T40,T120	Yes	T39,T40,T120	OUTPUT
tl_hmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_source[5:0]	Yes	Yes	*T68,*T50,*T81	Yes	T68,T50,T81	OUTPUT
tl_hmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_size[1:0]	Yes	Yes	T78,T79,T82	Yes	T78,T79,T82	OUTPUT
tl_hmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_opcode[2:0]	Yes	Yes	T120,T320,T652	Yes	T120,T320,T652	OUTPUT
tl_hmac_o.a_valid	Yes	Yes	T39,T40,T120	Yes	T39,T40,T120	OUTPUT
tl_hmac_i.a_ready	Yes	Yes	T39,T40,T120	Yes	T39,T40,T120	INPUT
tl_hmac_i.d_error	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_hmac_i.d_user.data_intg[6:0]	Yes	Yes	T39,T40,T120	Yes	T39,T40,T120	INPUT
tl_hmac_i.d_user.rsp_intg[6:0]	Yes	Yes	T39,T40,T120	Yes	T39,T40,T120	INPUT
tl_hmac_i.d_data[31:0]	Yes	Yes	T39,T40,T120	Yes	T39,T40,T120	INPUT
tl_hmac_i.d_sink	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_hmac_i.d_source[5:0]	Yes	Yes	*T68,*T50,*T81	Yes	T68,T50,T81	INPUT
tl_hmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_size[1:0]	Yes	Yes	T78,T79,T82	Yes	T78,T79,T82	INPUT
tl_hmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_opcode[0]	Yes	Yes	*T39,*T40,*T120	Yes	T39,T40,T120	INPUT
tl_hmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_valid	Yes	Yes	T39,T40,T120	Yes	T39,T40,T120	INPUT
tl_kmac_o.d_ready	Yes	Yes	T2,T4,T6	Yes	T1,T2,T3	OUTPUT
tl_kmac_o.a_user.data_intg[6:0]	Yes	Yes	T2,T344,T259	Yes	T2,T344,T259	OUTPUT
tl_kmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T2,T88,T344	Yes	T2,T88,T344	OUTPUT
tl_kmac_o.a_user.instr_type[3:0]	Yes	Yes	T2,T88,T344	Yes	T2,T88,T344	OUTPUT
tl_kmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_data[31:0]	Yes	Yes	T2,T344,T259	Yes	T2,T344,T259	OUTPUT
tl_kmac_o.a_mask[3:0]	Yes	Yes	T2,T88,T344	Yes	T2,T88,T344	OUTPUT
tl_kmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_source[5:0]	Yes	Yes	*T68,*T50,*T81	Yes	T68,T50,T81	OUTPUT
tl_kmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_size[1:0]	Yes	Yes	T77,T78,T82	Yes	T77,T78,T82	OUTPUT
tl_kmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_opcode[2:0]	Yes	Yes	T344,T259,T98	Yes	T344,T259,T98	OUTPUT
tl_kmac_o.a_valid	Yes	Yes	T2,T88,T344	Yes	T2,T88,T344	OUTPUT
tl_kmac_i.a_ready	Yes	Yes	T2,T88,T344	Yes	T2,T88,T344	INPUT
tl_kmac_i.d_error	Yes	Yes	T77,T78,T82	Yes	T77,T78,T82	INPUT
tl_kmac_i.d_user.data_intg[6:0]	Yes	Yes	T2,T88,T344	Yes	T2,T88,T344	INPUT
tl_kmac_i.d_user.rsp_intg[6:0]	Yes	Yes	T2,T88,T344	Yes	T2,T88,T344	INPUT
tl_kmac_i.d_data[31:0]	Yes	Yes	T2,T88,T344	Yes	T2,T344,T259	INPUT
tl_kmac_i.d_sink	Yes	Yes	T77,T78,T82	Yes	T77,T78,T82	INPUT
tl_kmac_i.d_source[5:0]	Yes	Yes	*T68,*T50,*T81	Yes	T68,T50,T81	INPUT
tl_kmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_size[1:0]	Yes	Yes	T77,T78,T82	Yes	T77,T78,T82	INPUT
tl_kmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_opcode[0]	Yes	Yes	*T2,*T88,*T344	Yes	T2,T344,T259	INPUT
tl_kmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_valid	Yes	Yes	T2,T88,T344	Yes	T2,T88,T344	INPUT
tl_aes_o.d_ready	Yes	Yes	T2,T27,T4	Yes	T1,T2,T3	OUTPUT
tl_aes_o.a_user.data_intg[6:0]	Yes	Yes	T172,T121,T648	Yes	T172,T121,T648	OUTPUT
tl_aes_o.a_user.cmd_intg[6:0]	Yes	Yes	T172,T121,T648	Yes	T172,T121,T648	OUTPUT
tl_aes_o.a_user.instr_type[3:0]	Yes	Yes	T27,T172,T121	Yes	T27,T172,T121	OUTPUT
tl_aes_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_data[31:0]	Yes	Yes	T172,T121,T648	Yes	T172,T121,T648	OUTPUT
tl_aes_o.a_mask[3:0]	Yes	Yes	T27,T172,T121	Yes	T27,T172,T121	OUTPUT
tl_aes_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_source[5:0]	Yes	Yes	*T77,*T78,*T82	Yes	T77,T78,T82	OUTPUT
tl_aes_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_size[1:0]	Yes	Yes	T77,T78,T82	Yes	T77,T78,T82	OUTPUT
tl_aes_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_opcode[2:0]	Yes	Yes	T77,T78,T82	Yes	T77,T78,T82	OUTPUT
tl_aes_o.a_valid	Yes	Yes	T27,T172,T121	Yes	T27,T172,T121	OUTPUT
tl_aes_i.a_ready	Yes	Yes	T27,T172,T121	Yes	T27,T172,T121	INPUT
tl_aes_i.d_error	Yes	Yes	T77,T78,T82	Yes	T77,T78,T82	INPUT
tl_aes_i.d_user.data_intg[6:0]	Yes	Yes	T27,T172,T121	Yes	T27,T172,T121	INPUT
tl_aes_i.d_user.rsp_intg[6:0]	Yes	Yes	T27,T172,T121	Yes	T27,T172,T121	INPUT
tl_aes_i.d_data[31:0]	Yes	Yes	T27,T172,T121	Yes	T27,T172,T121	INPUT
tl_aes_i.d_sink	Yes	Yes	T77,T78,T82	Yes	T77,T78,T82	INPUT
tl_aes_i.d_source[5:0]	Yes	Yes	*T77,*T78,*T82	Yes	T78,T82,T153	INPUT
tl_aes_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_size[1:0]	Yes	Yes	T77,T78,T82	Yes	T77,T78,T82	INPUT
tl_aes_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_opcode[0]	Yes	Yes	*T27,*T172,*T121	Yes	T27,T172,T121	INPUT
tl_aes_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_valid	Yes	Yes	T27,T172,T121	Yes	T27,T172,T121	INPUT
tl_entropy_src_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_source[5:0]	Yes	Yes	*T68,*T50,*T81	Yes	T68,T50,T81	OUTPUT
tl_entropy_src_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_size[1:0]	Yes	Yes	T77,T78,T82	Yes	T77,T78,T82	OUTPUT
tl_entropy_src_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_opcode[2:0]	Yes	Yes	T77,T78,T82	Yes	T77,T78,T82	OUTPUT
tl_entropy_src_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_error	Yes	Yes	T77,T78,T82	Yes	T77,T78,T82	INPUT
tl_entropy_src_i.d_user.data_intg[6:0]	Yes	Yes	T2,T27,T87	Yes	T2,T27,T87	INPUT
tl_entropy_src_i.d_user.rsp_intg[6:0]	Yes	Yes	T2,T27,T4	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_data[31:0]	Yes	Yes	T2,T27,T4	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_sink	Yes	Yes	T77,T78,T82	Yes	T77,T78,T82	INPUT
tl_entropy_src_i.d_source[5:0]	Yes	Yes	*T68,*T50,*T81	Yes	T68,T50,T81	INPUT
tl_entropy_src_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_size[1:0]	Yes	Yes	T77,T78,T82	Yes	T77,T78,T82	INPUT
tl_entropy_src_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_opcode[0]	Yes	Yes	*T2,*T27,*T87	Yes	T2,T27,T39	INPUT
tl_entropy_src_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_csrng_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_data[31:0]	Yes	Yes	T2,T27,T87	Yes	T2,T27,T87	OUTPUT
tl_csrng_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_source[5:0]	Yes	Yes	*T68,*T50,*T81	Yes	T68,T50,T81	OUTPUT
tl_csrng_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_size[1:0]	Yes	Yes	T78,T82,T153	Yes	T78,T82,T153	OUTPUT
tl_csrng_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_opcode[2:0]	Yes	Yes	T78,T82,T153	Yes	T78,T82,T153	OUTPUT
tl_csrng_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_error	Yes	Yes	T78,T82,T153	Yes	T78,T82,T153	INPUT
tl_csrng_i.d_user.data_intg[6:0]	Yes	Yes	T2,T27,T87	Yes	T2,T27,T87	INPUT
tl_csrng_i.d_user.rsp_intg[6:0]	Yes	Yes	T2,T27,T4	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_data[31:0]	Yes	Yes	T2,T27,T4	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_sink	Yes	Yes	T78,T82,T153	Yes	T78,T82,T153	INPUT
tl_csrng_i.d_source[5:0]	Yes	Yes	*T68,*T50,*T81	Yes	T68,T50,T81	INPUT
tl_csrng_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_size[1:0]	Yes	Yes	T78,T82,T153	Yes	T78,T82,T153	INPUT
tl_csrng_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_opcode[0]	Yes	Yes	*T2,*T27,*T87	Yes	T2,T27,T87	INPUT
tl_csrng_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn0_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.data_intg[6:0]	Yes	Yes	T2,T27,T87	Yes	T2,T27,T87	OUTPUT
tl_edn0_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_data[31:0]	Yes	Yes	T2,T27,T87	Yes	T2,T27,T87	OUTPUT
tl_edn0_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_source[5:0]	Yes	Yes	*T68,*T50,*T81	Yes	T68,T50,T81	OUTPUT
tl_edn0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_size[1:0]	Yes	Yes	T77,T78,T82	Yes	T77,T78,T82	OUTPUT
tl_edn0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_opcode[2:0]	Yes	Yes	T77,T78,T82	Yes	T77,T78,T82	OUTPUT
tl_edn0_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_error	Yes	Yes	T78,T82,T153	Yes	T77,T78,T82	INPUT
tl_edn0_i.d_user.data_intg[6:0]	Yes	Yes	T2,T27,T87	Yes	T2,T27,T87	INPUT
tl_edn0_i.d_user.rsp_intg[6:0]	Yes	Yes	T2,T27,T4	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_data[31:0]	Yes	Yes	T2,T27,T4	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_sink	Yes	Yes	T77,T78,T82	Yes	T77,T78,T82	INPUT
tl_edn0_i.d_source[5:0]	Yes	Yes	*T68,*T50,*T81	Yes	T68,T50,T81	INPUT
tl_edn0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_size[1:0]	Yes	Yes	T77,T78,T82	Yes	T77,T78,T82	INPUT
tl_edn0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_opcode[0]	Yes	Yes	*T2,*T27,*T87	Yes	T2,T27,T87	INPUT
tl_edn0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn1_o.d_ready	Yes	Yes	T2,T27,T4	Yes	T1,T2,T3	OUTPUT
tl_edn1_o.a_user.data_intg[6:0]	Yes	Yes	T2,T27,T87	Yes	T2,T27,T87	OUTPUT
tl_edn1_o.a_user.cmd_intg[6:0]	Yes	Yes	T2,T27,T87	Yes	T2,T27,T87	OUTPUT
tl_edn1_o.a_user.instr_type[3:0]	Yes	Yes	T2,T27,T87	Yes	T2,T27,T87	OUTPUT
tl_edn1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_data[31:0]	Yes	Yes	T2,T27,T87	Yes	T2,T27,T87	OUTPUT
tl_edn1_o.a_mask[3:0]	Yes	Yes	T2,T27,T87	Yes	T2,T27,T87	OUTPUT
tl_edn1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_source[5:0]	Yes	Yes	*T68,*T50,*T81	Yes	T68,T50,T81	OUTPUT
tl_edn1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_size[1:0]	Yes	Yes	T77,T78,T82	Yes	T77,T78,T82	OUTPUT
tl_edn1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_opcode[2:0]	Yes	Yes	T77,T78,T82	Yes	T77,T78,T82	OUTPUT
tl_edn1_o.a_valid	Yes	Yes	T2,T27,T87	Yes	T2,T27,T87	OUTPUT
tl_edn1_i.a_ready	Yes	Yes	T2,T27,T87	Yes	T2,T27,T87	INPUT
tl_edn1_i.d_error	Yes	Yes	T78,T82,T217	Yes	T78,T82,T217	INPUT
tl_edn1_i.d_user.data_intg[6:0]	Yes	Yes	T2,T27,T87	Yes	T2,T27,T87	INPUT
tl_edn1_i.d_user.rsp_intg[6:0]	Yes	Yes	T2,T27,T87	Yes	T2,T27,T87	INPUT
tl_edn1_i.d_data[31:0]	Yes	Yes	T2,T27,T87	Yes	T2,T27,T87	INPUT
tl_edn1_i.d_sink	Yes	Yes	T77,T78,T82	Yes	T77,T78,T82	INPUT
tl_edn1_i.d_source[5:0]	Yes	Yes	*T68,*T50,*T81	Yes	T68,T50,T81	INPUT
tl_edn1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_size[1:0]	Yes	Yes	T77,T78,T82	Yes	T77,T78,T82	INPUT
tl_edn1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_opcode[0]	Yes	Yes	*T2,*T27,*T87	Yes	T2,T27,T87	INPUT
tl_edn1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_valid	Yes	Yes	T2,T27,T87	Yes	T2,T27,T87	INPUT
tl_rv_plic_o.d_ready	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	OUTPUT
tl_rv_plic_o.a_user.data_intg[6:0]	Yes	Yes	T3,T4,T87	Yes	T3,T4,T87	OUTPUT
tl_rv_plic_o.a_user.cmd_intg[6:0]	Yes	Yes	T3,T4,T87	Yes	T3,T4,T87	OUTPUT
tl_rv_plic_o.a_user.instr_type[3:0]	Yes	Yes	T3,T4,T87	Yes	T3,T4,T87	OUTPUT
tl_rv_plic_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_data[31:0]	Yes	Yes	T3,T4,T87	Yes	T3,T4,T87	OUTPUT
tl_rv_plic_o.a_mask[3:0]	Yes	Yes	T3,T4,T87	Yes	T3,T4,T87	OUTPUT
tl_rv_plic_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_source[5:0]	Yes	Yes	*T77,*T78,*T82	Yes	T77,T78,T82	OUTPUT
tl_rv_plic_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_size[1:0]	Yes	Yes	T77,T78,T82	Yes	T77,T78,T82	OUTPUT
tl_rv_plic_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_opcode[2:0]	Yes	Yes	T77,T78,T82	Yes	T77,T78,T82	OUTPUT
tl_rv_plic_o.a_valid	Yes	Yes	T3,T4,T87	Yes	T3,T4,T87	OUTPUT
tl_rv_plic_i.a_ready	Yes	Yes	T3,T4,T87	Yes	T3,T4,T87	INPUT
tl_rv_plic_i.d_error	Yes	Yes	T77,T78,T82	Yes	T77,T78,T82	INPUT
tl_rv_plic_i.d_user.data_intg[6:0]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	INPUT
tl_rv_plic_i.d_user.rsp_intg[6:0]	Yes	Yes	T3,T4,T87	Yes	T3,T4,T87	INPUT
tl_rv_plic_i.d_data[31:0]	Yes	Yes	T3,T4,T87	Yes	T3,T4,T87	INPUT
tl_rv_plic_i.d_sink	Yes	Yes	T77,T78,T82	Yes	T77,T78,T82	INPUT
tl_rv_plic_i.d_source[5:0]	Yes	Yes	*T77,*T78,*T82	Yes	T77,T78,T82	INPUT
tl_rv_plic_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_size[1:0]	Yes	Yes	T77,T78,T82	Yes	T77,T78,T82	INPUT
tl_rv_plic_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_opcode[0]	Yes	Yes	*T3,*T4,*T87	Yes	T3,T4,T87	INPUT
tl_rv_plic_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_valid	Yes	Yes	T3,T4,T87	Yes	T3,T4,T87	INPUT
tl_otbn_o.d_ready	Yes	Yes	T2,T27,T4	Yes	T1,T2,T3	OUTPUT
tl_otbn_o.a_user.data_intg[6:0]	Yes	Yes	T27,T39,T87	Yes	T27,T39,T87	OUTPUT
tl_otbn_o.a_user.cmd_intg[6:0]	Yes	Yes	T27,T39,T87	Yes	T27,T39,T87	OUTPUT
tl_otbn_o.a_user.instr_type[3:0]	Yes	Yes	T27,T39,T87	Yes	T27,T39,T87	OUTPUT
tl_otbn_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_data[31:0]	Yes	Yes	T27,T39,T87	Yes	T27,T39,T87	OUTPUT
tl_otbn_o.a_mask[3:0]	Yes	Yes	T27,T39,T87	Yes	T27,T39,T87	OUTPUT
tl_otbn_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_source[5:0]	Yes	Yes	*T203,*T204,*T205	Yes	T203,T204,T205	OUTPUT
tl_otbn_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_size[1:0]	Yes	Yes	T77,T78,T82	Yes	T77,T78,T82	OUTPUT
tl_otbn_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_opcode[2:0]	Yes	Yes	T77,T78,T82	Yes	T77,T78,T82	OUTPUT
tl_otbn_o.a_valid	Yes	Yes	T27,T39,T87	Yes	T27,T39,T87	OUTPUT
tl_otbn_i.a_ready	Yes	Yes	T27,T39,T87	Yes	T27,T39,T87	INPUT
tl_otbn_i.d_error	Yes	Yes	T77,T78,T82	Yes	T77,T78,T82	INPUT
tl_otbn_i.d_user.data_intg[6:0]	Yes	Yes	T27,T39,T87	Yes	T27,T39,T87	INPUT
tl_otbn_i.d_user.rsp_intg[6:0]	Yes	Yes	T27,T39,T87	Yes	T27,T39,T87	INPUT
tl_otbn_i.d_data[31:0]	Yes	Yes	T27,T39,T87	Yes	T27,T39,T87	INPUT
tl_otbn_i.d_sink	Yes	Yes	T77,T78,T82	Yes	T77,T78,T82	INPUT
tl_otbn_i.d_source[5:0]	Yes	Yes	*T203,*T204,*T205	Yes	T203,T204,T205	INPUT
tl_otbn_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_size[1:0]	Yes	Yes	T77,T78,T82	Yes	T77,T78,T82	INPUT
tl_otbn_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_opcode[0]	Yes	Yes	*T27,*T39,*T87	Yes	T27,T39,T87	INPUT
tl_otbn_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_valid	Yes	Yes	T27,T39,T87	Yes	T27,T39,T87	INPUT
tl_keymgr_o.d_ready	Yes	Yes	T2,T4,T39	Yes	T1,T2,T3	OUTPUT
tl_keymgr_o.a_user.data_intg[6:0]	Yes	Yes	T39,T88,T40	Yes	T39,T88,T40	OUTPUT
tl_keymgr_o.a_user.cmd_intg[6:0]	Yes	Yes	T39,T88,T40	Yes	T39,T88,T40	OUTPUT
tl_keymgr_o.a_user.instr_type[3:0]	Yes	Yes	T39,T88,T40	Yes	T39,T88,T40	OUTPUT
tl_keymgr_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_data[31:0]	Yes	Yes	T40,T171,T172	Yes	T40,T171,T172	OUTPUT
tl_keymgr_o.a_mask[3:0]	Yes	Yes	T39,T88,T40	Yes	T39,T88,T40	OUTPUT
tl_keymgr_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_source[5:0]	Yes	Yes	*T68,*T50,*T81	Yes	T68,T50,T81	OUTPUT
tl_keymgr_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_size[1:0]	Yes	Yes	T77,T78,T82	Yes	T77,T78,T82	OUTPUT
tl_keymgr_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_opcode[2:0]	Yes	Yes	T77,T78,T82	Yes	T77,T78,T82	OUTPUT
tl_keymgr_o.a_valid	Yes	Yes	T39,T88,T40	Yes	T39,T88,T40	OUTPUT
tl_keymgr_i.a_ready	Yes	Yes	T39,T88,T40	Yes	T39,T88,T40	INPUT
tl_keymgr_i.d_error	Yes	Yes	T78,T82,T217	Yes	T77,T78,T82	INPUT
tl_keymgr_i.d_user.data_intg[6:0]	Yes	Yes	T171,T172,T154	Yes	T171,T172,T154	INPUT
tl_keymgr_i.d_user.rsp_intg[6:0]	Yes	Yes	T39,T40,T66	Yes	T39,T40,T66	INPUT
tl_keymgr_i.d_data[31:0]	Yes	Yes	T39,T40,T66	Yes	T39,T40,T66	INPUT
tl_keymgr_i.d_sink	Yes	Yes	T77,T78,T82	Yes	T78,T82,T153	INPUT
tl_keymgr_i.d_source[5:0]	Yes	Yes	*T68,*T50,*T81	Yes	T68,T50,T81	INPUT
tl_keymgr_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_size[1:0]	Yes	Yes	T77,T78,T82	Yes	T77,T78,T82	INPUT
tl_keymgr_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_opcode[0]	Yes	Yes	*T39,*T40,*T171	Yes	T39,T88,T40	INPUT
tl_keymgr_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_valid	Yes	Yes	T39,T88,T40	Yes	T39,T88,T40	INPUT
tl_rv_core_ibex__cfg_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.data_intg[6:0]	Yes	Yes	T2,T3,T27	Yes	T2,T3,T27	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.cmd_intg[6:0]	Yes	Yes	T2,T3,T27	Yes	T2,T3,T27	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_source[5:0]	Yes	Yes	*T65,*T50,*T77	Yes	T65,T50,T77	OUTPUT
tl_rv_core_ibex__cfg_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_size[1:0]	Yes	Yes	T77,T78,T82	Yes	T77,T78,T82	OUTPUT
tl_rv_core_ibex__cfg_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_opcode[2:0]	Yes	Yes	T77,T78,T82	Yes	T77,T78,T82	OUTPUT
tl_rv_core_ibex__cfg_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cfg_i.d_error	Yes	Yes	T50,T77,T78	Yes	T50,T77,T78	INPUT
tl_rv_core_ibex__cfg_i.d_user.data_intg[6:0]	Yes	Yes	T2,T3,T27	Yes	T2,T3,T27	INPUT
tl_rv_core_ibex__cfg_i.d_user.rsp_intg[6:0]	Yes	Yes	T2,T3,T27	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cfg_i.d_data[31:0]	Yes	Yes	T2,T3,T27	Yes	T2,T3,T27	INPUT
tl_rv_core_ibex__cfg_i.d_sink	Yes	Yes	T77,T78,T82	Yes	T77,T78,T82	INPUT
tl_rv_core_ibex__cfg_i.d_source[5:0]	Yes	Yes	*T50,*T77,*T78	Yes	T65,T50,T77	INPUT
tl_rv_core_ibex__cfg_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_size[1:0]	Yes	Yes	T77,T78,T82	Yes	T77,T78,T82	INPUT
tl_rv_core_ibex__cfg_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_opcode[0]	Yes	Yes	*T2,*T3,*T27	Yes	T2,T3,T27	INPUT
tl_rv_core_ibex__cfg_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__regs_o.d_ready	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.data_intg[6:0]	Yes	Yes	T1,T39,T40	Yes	T1,T39,T40	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T39,T40	Yes	T1,T39,T40	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.instr_type[3:0]	Yes	Yes	T1,T39,T40	Yes	T1,T39,T40	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_data[31:0]	Yes	Yes	T1,T39,T40	Yes	T1,T39,T40	OUTPUT
tl_sram_ctrl_main__regs_o.a_mask[3:0]	Yes	Yes	T1,T39,T40	Yes	T1,T39,T40	OUTPUT
tl_sram_ctrl_main__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_source[5:0]	Yes	Yes	*T410,*T411,*T77	Yes	T410,T411,T77	OUTPUT
tl_sram_ctrl_main__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_size[1:0]	Yes	Yes	T77,T78,T82	Yes	T77,T78,T82	OUTPUT
tl_sram_ctrl_main__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_opcode[2:0]	Yes	Yes	T77,T78,T82	Yes	T77,T78,T82	OUTPUT
tl_sram_ctrl_main__regs_o.a_valid	Yes	Yes	T1,T39,T40	Yes	T1,T39,T40	OUTPUT
tl_sram_ctrl_main__regs_i.a_ready	Yes	Yes	T1,T39,T40	Yes	T1,T39,T40	INPUT
tl_sram_ctrl_main__regs_i.d_error	Yes	Yes	T78,T82,T153	Yes	T78,T82,T153	INPUT
tl_sram_ctrl_main__regs_i.d_user.data_intg[6:0]	Yes	Yes	T282,T283,T284	Yes	T282,T283,T284	INPUT
tl_sram_ctrl_main__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T36,T37,T38	Yes	T1,T39,T40	INPUT
tl_sram_ctrl_main__regs_i.d_data[31:0]	Yes	Yes	T36,T37,T38	Yes	T1,T39,T40	INPUT
tl_sram_ctrl_main__regs_i.d_sink	Yes	Yes	T77,T78,T82	Yes	T77,T78,T82	INPUT
tl_sram_ctrl_main__regs_i.d_source[5:0]	Yes	Yes	*T77,*T78,*T82	Yes	T410,T411,T78	INPUT
tl_sram_ctrl_main__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_size[1:0]	Yes	Yes	T77,T78,T82	Yes	T78,T82,T153	INPUT
tl_sram_ctrl_main__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_opcode[0]	Yes	Yes	*T178,*T179,*T261	Yes	T105,T178,T179	INPUT
tl_sram_ctrl_main__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_valid	Yes	Yes	T1,T39,T40	Yes	T1,T39,T40	INPUT
tl_sram_ctrl_main__ram_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_sram_ctrl_main__ram_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_opcode[2:0]	Yes	Yes	T2,T3,T27	Yes	T2,T3,T27	OUTPUT
tl_sram_ctrl_main__ram_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_error	Yes	Yes	T1,T2,T3	Yes	T1,T2,T4	INPUT
tl_sram_ctrl_main__ram_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_sink	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_sram_ctrl_main__ram_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_sram_ctrl_main__ram_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range