Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : edn
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.34 99.34

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_edn1 99.02 99.02
tb.dut.top_earlgrey.u_edn0 99.25 99.25


Module Instance : tb.dut.top_earlgrey.u_edn1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.02 99.02


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.02 99.02


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.94 92.47 89.34 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_edn0

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.25 99.25


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.25 99.25


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.94 92.47 89.34 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Toggle Coverage for Module : edn
TotalCoveredPercent
Totals 78 75 96.15
Total Bits 1210 1202 99.34
Total Bits 0->1 605 602 99.50
Total Bits 1->0 605 600 99.17

Ports 78 75 96.15
Port Bits 1210 1202 99.34
Port Bits 0->1 605 602 99.50
Port Bits 1->0 605 600 99.17

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T4,T6 Yes T1,T2,T3 INPUT
tl_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T2,T27,T87 Yes T2,T27,T87 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T2,T27,T87 Yes T2,T27,T87 INPUT
tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_address[6:0] Yes Yes *T77,*T78,*T82 Yes T77,T78,T82 INPUT
tl_i.a_address[15:7] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[20:16] Yes Yes *T1,T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[23:21] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[24] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[29:25] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes *T68,*T50,*T81 Yes T68,T50,T81 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T77,T78,T82 Yes T77,T78,T82 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T77,T78,T82 Yes T77,T78,T82 INPUT
tl_i.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_o.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_error Yes Yes T78,T82,T153 Yes T77,T78,T82 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T2,T27,T87 Yes T2,T27,T87 OUTPUT
tl_o.d_user.rsp_intg[6:0] Yes Yes T2,T27,T4 Yes T1,T2,T3 OUTPUT
tl_o.d_data[31:0] Yes Yes T2,T27,T4 Yes T1,T2,T3 OUTPUT
tl_o.d_sink Yes Yes T77,T78,T82 Yes T77,T78,T82 OUTPUT
tl_o.d_source[5:0] Yes Yes *T68,*T50,*T81 Yes T68,T50,T81 OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[1:0] Yes Yes T77,T78,T82 Yes T77,T78,T82 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T2,*T27,*T87 Yes T2,T27,T87 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_i[0].edn_req Yes Yes T27,T87,T103 Yes T27,T87,T103 INPUT
edn_i[1].edn_req Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
edn_i[2].edn_req Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
edn_i[3].edn_req Yes Yes T419,T189,T198 Yes T419,T189,T198 INPUT
edn_i[4].edn_req Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
edn_i[5].edn_req Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
edn_i[6].edn_req Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
edn_i[7].edn_req Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
edn_o[0].edn_bus[31:0] Yes Yes T27,T87,T103 Yes T27,T87,T103 OUTPUT
edn_o[0].edn_fips Yes Yes T27,T421,T422 Yes T27,T87,T103 OUTPUT
edn_o[0].edn_ack Yes Yes T27,T87,T103 Yes T27,T87,T103 OUTPUT
edn_o[1].edn_bus[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[1].edn_fips No No Yes T87,T103,T118 OUTPUT
edn_o[1].edn_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[2].edn_bus[31:0] Yes Yes T2,T27,T4 Yes T1,T2,T3 OUTPUT
edn_o[2].edn_fips Yes Yes T115,T116,T117 Yes T118,T115,T119 OUTPUT
edn_o[2].edn_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[3].edn_bus[31:0] Yes Yes T419,T189,T198 Yes T419,T189,T198 OUTPUT
edn_o[3].edn_fips No No Yes T419,T189,T198 OUTPUT
edn_o[3].edn_ack Yes Yes T419,T189,T198 Yes T419,T189,T198 OUTPUT
edn_o[4].edn_bus[31:0] Yes Yes T2,T4,T6 Yes T2,T3,T4 OUTPUT
edn_o[4].edn_fips Yes Yes T117 Yes T118,T625,T626 OUTPUT
edn_o[4].edn_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[5].edn_bus[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[5].edn_fips Yes Yes T27,T421,T422 Yes T27,T172,T219 OUTPUT
edn_o[5].edn_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[6].edn_bus[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[6].edn_fips Yes Yes T27,T421,T422 Yes T27,T87,T103 OUTPUT
edn_o[6].edn_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[7].edn_bus[31:0] Yes Yes T27,T4,T39 Yes T1,T2,T27 OUTPUT
edn_o[7].edn_fips Yes Yes T27,T115,T116 Yes T27,T115,T116 OUTPUT
edn_o[7].edn_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
csrng_cmd_o.genbits_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
csrng_cmd_o.csrng_req_bus[31:0] Yes Yes T2,T27,T4 Yes T1,T2,T3 OUTPUT
csrng_cmd_o.csrng_req_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
csrng_cmd_i.genbits_bus[127:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
csrng_cmd_i.genbits_fips Yes Yes T115,T116,T621 Yes T27,T87,T103 INPUT
csrng_cmd_i.genbits_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
csrng_cmd_i.csrng_rsp_sts[2:0] No No No INPUT
csrng_cmd_i.csrng_rsp_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
csrng_cmd_i.csrng_req_ready Yes Yes T27,T399,T421 Yes T27,T399,T421 INPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T158,T84,T44 Yes T158,T84,T44 INPUT
alert_rx_i[0].ping_n Yes Yes T158,T84,T85 Yes T158,T84,T85 INPUT
alert_rx_i[0].ping_p Yes Yes T158,T84,T85 Yes T158,T84,T85 INPUT
alert_rx_i[1].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[1].ack_p Yes Yes T328,T84,T44 Yes T328,T84,T44 INPUT
alert_rx_i[1].ping_n Yes Yes T84,T157,T85 Yes T84,T157,T85 INPUT
alert_rx_i[1].ping_p Yes Yes T84,T157,T85 Yes T84,T157,T85 INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T158,T84,T44 Yes T158,T84,T44 OUTPUT
alert_tx_o[1].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[1].alert_p Yes Yes T328,T84,T44 Yes T328,T84,T44 OUTPUT
intr_edn_cmd_req_done_o Yes Yes T292,T299,T302 Yes T292,T299,T302 OUTPUT
intr_edn_fatal_err_o Yes Yes T292,T299,T296 Yes T292,T299,T296 OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.top_earlgrey.u_edn1
TotalCoveredPercent
Totals 50 48 96.00
Total Bits 714 707 99.02
Total Bits 0->1 357 354 99.16
Total Bits 1->0 357 353 98.88

Ports 50 48 96.00
Port Bits 714 707 99.02
Port Bits 0->1 357 354 99.16
Port Bits 1->0 357 353 98.88

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T4,T6 Yes T1,T2,T3 INPUT
tl_i.d_ready Yes Yes T2,T27,T4 Yes T1,T2,T3 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T2,T27,T87 Yes T2,T27,T87 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T2,T27,T87 Yes T2,T27,T87 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T2,T27,T87 Yes T2,T27,T87 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T2,T27,T87 Yes T2,T27,T87 INPUT
tl_i.a_mask[3:0] Yes Yes T2,T27,T87 Yes T2,T27,T87 INPUT
tl_i.a_address[6:0] Yes Yes *T77,*T78,*T82 Yes T77,T78,T82 INPUT
tl_i.a_address[18:7] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[20:19] Yes Yes T2,T27,T87 Yes T2,T27,T87 INPUT
tl_i.a_address[23:21] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[24] Yes Yes *T2,*T27,*T87 Yes T2,T27,T87 INPUT
tl_i.a_address[29:25] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T2,*T27,*T87 Yes T2,T27,T87 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes *T68,*T50,*T81 Yes T68,T50,T81 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T77,T78,T82 Yes T77,T78,T82 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T77,T78,T82 Yes T77,T78,T82 INPUT
tl_i.a_valid Yes Yes T2,T27,T87 Yes T2,T27,T87 INPUT
tl_o.a_ready Yes Yes T2,T27,T87 Yes T2,T27,T87 OUTPUT
tl_o.d_error Yes Yes T78,T82,T217 Yes T78,T82,T217 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T2,T27,T87 Yes T2,T27,T87 OUTPUT
tl_o.d_user.rsp_intg[6:0] Yes Yes T2,T27,T87 Yes T2,T27,T87 OUTPUT
tl_o.d_data[31:0] Yes Yes T2,T27,T87 Yes T2,T27,T87 OUTPUT
tl_o.d_sink Yes Yes T77,T78,T82 Yes T77,T78,T82 OUTPUT
tl_o.d_source[5:0] Yes Yes *T68,*T50,*T81 Yes T68,T50,T81 OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[1:0] Yes Yes T77,T78,T82 Yes T77,T78,T82 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T2,*T27,*T87 Yes T2,T27,T87 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T2,T27,T87 Yes T2,T27,T87 OUTPUT
edn_i[0].edn_req Yes Yes T27,T87,T103 Yes T27,T87,T103 INPUT
edn_i[1].edn_req[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off and unused.
edn_i[2].edn_req[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off and unused.
edn_i[3].edn_req[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off and unused.
edn_i[4].edn_req[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off and unused.
edn_i[5].edn_req[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off and unused.
edn_i[6].edn_req[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off and unused.
edn_i[7].edn_req[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off and unused.
edn_o[0].edn_bus[31:0] Yes Yes T27,T87,T103 Yes T27,T87,T103 OUTPUT
edn_o[0].edn_fips Yes Yes T27,T421,T422 Yes T27,T87,T103 OUTPUT
edn_o[0].edn_ack Yes Yes T27,T87,T103 Yes T27,T87,T103 OUTPUT
edn_o[1].edn_bus[31:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[1].edn_fips[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[1].edn_ack[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[2].edn_bus[31:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[2].edn_fips[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[2].edn_ack[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[3].edn_bus[31:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[3].edn_fips[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[3].edn_ack[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[4].edn_bus[31:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[4].edn_fips[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[4].edn_ack[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[5].edn_bus[31:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[5].edn_fips[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[5].edn_ack[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[6].edn_bus[31:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[6].edn_fips[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[6].edn_ack[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[7].edn_bus[31:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[7].edn_fips[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[7].edn_ack[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
csrng_cmd_o.genbits_ready Yes Yes T27,T87,T103 Yes T27,T87,T103 OUTPUT
csrng_cmd_o.csrng_req_bus[31:0] Yes Yes T27,T87,T103 Yes T27,T87,T103 OUTPUT
csrng_cmd_o.csrng_req_valid Yes Yes T27,T87,T103 Yes T27,T87,T103 OUTPUT
csrng_cmd_i.genbits_bus[127:0] Yes Yes T27,T87,T103 Yes T27,T87,T103 INPUT
csrng_cmd_i.genbits_fips No No Yes T621,T622,T623 INPUT
csrng_cmd_i.genbits_valid Yes Yes T27,T87,T103 Yes T27,T87,T103 INPUT
csrng_cmd_i.csrng_rsp_sts[2:0] No No No INPUT
csrng_cmd_i.csrng_rsp_ack Yes Yes T27,T87,T103 Yes T27,T87,T103 INPUT
csrng_cmd_i.csrng_req_ready Yes Yes T27,T421,T422 Yes T27,T421,T422 INPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T158,T84,T44 Yes T158,T84,T44 INPUT
alert_rx_i[0].ping_n Yes Yes T158,T84,T85 Yes T158,T84,T85 INPUT
alert_rx_i[0].ping_p Yes Yes T158,T84,T85 Yes T158,T84,T85 INPUT
alert_rx_i[1].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[1].ack_p Yes Yes T328,T84,T44 Yes T328,T84,T44 INPUT
alert_rx_i[1].ping_n Yes Yes T84,T85,T86 Yes T84,T85,T86 INPUT
alert_rx_i[1].ping_p Yes Yes T84,T85,T86 Yes T84,T85,T86 INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T158,T84,T44 Yes T158,T84,T44 OUTPUT
alert_tx_o[1].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[1].alert_p Yes Yes T328,T84,T44 Yes T328,T84,T44 OUTPUT
intr_edn_cmd_req_done_o Yes Yes T292,T299,T302 Yes T292,T299,T302 OUTPUT
intr_edn_fatal_err_o Yes Yes T292,T299,T296 Yes T292,T299,T296 OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.top_earlgrey.u_edn0
TotalCoveredPercent
Totals 78 74 94.87
Total Bits 1208 1199 99.25
Total Bits 0->1 604 601 99.50
Total Bits 1->0 604 598 99.01

Ports 78 74 94.87
Port Bits 1208 1199 99.25
Port Bits 0->1 604 601 99.50
Port Bits 1->0 604 598 99.01

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T4,T6 Yes T1,T2,T3 INPUT
tl_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T2,T27,T87 Yes T2,T27,T87 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T2,T27,T87 Yes T2,T27,T87 INPUT
tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_address[6:0] Yes Yes *T78,*T82,*T153 Yes T78,T82,T153 INPUT
tl_i.a_address[15:7] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[18:16] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_address[19] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[20] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[23:21] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[24] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[29:25] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes *T68,*T50,*T81 Yes T68,T50,T81 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T77,T78,T82 Yes T77,T78,T82 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T77,T78,T82 Yes T77,T78,T82 INPUT
tl_i.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_o.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_error Yes Yes T78,T82,T153 Yes T77,T78,T82 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T2,T27,T87 Yes T2,T27,T87 OUTPUT
tl_o.d_user.rsp_intg[6:0] Yes Yes T2,T27,T4 Yes T1,T2,T3 OUTPUT
tl_o.d_data[31:0] Yes Yes T2,T27,T4 Yes T1,T2,T3 OUTPUT
tl_o.d_sink Yes Yes T77,T78,T82 Yes T77,T78,T82 OUTPUT
tl_o.d_source[5:0] Yes Yes *T68,*T50,*T81 Yes T68,T50,T81 OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[1:0] Yes Yes T77,T78,T82 Yes T77,T78,T82 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T2,*T27,*T87 Yes T2,T27,T87 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_i[0].edn_req Yes Yes T171,T172,T94 Yes T171,T172,T94 INPUT
edn_i[1].edn_req Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
edn_i[2].edn_req Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
edn_i[3].edn_req Yes Yes T419,T189,T198 Yes T419,T189,T198 INPUT
edn_i[4].edn_req Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
edn_i[5].edn_req Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
edn_i[6].edn_req Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
edn_i[7].edn_req Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
edn_o[0].edn_bus[31:0] Yes Yes T171,T94,T218 Yes T171,T172,T94 OUTPUT
edn_o[0].edn_fips No No Yes T171,T172,T119 OUTPUT
edn_o[0].edn_ack Yes Yes T171,T172,T94 Yes T171,T172,T94 OUTPUT
edn_o[1].edn_bus[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[1].edn_fips No No Yes T87,T103,T118 OUTPUT
edn_o[1].edn_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[2].edn_bus[31:0] Yes Yes T2,T27,T4 Yes T1,T2,T3 OUTPUT
edn_o[2].edn_fips Yes Yes T115,T116,T117 Yes T118,T115,T119 OUTPUT
edn_o[2].edn_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[3].edn_bus[31:0] Yes Yes T419,T189,T198 Yes T419,T189,T198 OUTPUT
edn_o[3].edn_fips No No Yes T419,T189,T198 OUTPUT
edn_o[3].edn_ack Yes Yes T419,T189,T198 Yes T419,T189,T198 OUTPUT
edn_o[4].edn_bus[31:0] Yes Yes T2,T4,T6 Yes T2,T3,T4 OUTPUT
edn_o[4].edn_fips Yes Yes T117 Yes T118,T625,T626 OUTPUT
edn_o[4].edn_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[5].edn_bus[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[5].edn_fips Yes Yes T27,T421,T422 Yes T27,T172,T219 OUTPUT
edn_o[5].edn_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[6].edn_bus[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[6].edn_fips Yes Yes T27,T421,T422 Yes T27,T87,T103 OUTPUT
edn_o[6].edn_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[7].edn_bus[31:0] Yes Yes T27,T4,T39 Yes T1,T2,T27 OUTPUT
edn_o[7].edn_fips Yes Yes T27,T115,T116 Yes T27,T115,T116 OUTPUT
edn_o[7].edn_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
csrng_cmd_o.genbits_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
csrng_cmd_o.csrng_req_bus[31:0] Yes Yes T2,T27,T4 Yes T1,T2,T3 OUTPUT
csrng_cmd_o.csrng_req_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
csrng_cmd_i.genbits_bus[127:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
csrng_cmd_i.genbits_fips Yes Yes T115,T116,T621 Yes T27,T87,T103 INPUT
csrng_cmd_i.genbits_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
csrng_cmd_i.csrng_rsp_sts[2:0] No No No INPUT
csrng_cmd_i.csrng_rsp_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
csrng_cmd_i.csrng_req_ready Yes Yes T27,T399,T421 Yes T27,T399,T421 INPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T84,T44,T399 Yes T84,T44,T399 INPUT
alert_rx_i[0].ping_n Yes Yes T84,T85,T86 Yes T84,T85,T86 INPUT
alert_rx_i[0].ping_p Yes Yes T84,T85,T86 Yes T84,T85,T86 INPUT
alert_rx_i[1].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[1].ack_p Yes Yes T84,T44,T68 Yes T84,T44,T68 INPUT
alert_rx_i[1].ping_n Yes Yes T84,T157,T85 Yes T84,T157,T85 INPUT
alert_rx_i[1].ping_p Yes Yes T84,T157,T85 Yes T84,T157,T85 INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T84,T44,T399 Yes T84,T44,T399 OUTPUT
alert_tx_o[1].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[1].alert_p Yes Yes T84,T44,T68 Yes T84,T44,T68 OUTPUT
intr_edn_cmd_req_done_o Yes Yes T292,T299,T302 Yes T292,T299,T302 OUTPUT
intr_edn_fatal_err_o Yes Yes T292,T299,T296 Yes T292,T299,T296 OUTPUT

*Tests covering at least one bit in the range
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%