Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	50	0	50	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	50	0	50	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	50	0	50	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	480	1			T227	2		T421	6		T556	1
all_values[1]	536	1			T421	4		T495	1		T556	3
all_values[2]	521	1			T561	1		T421	6		T886	1
all_values[3]	482	1			T421	4		T556	3		T897	1
all_values[4]	489	1			T421	4		T495	1		T556	1
all_values[5]	488	1			T227	3		T777	2		T421	5
all_values[6]	463	1			T227	1		T561	1		T421	7
all_values[7]	502	1			T227	1		T421	6		T556	3
all_values[8]	511	1			T227	1		T421	3		T556	5
all_values[9]	469	1			T227	1		T561	1		T421	4
all_values[10]	446	1			T227	1		T421	7		T556	4
all_values[11]	513	1			T227	1		T777	1		T421	6
all_values[12]	485	1			T227	1		T777	1		T421	3
all_values[13]	477	1			T421	5		T556	4		T897	4
all_values[14]	486	1			T227	2		T421	1		T495	1
all_values[15]	452	1			T421	5		T556	4		T897	1
all_values[16]	545	1			T421	9		T495	1		T556	3
all_values[17]	518	1			T421	14		T556	4		T897	2
all_values[18]	490	1			T421	6		T556	2		T897	2
all_values[19]	490	1			T421	4		T556	5		T897	4
all_values[20]	501	1			T227	1		T421	7		T556	3
all_values[21]	483	1			T421	6		T495	1		T556	5
all_values[22]	536	1			T227	3		T421	3		T495	1
all_values[23]	525	1			T421	6		T495	1		T556	6
all_values[24]	531	1			T227	1		T421	4		T495	1
all_values[25]	519	1			T227	1		T421	5		T556	3
all_values[26]	526	1			T227	1		T421	9		T556	3
all_values[27]	504	1			T227	1		T421	2		T556	4
all_values[28]	468	1			T421	6		T556	2		T897	2
all_values[29]	485	1			T777	1		T421	2		T495	1
all_values[30]	494	1			T227	2		T421	6		T556	2
all_values[31]	523	1			T777	1		T421	13		T556	1
all_values[32]	479	1			T421	4		T886	1		T556	3
all_values[33]	475	1			T421	6		T556	3		T897	10
all_values[34]	481	1			T421	9		T495	2		T556	7
all_values[35]	476	1			T421	7		T886	1		T495	2
all_values[36]	482	1			T227	2		T777	1		T421	5
all_values[37]	486	1			T421	3		T495	1		T556	5
all_values[38]	473	1			T227	1		T421	5		T556	2
all_values[39]	520	1			T421	5		T495	1		T556	4
all_values[40]	503	1			T227	2		T421	5		T495	2
all_values[41]	500	1			T777	1		T421	4		T495	1
all_values[42]	484	1			T227	1		T561	1		T421	6
all_values[43]	481	1			T421	6		T495	2		T897	4
all_values[44]	473	1			T227	1		T421	4		T556	2
all_values[45]	484	1			T227	1		T421	5		T556	1
all_values[46]	490	1			T227	1		T421	6		T556	8
all_values[47]	460	1			T421	6		T556	2		T897	2
all_values[48]	482	1			T227	1		T777	1		T495	1
all_values[49]	501	1			T561	1		T421	2		T556	2