Name |
/workspace/coverage/cover_reg_top/0.chip_csr_bit_bash.3351246354 |
/workspace/coverage/cover_reg_top/0.chip_csr_rw.2330748382 |
/workspace/coverage/cover_reg_top/0.chip_prim_tl_access.2636663300 |
/workspace/coverage/cover_reg_top/0.chip_same_csr_outstanding.3509912440 |
/workspace/coverage/cover_reg_top/0.chip_tl_errors.3708808175 |
/workspace/coverage/cover_reg_top/0.xbar_access_same_device.2782760071 |
/workspace/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.806515937 |
/workspace/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.2233472965 |
/workspace/coverage/cover_reg_top/0.xbar_error_random.3276400533 |
/workspace/coverage/cover_reg_top/0.xbar_random.2319320321 |
/workspace/coverage/cover_reg_top/0.xbar_random_large_delays.3613644690 |
/workspace/coverage/cover_reg_top/0.xbar_random_zero_delays.2856578372 |
/workspace/coverage/cover_reg_top/0.xbar_same_source.2087740909 |
/workspace/coverage/cover_reg_top/0.xbar_smoke.3986849869 |
/workspace/coverage/cover_reg_top/0.xbar_smoke_large_delays.3494541899 |
/workspace/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.3126525748 |
/workspace/coverage/cover_reg_top/0.xbar_smoke_zero_delays.1951476892 |
/workspace/coverage/cover_reg_top/0.xbar_stress_all.755005013 |
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.4045471752 |
/workspace/coverage/cover_reg_top/0.xbar_unmapped_addr.2285167250 |
/workspace/coverage/cover_reg_top/1.chip_csr_aliasing.1754204157 |
/workspace/coverage/cover_reg_top/1.chip_csr_bit_bash.4255220115 |
/workspace/coverage/cover_reg_top/1.chip_csr_mem_rw_with_rand_reset.2297040112 |
/workspace/coverage/cover_reg_top/1.chip_csr_rw.2306626231 |
/workspace/coverage/cover_reg_top/1.chip_prim_tl_access.563386532 |
/workspace/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.992609173 |
/workspace/coverage/cover_reg_top/1.chip_same_csr_outstanding.1546996115 |
/workspace/coverage/cover_reg_top/1.chip_tl_errors.3022414883 |
/workspace/coverage/cover_reg_top/1.xbar_access_same_device.791561217 |
/workspace/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.815763777 |
/workspace/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.2170373834 |
/workspace/coverage/cover_reg_top/1.xbar_error_random.3073176301 |
/workspace/coverage/cover_reg_top/1.xbar_random.1730034185 |
/workspace/coverage/cover_reg_top/1.xbar_random_large_delays.1893768964 |
/workspace/coverage/cover_reg_top/1.xbar_random_slow_rsp.1287467359 |
/workspace/coverage/cover_reg_top/1.xbar_random_zero_delays.1619016027 |
/workspace/coverage/cover_reg_top/1.xbar_same_source.3505613537 |
/workspace/coverage/cover_reg_top/1.xbar_smoke.1306179548 |
/workspace/coverage/cover_reg_top/1.xbar_smoke_large_delays.3989524546 |
/workspace/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.3129575093 |
/workspace/coverage/cover_reg_top/1.xbar_smoke_zero_delays.527297286 |
/workspace/coverage/cover_reg_top/1.xbar_stress_all.2845637320 |
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_error.834050089 |
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.1440475528 |
/workspace/coverage/cover_reg_top/1.xbar_unmapped_addr.3392013350 |
/workspace/coverage/cover_reg_top/10.chip_csr_rw.2646057761 |
/workspace/coverage/cover_reg_top/10.xbar_access_same_device.2774373407 |
/workspace/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.1666492642 |
/workspace/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.1313832278 |
/workspace/coverage/cover_reg_top/10.xbar_error_random.4293851006 |
/workspace/coverage/cover_reg_top/10.xbar_random.1569863855 |
/workspace/coverage/cover_reg_top/10.xbar_random_large_delays.1809994543 |
/workspace/coverage/cover_reg_top/10.xbar_random_slow_rsp.1245603917 |
/workspace/coverage/cover_reg_top/10.xbar_random_zero_delays.1647265056 |
/workspace/coverage/cover_reg_top/10.xbar_same_source.3975051598 |
/workspace/coverage/cover_reg_top/10.xbar_smoke.3472120895 |
/workspace/coverage/cover_reg_top/10.xbar_smoke_large_delays.71121719 |
/workspace/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.1583468614 |
/workspace/coverage/cover_reg_top/10.xbar_smoke_zero_delays.3947597786 |
/workspace/coverage/cover_reg_top/10.xbar_stress_all.3691620598 |
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_error.525487979 |
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.2955155048 |
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.630581298 |
/workspace/coverage/cover_reg_top/10.xbar_unmapped_addr.3519662920 |
/workspace/coverage/cover_reg_top/11.chip_csr_mem_rw_with_rand_reset.617695509 |
/workspace/coverage/cover_reg_top/11.chip_csr_rw.2584512837 |
/workspace/coverage/cover_reg_top/11.xbar_access_same_device.2177906378 |
/workspace/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.2789635842 |
/workspace/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.3335803519 |
/workspace/coverage/cover_reg_top/11.xbar_error_random.2902941582 |
/workspace/coverage/cover_reg_top/11.xbar_random.1950316655 |
/workspace/coverage/cover_reg_top/11.xbar_random_large_delays.2905031395 |
/workspace/coverage/cover_reg_top/11.xbar_random_slow_rsp.3010475789 |
/workspace/coverage/cover_reg_top/11.xbar_random_zero_delays.725166226 |
/workspace/coverage/cover_reg_top/11.xbar_same_source.371926408 |
/workspace/coverage/cover_reg_top/11.xbar_smoke.1626486995 |
/workspace/coverage/cover_reg_top/11.xbar_smoke_large_delays.2392178748 |
/workspace/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.51751452 |
/workspace/coverage/cover_reg_top/11.xbar_smoke_zero_delays.1267790927 |
/workspace/coverage/cover_reg_top/11.xbar_stress_all.1428365572 |
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_error.2564848057 |
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.3341953079 |
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.2494617158 |
/workspace/coverage/cover_reg_top/11.xbar_unmapped_addr.3601683893 |
/workspace/coverage/cover_reg_top/12.chip_csr_mem_rw_with_rand_reset.3061306128 |
/workspace/coverage/cover_reg_top/12.chip_csr_rw.1227215919 |
/workspace/coverage/cover_reg_top/12.chip_same_csr_outstanding.1238999161 |
/workspace/coverage/cover_reg_top/12.chip_tl_errors.2828412922 |
/workspace/coverage/cover_reg_top/12.xbar_access_same_device.1219884642 |
/workspace/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.4117127138 |
/workspace/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.1604146380 |
/workspace/coverage/cover_reg_top/12.xbar_error_random.1527536738 |
/workspace/coverage/cover_reg_top/12.xbar_random.803080484 |
/workspace/coverage/cover_reg_top/12.xbar_random_large_delays.1397417017 |
/workspace/coverage/cover_reg_top/12.xbar_random_slow_rsp.1157983654 |
/workspace/coverage/cover_reg_top/12.xbar_random_zero_delays.3252106815 |
/workspace/coverage/cover_reg_top/12.xbar_same_source.2288243326 |
/workspace/coverage/cover_reg_top/12.xbar_smoke.80895147 |
/workspace/coverage/cover_reg_top/12.xbar_smoke_large_delays.269672921 |
/workspace/coverage/cover_reg_top/12.xbar_smoke_slow_rsp.2175547695 |
/workspace/coverage/cover_reg_top/12.xbar_smoke_zero_delays.2613669280 |
/workspace/coverage/cover_reg_top/12.xbar_stress_all.487597052 |
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_error.1354324111 |
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_rand_reset.1220417126 |
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_reset_error.3127465312 |
/workspace/coverage/cover_reg_top/12.xbar_unmapped_addr.489460619 |
/workspace/coverage/cover_reg_top/13.chip_csr_mem_rw_with_rand_reset.415919262 |
/workspace/coverage/cover_reg_top/13.chip_csr_rw.2406906729 |
/workspace/coverage/cover_reg_top/13.chip_same_csr_outstanding.1569214426 |
/workspace/coverage/cover_reg_top/13.chip_tl_errors.1374144683 |
/workspace/coverage/cover_reg_top/13.xbar_access_same_device.2966686464 |
/workspace/coverage/cover_reg_top/13.xbar_access_same_device_slow_rsp.1576918367 |
/workspace/coverage/cover_reg_top/13.xbar_error_and_unmapped_addr.3592906808 |
/workspace/coverage/cover_reg_top/13.xbar_error_random.3793581853 |
/workspace/coverage/cover_reg_top/13.xbar_random.3997019388 |
/workspace/coverage/cover_reg_top/13.xbar_random_large_delays.1213847562 |
/workspace/coverage/cover_reg_top/13.xbar_random_slow_rsp.2769859624 |
/workspace/coverage/cover_reg_top/13.xbar_random_zero_delays.2989153818 |
/workspace/coverage/cover_reg_top/13.xbar_same_source.2742567516 |
/workspace/coverage/cover_reg_top/13.xbar_smoke.669995426 |
/workspace/coverage/cover_reg_top/13.xbar_smoke_large_delays.1353023298 |
/workspace/coverage/cover_reg_top/13.xbar_smoke_slow_rsp.1547604040 |
/workspace/coverage/cover_reg_top/13.xbar_smoke_zero_delays.3019106255 |
/workspace/coverage/cover_reg_top/13.xbar_stress_all.2333568451 |
/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_error.3884686587 |
/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_rand_reset.1712757885 |
/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_reset_error.3428086365 |
/workspace/coverage/cover_reg_top/13.xbar_unmapped_addr.3691824463 |
/workspace/coverage/cover_reg_top/14.chip_csr_mem_rw_with_rand_reset.3816703680 |
/workspace/coverage/cover_reg_top/14.chip_csr_rw.307007269 |
/workspace/coverage/cover_reg_top/14.chip_same_csr_outstanding.239026671 |
/workspace/coverage/cover_reg_top/14.chip_tl_errors.1484498847 |
/workspace/coverage/cover_reg_top/14.xbar_access_same_device.2328978290 |
/workspace/coverage/cover_reg_top/14.xbar_access_same_device_slow_rsp.3373857242 |
/workspace/coverage/cover_reg_top/14.xbar_error_and_unmapped_addr.821146028 |
/workspace/coverage/cover_reg_top/14.xbar_error_random.1919281666 |
/workspace/coverage/cover_reg_top/14.xbar_random.3307584027 |
/workspace/coverage/cover_reg_top/14.xbar_random_large_delays.2197701226 |
/workspace/coverage/cover_reg_top/14.xbar_random_slow_rsp.647704610 |
/workspace/coverage/cover_reg_top/14.xbar_random_zero_delays.3080219306 |
/workspace/coverage/cover_reg_top/14.xbar_same_source.2330928946 |
/workspace/coverage/cover_reg_top/14.xbar_smoke.3301401534 |
/workspace/coverage/cover_reg_top/14.xbar_smoke_large_delays.4079449419 |
/workspace/coverage/cover_reg_top/14.xbar_smoke_slow_rsp.1161973876 |
/workspace/coverage/cover_reg_top/14.xbar_smoke_zero_delays.3198182563 |
/workspace/coverage/cover_reg_top/14.xbar_stress_all.766497111 |
/workspace/coverage/cover_reg_top/14.xbar_stress_all_with_rand_reset.316967822 |
/workspace/coverage/cover_reg_top/14.xbar_stress_all_with_reset_error.733621781 |
/workspace/coverage/cover_reg_top/14.xbar_unmapped_addr.2418554787 |
/workspace/coverage/cover_reg_top/15.chip_csr_mem_rw_with_rand_reset.2799149286 |
/workspace/coverage/cover_reg_top/15.chip_csr_rw.606386524 |
/workspace/coverage/cover_reg_top/15.chip_same_csr_outstanding.550280942 |
/workspace/coverage/cover_reg_top/15.xbar_access_same_device.782174647 |
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/workspace/coverage/cover_reg_top/15.xbar_error_and_unmapped_addr.2781105173 |
/workspace/coverage/cover_reg_top/15.xbar_error_random.2139213705 |
/workspace/coverage/cover_reg_top/15.xbar_random.3839516386 |
/workspace/coverage/cover_reg_top/15.xbar_random_large_delays.1223448065 |
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/workspace/coverage/cover_reg_top/15.xbar_stress_all.2486803509 |
/workspace/coverage/cover_reg_top/15.xbar_stress_all_with_error.2251907473 |
/workspace/coverage/cover_reg_top/15.xbar_stress_all_with_rand_reset.2922515023 |
/workspace/coverage/cover_reg_top/15.xbar_stress_all_with_reset_error.1166321103 |
/workspace/coverage/cover_reg_top/15.xbar_unmapped_addr.1337257503 |
/workspace/coverage/cover_reg_top/16.chip_csr_mem_rw_with_rand_reset.1886274554 |
/workspace/coverage/cover_reg_top/16.chip_csr_rw.1936508069 |
/workspace/coverage/cover_reg_top/16.chip_same_csr_outstanding.71286911 |
/workspace/coverage/cover_reg_top/16.xbar_access_same_device.4005353533 |
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/workspace/coverage/cover_reg_top/16.xbar_error_and_unmapped_addr.3782455584 |
/workspace/coverage/cover_reg_top/16.xbar_error_random.2149104915 |
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/workspace/coverage/cover_reg_top/17.chip_same_csr_outstanding.3234298868 |
/workspace/coverage/cover_reg_top/17.chip_tl_errors.88102717 |
/workspace/coverage/cover_reg_top/17.xbar_access_same_device.3251533598 |
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/workspace/coverage/cover_reg_top/19.xbar_access_same_device.2076077984 |
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/workspace/coverage/cover_reg_top/19.xbar_same_source.920182266 |
/workspace/coverage/cover_reg_top/19.xbar_smoke.1889431882 |
/workspace/coverage/cover_reg_top/19.xbar_smoke_large_delays.2584389977 |
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/workspace/coverage/cover_reg_top/19.xbar_smoke_zero_delays.2298764057 |
/workspace/coverage/cover_reg_top/19.xbar_stress_all.2265216061 |
/workspace/coverage/cover_reg_top/19.xbar_stress_all_with_error.3023533014 |
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/workspace/coverage/cover_reg_top/19.xbar_stress_all_with_reset_error.3035297775 |
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/workspace/coverage/default/2.rom_e2e_asm_init_test_unlocked0.1435213255 |
/workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_invalid_meas.947420230 |
/workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_meas.943939446 |
/workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_no_meas.1445922898 |
/workspace/coverage/default/2.rom_e2e_self_hash.3089841410 |
/workspace/coverage/default/2.rom_e2e_shutdown_exception_c.2668392674 |
/workspace/coverage/default/2.rom_e2e_shutdown_output.1927224459 |
/workspace/coverage/default/2.rom_e2e_smoke.390125613 |
/workspace/coverage/default/2.rom_e2e_static_critical.2864328182 |
/workspace/coverage/default/2.rom_keymgr_functest.3292223737 |
/workspace/coverage/default/2.rom_raw_unlock.3332292722 |
/workspace/coverage/default/2.rom_volatile_raw_unlock.2110433507 |
/workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.2186880582 |
/workspace/coverage/default/22.chip_sw_all_escalation_resets.1318762167 |
/workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.2452463327 |
/workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.1356882015 |
/workspace/coverage/default/26.chip_sw_all_escalation_resets.3037791985 |
/workspace/coverage/default/27.chip_sw_all_escalation_resets.2363412973 |
/workspace/coverage/default/28.chip_sw_all_escalation_resets.1978396272 |
/workspace/coverage/default/29.chip_sw_all_escalation_resets.3200841646 |
/workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.259983541 |
/workspace/coverage/default/3.chip_sw_csrng_edn_concurrency.4294562677 |
/workspace/coverage/default/3.chip_sw_data_integrity_escalation.3416166435 |
/workspace/coverage/default/3.chip_sw_lc_ctrl_transition.2370204796 |
/workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.1902147245 |
/workspace/coverage/default/3.chip_sw_uart_rand_baudrate.3285129561 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx.558518421 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.2760038820 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1358377840 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx1.2155797998 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.1047375500 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx3.1598672547 |
/workspace/coverage/default/3.chip_tap_straps_dev.3591767047 |
/workspace/coverage/default/3.chip_tap_straps_prod.3931366151 |
/workspace/coverage/default/3.chip_tap_straps_rma.1818977210 |
/workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.2283176724 |
/workspace/coverage/default/32.chip_sw_all_escalation_resets.1614194008 |
/workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.951945325 |
/workspace/coverage/default/33.chip_sw_all_escalation_resets.529482299 |
/workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.2103127686 |
/workspace/coverage/default/36.chip_sw_all_escalation_resets.3262312202 |
/workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.3989469380 |
/workspace/coverage/default/38.chip_sw_all_escalation_resets.3732672307 |
/workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.2452137800 |
/workspace/coverage/default/39.chip_sw_all_escalation_resets.1466961912 |
/workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.1318776595 |
/workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.2896397464 |
/workspace/coverage/default/4.chip_sw_csrng_edn_concurrency.995895477 |
/workspace/coverage/default/4.chip_sw_data_integrity_escalation.2236395314 |
/workspace/coverage/default/4.chip_sw_lc_ctrl_transition.1612690455 |
/workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.148318204 |
/workspace/coverage/default/4.chip_sw_uart_rand_baudrate.4049131098 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx.628727410 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.3236169169 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.2762918583 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.4125542880 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.1145481536 |
/workspace/coverage/default/4.chip_tap_straps_dev.2528481625 |
/workspace/coverage/default/4.chip_tap_straps_prod.2481515477 |
/workspace/coverage/default/4.chip_tap_straps_rma.1366449004 |
/workspace/coverage/default/4.chip_tap_straps_testunlock0.1654945808 |
/workspace/coverage/default/41.chip_sw_all_escalation_resets.3251961434 |
/workspace/coverage/default/42.chip_sw_all_escalation_resets.4120324400 |
/workspace/coverage/default/43.chip_sw_all_escalation_resets.4070856526 |
/workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.1534460939 |
/workspace/coverage/default/44.chip_sw_all_escalation_resets.624085771 |
/workspace/coverage/default/45.chip_sw_all_escalation_resets.860435786 |
/workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.2214800277 |
/workspace/coverage/default/46.chip_sw_all_escalation_resets.3927617960 |
/workspace/coverage/default/47.chip_sw_all_escalation_resets.2631390493 |
/workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.3070344980 |
/workspace/coverage/default/48.chip_sw_all_escalation_resets.4081977410 |
/workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.105439193 |
/workspace/coverage/default/5.chip_sw_all_escalation_resets.2320172633 |
/workspace/coverage/default/5.chip_sw_csrng_edn_concurrency.346941422 |
/workspace/coverage/default/5.chip_sw_data_integrity_escalation.76008848 |
/workspace/coverage/default/5.chip_sw_lc_ctrl_transition.4132535763 |
/workspace/coverage/default/5.chip_sw_uart_rand_baudrate.3177335610 |
/workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.2386104095 |
/workspace/coverage/default/51.chip_sw_all_escalation_resets.742756913 |
/workspace/coverage/default/52.chip_sw_all_escalation_resets.3167560117 |
/workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.401179603 |
/workspace/coverage/default/53.chip_sw_all_escalation_resets.2377178089 |
/workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.2522110248 |
/workspace/coverage/default/54.chip_sw_all_escalation_resets.448048200 |
/workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.1400359385 |
/workspace/coverage/default/55.chip_sw_all_escalation_resets.4258400438 |
/workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.3940371085 |
/workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.3793124626 |
/workspace/coverage/default/57.chip_sw_all_escalation_resets.3109428296 |
/workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.1965791899 |
/workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.289183388 |
/workspace/coverage/default/6.chip_sw_csrng_edn_concurrency.1138849854 |
/workspace/coverage/default/6.chip_sw_lc_ctrl_transition.2037197971 |
/workspace/coverage/default/6.chip_sw_uart_rand_baudrate.580988280 |
/workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.3126849696 |
/workspace/coverage/default/61.chip_sw_all_escalation_resets.2221079304 |
/workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.4006186707 |
/workspace/coverage/default/62.chip_sw_all_escalation_resets.1852391771 |
/workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.824974924 |
/workspace/coverage/default/64.chip_sw_all_escalation_resets.834230077 |
/workspace/coverage/default/65.chip_sw_all_escalation_resets.3390107706 |
/workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.3381494484 |
/workspace/coverage/default/66.chip_sw_all_escalation_resets.2710600841 |
/workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.3526053746 |
/workspace/coverage/default/67.chip_sw_all_escalation_resets.4266875552 |
/workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.1446830311 |
/workspace/coverage/default/68.chip_sw_all_escalation_resets.2444332381 |
/workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.478783951 |
/workspace/coverage/default/69.chip_sw_all_escalation_resets.1914814407 |
/workspace/coverage/default/7.chip_sw_all_escalation_resets.641500309 |
/workspace/coverage/default/7.chip_sw_csrng_edn_concurrency.3072412119 |
/workspace/coverage/default/7.chip_sw_lc_ctrl_transition.2824375289 |
/workspace/coverage/default/7.chip_sw_uart_rand_baudrate.3402324415 |
/workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.3850921141 |
/workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.2793534884 |
/workspace/coverage/default/71.chip_sw_all_escalation_resets.2383721099 |
/workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.1340832509 |
/workspace/coverage/default/72.chip_sw_all_escalation_resets.3808254889 |
/workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.59846703 |
/workspace/coverage/default/73.chip_sw_all_escalation_resets.3357485341 |
/workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.1420436405 |
/workspace/coverage/default/74.chip_sw_all_escalation_resets.1042628176 |
/workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.473121618 |
/workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.3261818565 |
/workspace/coverage/default/76.chip_sw_all_escalation_resets.867843220 |
/workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.1345162113 |
/workspace/coverage/default/77.chip_sw_all_escalation_resets.4185462554 |
/workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.1256427338 |
/workspace/coverage/default/78.chip_sw_all_escalation_resets.1794937172 |
/workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.320402635 |
/workspace/coverage/default/79.chip_sw_all_escalation_resets.3215391560 |
/workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.3723439987 |
/workspace/coverage/default/8.chip_sw_csrng_edn_concurrency.3832555325 |
/workspace/coverage/default/8.chip_sw_lc_ctrl_transition.3751151116 |
/workspace/coverage/default/8.chip_sw_uart_rand_baudrate.646556033 |
/workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.2437816947 |
/workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.3439764800 |
/workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.857062917 |
/workspace/coverage/default/82.chip_sw_all_escalation_resets.1787662061 |
/workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.1775538828 |
/workspace/coverage/default/83.chip_sw_all_escalation_resets.1164841379 |
/workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.4029387204 |
/workspace/coverage/default/84.chip_sw_all_escalation_resets.3322754146 |
/workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.3210209975 |
/workspace/coverage/default/85.chip_sw_all_escalation_resets.826772786 |
/workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.1862658199 |
/workspace/coverage/default/86.chip_sw_all_escalation_resets.1826566873 |
/workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.1856368779 |
/workspace/coverage/default/87.chip_sw_all_escalation_resets.94104492 |
/workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.2541241678 |
/workspace/coverage/default/88.chip_sw_all_escalation_resets.1975054534 |
/workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.913801757 |
/workspace/coverage/default/89.chip_sw_all_escalation_resets.2208846408 |
/workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.3423125783 |
/workspace/coverage/default/9.chip_sw_all_escalation_resets.3969234331 |
/workspace/coverage/default/9.chip_sw_csrng_edn_concurrency.2251950808 |
/workspace/coverage/default/9.chip_sw_lc_ctrl_transition.982338608 |
/workspace/coverage/default/9.chip_sw_uart_rand_baudrate.2109245649 |
/workspace/coverage/default/90.chip_sw_all_escalation_resets.887114864 |
/workspace/coverage/default/91.chip_sw_all_escalation_resets.371008527 |
/workspace/coverage/default/92.chip_sw_all_escalation_resets.758433042 |
/workspace/coverage/default/93.chip_sw_all_escalation_resets.2655307007 |
/workspace/coverage/default/94.chip_sw_all_escalation_resets.41302538 |
/workspace/coverage/default/95.chip_sw_all_escalation_resets.3358280890 |
/workspace/coverage/default/96.chip_sw_all_escalation_resets.3831378189 |
/workspace/coverage/default/98.chip_sw_all_escalation_resets.3187502548 |
/workspace/coverage/default/99.chip_sw_all_escalation_resets.377294301 |
/workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.2149797186 |
/workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.1948658276 |
/workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.1726404817 |
/workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.1221262080 |
/workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.598668445 |
/workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.3420465919 |
/workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.3414783364 |
/workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.2530429001 |
TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
T1 |
/workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.1398476817 |
|
|
Aug 06 08:42:47 PM PDT 24 |
Aug 06 08:49:31 PM PDT 24 |
3738402888 ps |
T2 |
/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.975138550 |
|
|
Aug 06 08:28:37 PM PDT 24 |
Aug 06 09:34:05 PM PDT 24 |
41847749055 ps |
T3 |
/workspace/coverage/default/0.chip_sw_kmac_entropy.3939475746 |
|
|
Aug 06 08:24:01 PM PDT 24 |
Aug 06 08:28:44 PM PDT 24 |
2853371000 ps |
T4 |
/workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.2984221283 |
|
|
Aug 06 08:42:17 PM PDT 24 |
Aug 06 08:51:03 PM PDT 24 |
3480323008 ps |
T62 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_wake_5_bug.1299158102 |
|
|
Aug 06 08:38:15 PM PDT 24 |
Aug 06 08:46:31 PM PDT 24 |
5872041990 ps |
T86 |
/workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.234243505 |
|
|
Aug 06 08:43:09 PM PDT 24 |
Aug 06 08:50:42 PM PDT 24 |
4001746018 ps |
T87 |
/workspace/coverage/default/0.chip_sw_alert_handler_ping_ok.2993077938 |
|
|
Aug 06 08:24:15 PM PDT 24 |
Aug 06 08:47:26 PM PDT 24 |
7938747000 ps |
T33 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.193946907 |
|
|
Aug 06 08:26:27 PM PDT 24 |
Aug 06 08:34:14 PM PDT 24 |
5220310810 ps |
T88 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx.937813598 |
|
|
Aug 06 08:18:15 PM PDT 24 |
Aug 06 08:30:44 PM PDT 24 |
4179605334 ps |
T29 |
/workspace/coverage/default/23.chip_sw_all_escalation_resets.1313801164 |
|
|
Aug 06 08:42:37 PM PDT 24 |
Aug 06 08:52:03 PM PDT 24 |
4693110060 ps |
T47 |
/workspace/coverage/default/2.chip_sw_rv_dm_access_after_wakeup.2665474460 |
|
|
Aug 06 08:38:42 PM PDT 24 |
Aug 06 08:46:12 PM PDT 24 |
6697394240 ps |
T82 |
/workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.3360460913 |
|
|
Aug 06 08:46:03 PM PDT 24 |
Aug 06 08:53:33 PM PDT 24 |
4019276056 ps |
T93 |
/workspace/coverage/default/1.chip_sw_sensor_ctrl_status.1251759807 |
|
|
Aug 06 08:21:44 PM PDT 24 |
Aug 06 08:25:58 PM PDT 24 |
3084369770 ps |
T94 |
/workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.928188600 |
|
|
Aug 06 08:43:40 PM PDT 24 |
Aug 06 08:51:30 PM PDT 24 |
4007198144 ps |
T30 |
/workspace/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.609834265 |
|
|
Aug 06 08:37:01 PM PDT 24 |
Aug 06 08:44:43 PM PDT 24 |
4401118814 ps |
T95 |
/workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.1776624572 |
|
|
Aug 06 08:37:41 PM PDT 24 |
Aug 06 08:43:23 PM PDT 24 |
3235817265 ps |
T5 |
/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_por_reset.1586965633 |
|
|
Aug 06 08:27:53 PM PDT 24 |
Aug 06 08:35:59 PM PDT 24 |
6495069211 ps |
T65 |
/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.2809232052 |
|
|
Aug 06 08:29:12 PM PDT 24 |
Aug 06 09:05:43 PM PDT 24 |
25992598494 ps |
T19 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.2416101048 |
|
|
Aug 06 08:31:18 PM PDT 24 |
Aug 06 09:29:12 PM PDT 24 |
20419216776 ps |
T6 |
/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_por_reset.955471694 |
|
|
Aug 06 08:24:20 PM PDT 24 |
Aug 06 08:33:49 PM PDT 24 |
5264900648 ps |
T44 |
/workspace/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.440038191 |
|
|
Aug 06 08:21:51 PM PDT 24 |
Aug 06 08:30:41 PM PDT 24 |
4896983570 ps |
T196 |
/workspace/coverage/default/0.chip_sw_all_escalation_resets.770887786 |
|
|
Aug 06 08:24:20 PM PDT 24 |
Aug 06 08:34:25 PM PDT 24 |
5536326004 ps |
T45 |
/workspace/coverage/default/1.rom_raw_unlock.179361774 |
|
|
Aug 06 08:23:19 PM PDT 24 |
Aug 06 08:27:24 PM PDT 24 |
5279764784 ps |
T120 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3922985917 |
|
|
Aug 06 08:40:32 PM PDT 24 |
Aug 06 09:02:40 PM PDT 24 |
8556309829 ps |
T114 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.1953991465 |
|
|
Aug 06 08:39:10 PM PDT 24 |
Aug 06 09:03:10 PM PDT 24 |
7141602916 ps |
T151 |
/workspace/coverage/default/1.rom_keymgr_functest.2973209165 |
|
|
Aug 06 08:26:50 PM PDT 24 |
Aug 06 08:39:23 PM PDT 24 |
4388490190 ps |
T128 |
/workspace/coverage/default/0.chip_sw_edn_sw_mode.449163252 |
|
|
Aug 06 08:24:26 PM PDT 24 |
Aug 06 08:59:55 PM PDT 24 |
9732941788 ps |
T222 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.2379952129 |
|
|
Aug 06 08:24:11 PM PDT 24 |
Aug 06 08:32:22 PM PDT 24 |
4721577748 ps |
T115 |
/workspace/coverage/default/1.chip_sw_clkmgr_jitter.650063468 |
|
|
Aug 06 08:28:26 PM PDT 24 |
Aug 06 08:32:17 PM PDT 24 |
2630394724 ps |
T457 |
/workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.1917438234 |
|
|
Aug 06 08:20:48 PM PDT 24 |
Aug 06 08:26:42 PM PDT 24 |
2964506681 ps |
T83 |
/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.3643369717 |
|
|
Aug 06 08:25:04 PM PDT 24 |
Aug 06 08:45:45 PM PDT 24 |
11134448200 ps |
T168 |
/workspace/coverage/default/1.chip_sival_flash_info_access.1431277278 |
|
|
Aug 06 08:22:49 PM PDT 24 |
Aug 06 08:28:40 PM PDT 24 |
3636065342 ps |
T306 |
/workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.253427027 |
|
|
Aug 06 08:21:32 PM PDT 24 |
Aug 06 08:42:18 PM PDT 24 |
6035008052 ps |
T13 |
/workspace/coverage/default/1.chip_sw_gpio.4263227168 |
|
|
Aug 06 08:27:00 PM PDT 24 |
Aug 06 08:33:32 PM PDT 24 |
3475674056 ps |
T281 |
/workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.830592993 |
|
|
Aug 06 08:42:05 PM PDT 24 |
Aug 06 08:49:29 PM PDT 24 |
3782107704 ps |
T220 |
/workspace/coverage/default/2.chip_sw_data_integrity_escalation.4211146769 |
|
|
Aug 06 08:23:43 PM PDT 24 |
Aug 06 08:37:20 PM PDT 24 |
6844696180 ps |
T254 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.1840355669 |
|
|
Aug 06 08:26:24 PM PDT 24 |
Aug 06 08:33:12 PM PDT 24 |
4801431024 ps |
T255 |
/workspace/coverage/default/1.chip_sw_kmac_mode_kmac.1066912234 |
|
|
Aug 06 08:24:37 PM PDT 24 |
Aug 06 08:30:12 PM PDT 24 |
3451718368 ps |
T152 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1306212062 |
|
|
Aug 06 08:21:30 PM PDT 24 |
Aug 06 08:30:09 PM PDT 24 |
4437717940 ps |
T217 |
/workspace/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.4130472292 |
|
|
Aug 06 08:28:04 PM PDT 24 |
Aug 06 08:48:38 PM PDT 24 |
6045304246 ps |
T14 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx3.1598672547 |
|
|
Aug 06 08:39:42 PM PDT 24 |
Aug 06 08:54:11 PM PDT 24 |
4728018540 ps |
T129 |
/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.2095389933 |
|
|
Aug 06 08:32:21 PM PDT 24 |
Aug 06 09:27:28 PM PDT 24 |
17814999784 ps |
T232 |
/workspace/coverage/default/2.chip_sw_rv_timer_irq.3500199076 |
|
|
Aug 06 08:28:07 PM PDT 24 |
Aug 06 08:31:41 PM PDT 24 |
2761770420 ps |
T7 |
/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.2175373630 |
|
|
Aug 06 08:21:53 PM PDT 24 |
Aug 06 08:27:02 PM PDT 24 |
3473296530 ps |
T133 |
/workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.2949674336 |
|
|
Aug 06 08:23:34 PM PDT 24 |
Aug 06 08:34:16 PM PDT 24 |
5352151236 ps |
T46 |
/workspace/coverage/default/1.chip_jtag_csr_rw.1639480282 |
|
|
Aug 06 08:10:45 PM PDT 24 |
Aug 06 08:55:06 PM PDT 24 |
18374922114 ps |
T130 |
/workspace/coverage/default/1.chip_sw_edn_entropy_reqs.1179495053 |
|
|
Aug 06 08:27:47 PM PDT 24 |
Aug 06 08:50:04 PM PDT 24 |
7496074440 ps |
T828 |
/workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.3439764800 |
|
|
Aug 06 08:48:23 PM PDT 24 |
Aug 06 08:53:53 PM PDT 24 |
4203163636 ps |
T20 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.4035983718 |
|
|
Aug 06 08:30:00 PM PDT 24 |
Aug 06 08:57:04 PM PDT 24 |
24136608488 ps |
T829 |
/workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.969917816 |
|
|
Aug 06 08:43:57 PM PDT 24 |
Aug 06 08:51:33 PM PDT 24 |
3907379952 ps |
T363 |
/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.2529161196 |
|
|
Aug 06 08:33:25 PM PDT 24 |
Aug 06 09:14:38 PM PDT 24 |
22719909244 ps |
T932 |
/workspace/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.3458887638 |
|
|
Aug 06 08:24:40 PM PDT 24 |
Aug 06 08:36:55 PM PDT 24 |
6940672792 ps |
T277 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx.4223362603 |
|
|
Aug 06 08:24:14 PM PDT 24 |
Aug 06 08:35:20 PM PDT 24 |
4155728888 ps |
T276 |
/workspace/coverage/default/0.chip_sw_pattgen_ios.1885898054 |
|
|
Aug 06 08:22:37 PM PDT 24 |
Aug 06 08:27:20 PM PDT 24 |
3255923926 ps |
T43 |
/workspace/coverage/default/1.rom_e2e_asm_init_test_unlocked0.420476509 |
|
|
Aug 06 08:35:26 PM PDT 24 |
Aug 06 09:30:36 PM PDT 24 |
10912994655 ps |
T728 |
/workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.884650995 |
|
|
Aug 06 08:41:59 PM PDT 24 |
Aug 06 08:48:35 PM PDT 24 |
3841242008 ps |
T31 |
/workspace/coverage/default/2.chip_sw_spi_host_tx_rx.3403350497 |
|
|
Aug 06 08:23:20 PM PDT 24 |
Aug 06 08:26:47 PM PDT 24 |
3342523200 ps |
T15 |
/workspace/coverage/default/2.chip_sw_gpio.1303053980 |
|
|
Aug 06 08:24:35 PM PDT 24 |
Aug 06 08:32:39 PM PDT 24 |
4197525968 ps |
T228 |
/workspace/coverage/default/12.chip_sw_all_escalation_resets.3031687443 |
|
|
Aug 06 08:42:52 PM PDT 24 |
Aug 06 08:51:59 PM PDT 24 |
5546389550 ps |
T307 |
/workspace/coverage/default/15.chip_sw_uart_rand_baudrate.1136061597 |
|
|
Aug 06 08:41:46 PM PDT 24 |
Aug 06 09:05:58 PM PDT 24 |
8385118616 ps |
T16 |
/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_wake_ups.2277252973 |
|
|
Aug 06 08:39:45 PM PDT 24 |
Aug 06 09:04:13 PM PDT 24 |
21927414140 ps |
T97 |
/workspace/coverage/default/1.chip_sw_otbn_mem_scramble.1901065557 |
|
|
Aug 06 08:28:01 PM PDT 24 |
Aug 06 08:37:14 PM PDT 24 |
3676449176 ps |
T98 |
/workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.893660438 |
|
|
Aug 06 08:44:21 PM PDT 24 |
Aug 06 08:49:17 PM PDT 24 |
3586295752 ps |
T99 |
/workspace/coverage/default/2.chip_sw_rv_plic_smoketest.754180048 |
|
|
Aug 06 08:40:09 PM PDT 24 |
Aug 06 08:43:10 PM PDT 24 |
2847459008 ps |
T40 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_rma.484982288 |
|
|
Aug 06 08:34:58 PM PDT 24 |
Aug 06 10:37:07 PM PDT 24 |
21971882210 ps |
T100 |
/workspace/coverage/default/2.chip_sw_hmac_enc_idle.2814894503 |
|
|
Aug 06 08:34:55 PM PDT 24 |
Aug 06 08:40:23 PM PDT 24 |
3247590768 ps |
T101 |
/workspace/coverage/default/0.chip_sw_sensor_ctrl_status.2125323840 |
|
|
Aug 06 08:26:38 PM PDT 24 |
Aug 06 08:30:55 PM PDT 24 |
2386073292 ps |
T102 |
/workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.2901135229 |
|
|
Aug 06 08:23:27 PM PDT 24 |
Aug 06 08:34:14 PM PDT 24 |
7288667762 ps |
T79 |
/workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.1428712464 |
|
|
Aug 06 08:26:40 PM PDT 24 |
Aug 06 08:34:39 PM PDT 24 |
3650657320 ps |
T103 |
/workspace/coverage/default/0.chip_sw_hmac_enc_idle.3773391207 |
|
|
Aug 06 08:24:42 PM PDT 24 |
Aug 06 08:30:03 PM PDT 24 |
3079691608 ps |
T121 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.2760038820 |
|
|
Aug 06 08:40:52 PM PDT 24 |
Aug 06 09:07:19 PM PDT 24 |
7609841458 ps |
T361 |
/workspace/coverage/default/40.chip_sw_all_escalation_resets.1498596921 |
|
|
Aug 06 08:44:19 PM PDT 24 |
Aug 06 08:55:35 PM PDT 24 |
5165633984 ps |
T63 |
/workspace/coverage/default/1.chip_sw_exit_test_unlocked_bootstrap.790942530 |
|
|
Aug 06 08:26:17 PM PDT 24 |
Aug 06 11:29:42 PM PDT 24 |
57545615626 ps |
T933 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_access.2184726526 |
|
|
Aug 06 08:25:27 PM PDT 24 |
Aug 06 08:42:38 PM PDT 24 |
5670692476 ps |
T405 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_clock_freqs.3817897422 |
|
|
Aug 06 08:25:48 PM PDT 24 |
Aug 06 08:47:54 PM PDT 24 |
5766086690 ps |
T17 |
/workspace/coverage/default/0.chip_sw_usbdev_stream.716754599 |
|
|
Aug 06 08:21:59 PM PDT 24 |
Aug 06 09:38:54 PM PDT 24 |
18541590096 ps |
T317 |
/workspace/coverage/default/2.chip_plic_all_irqs_20.2478666212 |
|
|
Aug 06 08:36:11 PM PDT 24 |
Aug 06 08:51:11 PM PDT 24 |
5087709320 ps |
T41 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod.3159574912 |
|
|
Aug 06 08:35:56 PM PDT 24 |
Aug 06 10:41:41 PM PDT 24 |
24288733604 ps |
T175 |
/workspace/coverage/default/0.rom_e2e_static_critical.3696992605 |
|
|
Aug 06 08:31:41 PM PDT 24 |
Aug 06 09:44:04 PM PDT 24 |
17057703804 ps |
T305 |
/workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.4006186707 |
|
|
Aug 06 08:44:48 PM PDT 24 |
Aug 06 08:50:46 PM PDT 24 |
3436397904 ps |
T934 |
/workspace/coverage/default/2.chip_sw_clkmgr_smoketest.466356881 |
|
|
Aug 06 08:40:34 PM PDT 24 |
Aug 06 08:44:40 PM PDT 24 |
3599190752 ps |
T465 |
/workspace/coverage/default/1.chip_sw_all_escalation_resets.3959428231 |
|
|
Aug 06 08:24:45 PM PDT 24 |
Aug 06 08:34:52 PM PDT 24 |
4711293104 ps |
T466 |
/workspace/coverage/default/73.chip_sw_all_escalation_resets.3357485341 |
|
|
Aug 06 08:46:40 PM PDT 24 |
Aug 06 08:56:26 PM PDT 24 |
4070442976 ps |
T749 |
/workspace/coverage/default/2.chip_sw_hmac_oneshot.2782930632 |
|
|
Aug 06 08:36:20 PM PDT 24 |
Aug 06 08:41:28 PM PDT 24 |
2651173240 ps |
T64 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.4242769279 |
|
|
Aug 06 08:21:57 PM PDT 24 |
Aug 06 08:27:12 PM PDT 24 |
3860094415 ps |
T156 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.2760111233 |
|
|
Aug 06 08:21:02 PM PDT 24 |
Aug 06 08:31:39 PM PDT 24 |
6067468750 ps |
T275 |
/workspace/coverage/default/13.chip_sw_uart_rand_baudrate.926989633 |
|
|
Aug 06 08:41:53 PM PDT 24 |
Aug 06 08:54:07 PM PDT 24 |
4105299800 ps |
T195 |
/workspace/coverage/default/1.chip_sw_alert_handler_escalation.380100646 |
|
|
Aug 06 08:27:06 PM PDT 24 |
Aug 06 08:35:12 PM PDT 24 |
4866194130 ps |
T935 |
/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_por_reset.607257449 |
|
|
Aug 06 08:26:04 PM PDT 24 |
Aug 06 08:32:57 PM PDT 24 |
5295324900 ps |
T111 |
/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en.1247999791 |
|
|
Aug 06 08:20:00 PM PDT 24 |
Aug 06 09:30:51 PM PDT 24 |
18323417022 ps |
T125 |
/workspace/coverage/default/1.chip_sw_entropy_src_csrng.3871411591 |
|
|
Aug 06 08:28:20 PM PDT 24 |
Aug 06 08:58:01 PM PDT 24 |
6739972000 ps |
T221 |
/workspace/coverage/default/2.chip_sw_rstmgr_cpu_info.2881166155 |
|
|
Aug 06 08:26:42 PM PDT 24 |
Aug 06 08:35:15 PM PDT 24 |
6283208164 ps |
T936 |
/workspace/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.1150718080 |
|
|
Aug 06 08:22:44 PM PDT 24 |
Aug 06 09:10:08 PM PDT 24 |
27466910171 ps |
T937 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.3714991840 |
|
|
Aug 06 08:27:22 PM PDT 24 |
Aug 06 08:35:40 PM PDT 24 |
4296877000 ps |
T112 |
/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.2792526556 |
|
|
Aug 06 08:21:34 PM PDT 24 |
Aug 06 08:53:29 PM PDT 24 |
11995817893 ps |
T224 |
/workspace/coverage/default/9.chip_sw_all_escalation_resets.3969234331 |
|
|
Aug 06 08:47:49 PM PDT 24 |
Aug 06 08:57:58 PM PDT 24 |
5382511208 ps |
T247 |
/workspace/coverage/default/2.chip_sw_rom_ctrl_integrity_check.3908498031 |
|
|
Aug 06 08:35:35 PM PDT 24 |
Aug 06 08:44:26 PM PDT 24 |
8654172050 ps |
T257 |
/workspace/coverage/default/2.chip_sw_rstmgr_sw_req.1839871840 |
|
|
Aug 06 08:30:09 PM PDT 24 |
Aug 06 08:36:55 PM PDT 24 |
4165521816 ps |
T258 |
/workspace/coverage/default/1.chip_sw_aon_timer_irq.1083504231 |
|
|
Aug 06 08:24:47 PM PDT 24 |
Aug 06 08:32:34 PM PDT 24 |
3760363580 ps |
T166 |
/workspace/coverage/default/47.chip_sw_all_escalation_resets.2631390493 |
|
|
Aug 06 08:44:26 PM PDT 24 |
Aug 06 08:55:34 PM PDT 24 |
5508390350 ps |
T24 |
/workspace/coverage/default/1.chip_sw_gpio_smoketest.379472207 |
|
|
Aug 06 08:26:41 PM PDT 24 |
Aug 06 08:30:41 PM PDT 24 |
3161429194 ps |
T259 |
/workspace/coverage/default/1.chip_sw_ast_clk_outputs.792284439 |
|
|
Aug 06 08:27:32 PM PDT 24 |
Aug 06 08:46:10 PM PDT 24 |
7246213160 ps |
T126 |
/workspace/coverage/default/0.chip_sw_edn_auto_mode.4094791822 |
|
|
Aug 06 08:24:48 PM PDT 24 |
Aug 06 08:57:18 PM PDT 24 |
5999740150 ps |
T260 |
/workspace/coverage/default/2.chip_sw_clkmgr_off_hmac_trans.1921384899 |
|
|
Aug 06 08:37:42 PM PDT 24 |
Aug 06 08:48:55 PM PDT 24 |
6007324240 ps |
T261 |
/workspace/coverage/default/24.chip_sw_all_escalation_resets.1476487308 |
|
|
Aug 06 08:42:50 PM PDT 24 |
Aug 06 08:53:10 PM PDT 24 |
5392620794 ps |
T730 |
/workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.1345162113 |
|
|
Aug 06 08:45:45 PM PDT 24 |
Aug 06 08:53:54 PM PDT 24 |
3917919684 ps |
T42 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.3005037923 |
|
|
Aug 06 08:29:16 PM PDT 24 |
Aug 06 09:19:00 PM PDT 24 |
11523033756 ps |
T181 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.4153234654 |
|
|
Aug 06 08:38:30 PM PDT 24 |
Aug 06 08:43:02 PM PDT 24 |
3450771902 ps |
T265 |
/workspace/coverage/default/2.chip_sw_i2c_device_tx_rx.728052810 |
|
|
Aug 06 08:25:16 PM PDT 24 |
Aug 06 08:33:35 PM PDT 24 |
4617556818 ps |
T266 |
/workspace/coverage/default/6.chip_sw_uart_rand_baudrate.580988280 |
|
|
Aug 06 08:41:56 PM PDT 24 |
Aug 06 09:27:41 PM PDT 24 |
13625020400 ps |
T118 |
/workspace/coverage/default/1.rom_volatile_raw_unlock.207685113 |
|
|
Aug 06 08:24:04 PM PDT 24 |
Aug 06 08:26:15 PM PDT 24 |
2356123655 ps |
T267 |
/workspace/coverage/default/79.chip_sw_all_escalation_resets.3215391560 |
|
|
Aug 06 08:46:28 PM PDT 24 |
Aug 06 08:57:51 PM PDT 24 |
4979025638 ps |
T268 |
/workspace/coverage/default/0.chip_sw_aon_timer_smoketest.2081275045 |
|
|
Aug 06 08:22:53 PM PDT 24 |
Aug 06 08:27:31 PM PDT 24 |
3139966150 ps |
T269 |
/workspace/coverage/default/1.chip_sw_kmac_smoketest.3176884496 |
|
|
Aug 06 08:25:04 PM PDT 24 |
Aug 06 08:31:57 PM PDT 24 |
3325428530 ps |
T270 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.2723771857 |
|
|
Aug 06 08:25:08 PM PDT 24 |
Aug 06 08:42:28 PM PDT 24 |
8293365160 ps |
T271 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_power_glitch_reset.957610917 |
|
|
Aug 06 08:27:00 PM PDT 24 |
Aug 06 08:36:36 PM PDT 24 |
5242430822 ps |
T272 |
/workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_invalid_meas.1374496367 |
|
|
Aug 06 08:34:47 PM PDT 24 |
Aug 06 09:39:49 PM PDT 24 |
15284414520 ps |
T122 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.4164563841 |
|
|
Aug 06 08:22:16 PM PDT 24 |
Aug 06 08:34:20 PM PDT 24 |
4022184694 ps |
T362 |
/workspace/coverage/default/30.chip_sw_all_escalation_resets.909011454 |
|
|
Aug 06 08:42:38 PM PDT 24 |
Aug 06 08:53:30 PM PDT 24 |
5037803654 ps |
T342 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_ops.468312667 |
|
|
Aug 06 08:23:25 PM PDT 24 |
Aug 06 08:35:15 PM PDT 24 |
4489474196 ps |
T729 |
/workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.2214800277 |
|
|
Aug 06 08:45:01 PM PDT 24 |
Aug 06 08:51:42 PM PDT 24 |
3622151902 ps |
T165 |
/workspace/coverage/default/2.rom_volatile_raw_unlock.2110433507 |
|
|
Aug 06 08:39:14 PM PDT 24 |
Aug 06 08:40:59 PM PDT 24 |
1954403113 ps |
T938 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.3038599218 |
|
|
Aug 06 08:20:23 PM PDT 24 |
Aug 06 08:26:50 PM PDT 24 |
5352153640 ps |
T172 |
/workspace/coverage/default/0.chip_sw_flash_rma_unlocked.2193817987 |
|
|
Aug 06 08:22:15 PM PDT 24 |
Aug 06 09:49:42 PM PDT 24 |
44175876648 ps |
T218 |
/workspace/coverage/default/67.chip_sw_all_escalation_resets.4266875552 |
|
|
Aug 06 08:53:14 PM PDT 24 |
Aug 06 09:06:18 PM PDT 24 |
5682470750 ps |
T939 |
/workspace/coverage/default/1.chip_sw_example_manufacturer.2554457788 |
|
|
Aug 06 08:27:11 PM PDT 24 |
Aug 06 08:30:13 PM PDT 24 |
3171944280 ps |
T552 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_smoketest.3782290049 |
|
|
Aug 06 08:24:36 PM PDT 24 |
Aug 06 08:30:24 PM PDT 24 |
3411606810 ps |
T343 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.2420651486 |
|
|
Aug 06 08:26:25 PM PDT 24 |
Aug 06 08:37:01 PM PDT 24 |
4935693900 ps |
T940 |
/workspace/coverage/default/2.rom_e2e_smoke.390125613 |
|
|
Aug 06 08:43:20 PM PDT 24 |
Aug 06 09:53:35 PM PDT 24 |
15403035430 ps |
T775 |
/workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.994281244 |
|
|
Aug 06 08:43:53 PM PDT 24 |
Aug 06 08:50:24 PM PDT 24 |
4346313438 ps |
T344 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.3476054966 |
|
|
Aug 06 08:26:44 PM PDT 24 |
Aug 06 08:38:38 PM PDT 24 |
4143811954 ps |
T941 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx.1039316670 |
|
|
Aug 06 08:25:40 PM PDT 24 |
Aug 06 08:36:16 PM PDT 24 |
4200355784 ps |
T18 |
/workspace/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.2416186954 |
|
|
Aug 06 08:42:01 PM PDT 24 |
Aug 06 08:48:40 PM PDT 24 |
5091611450 ps |
T942 |
/workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.4049469298 |
|
|
Aug 06 08:27:39 PM PDT 24 |
Aug 06 08:32:11 PM PDT 24 |
3172352319 ps |
T943 |
/workspace/coverage/default/0.chip_sw_rstmgr_smoketest.2982759469 |
|
|
Aug 06 08:22:17 PM PDT 24 |
Aug 06 08:26:06 PM PDT 24 |
2254392882 ps |
T119 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.887997156 |
|
|
Aug 06 08:24:40 PM PDT 24 |
Aug 06 08:27:19 PM PDT 24 |
2956837078 ps |
T735 |
/workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.1852088991 |
|
|
Aug 06 08:44:32 PM PDT 24 |
Aug 06 08:50:09 PM PDT 24 |
3439831554 ps |
T321 |
/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.4074973427 |
|
|
Aug 06 08:27:12 PM PDT 24 |
Aug 06 08:42:46 PM PDT 24 |
5003580088 ps |
T60 |
/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.676418092 |
|
|
Aug 06 08:38:42 PM PDT 24 |
Aug 06 09:02:38 PM PDT 24 |
22189983266 ps |
T944 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_mem_protection.2405005252 |
|
|
Aug 06 08:20:51 PM PDT 24 |
Aug 06 08:40:27 PM PDT 24 |
5903252236 ps |
T301 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.2419501081 |
|
|
Aug 06 08:25:41 PM PDT 24 |
Aug 06 08:32:41 PM PDT 24 |
5351396464 ps |
T396 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_peri.2373725765 |
|
|
Aug 06 08:23:24 PM PDT 24 |
Aug 06 08:50:06 PM PDT 24 |
12312961912 ps |
T406 |
/workspace/coverage/default/75.chip_sw_all_escalation_resets.2950133038 |
|
|
Aug 06 08:47:07 PM PDT 24 |
Aug 06 08:56:57 PM PDT 24 |
5036049016 ps |
T235 |
/workspace/coverage/default/5.chip_sw_csrng_edn_concurrency.346941422 |
|
|
Aug 06 08:42:21 PM PDT 24 |
Aug 06 10:25:31 PM PDT 24 |
25210543856 ps |
T945 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_dai_lock.1174353351 |
|
|
Aug 06 08:24:56 PM PDT 24 |
Aug 06 09:58:00 PM PDT 24 |
28481979642 ps |
T456 |
/workspace/coverage/default/2.chip_sw_flash_crash_alert.4175162800 |
|
|
Aug 06 08:38:37 PM PDT 24 |
Aug 06 08:49:12 PM PDT 24 |
4302649248 ps |
T946 |
/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1288545793 |
|
|
Aug 06 08:28:35 PM PDT 24 |
Aug 06 08:37:57 PM PDT 24 |
7672524108 ps |
T353 |
/workspace/coverage/default/29.chip_sw_all_escalation_resets.3200841646 |
|
|
Aug 06 08:43:17 PM PDT 24 |
Aug 06 08:55:36 PM PDT 24 |
4873802010 ps |
T947 |
/workspace/coverage/default/1.chip_sw_hmac_multistream.1863751096 |
|
|
Aug 06 08:27:34 PM PDT 24 |
Aug 06 08:59:14 PM PDT 24 |
7950264858 ps |
T948 |
/workspace/coverage/default/2.chip_sw_aes_entropy.75176511 |
|
|
Aug 06 08:33:37 PM PDT 24 |
Aug 06 08:37:46 PM PDT 24 |
2390589944 ps |
T173 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.3514394905 |
|
|
Aug 06 08:23:15 PM PDT 24 |
Aug 06 10:08:42 PM PDT 24 |
49628965980 ps |
T10 |
/workspace/coverage/default/0.chip_sw_spi_device_pass_through.1936104385 |
|
|
Aug 06 08:24:47 PM PDT 24 |
Aug 06 08:35:05 PM PDT 24 |
6653804849 ps |
T949 |
/workspace/coverage/default/19.chip_sw_uart_rand_baudrate.4172470495 |
|
|
Aug 06 08:42:32 PM PDT 24 |
Aug 06 09:18:46 PM PDT 24 |
9034384880 ps |
T174 |
/workspace/coverage/default/1.chip_sw_flash_init.2281905008 |
|
|
Aug 06 08:24:37 PM PDT 24 |
Aug 06 09:00:03 PM PDT 24 |
24263674325 ps |
T69 |
/workspace/coverage/default/0.chip_tap_straps_rma.916975438 |
|
|
Aug 06 08:25:05 PM PDT 24 |
Aug 06 08:29:50 PM PDT 24 |
3944922806 ps |
T153 |
/workspace/coverage/default/1.chip_plic_all_irqs_10.165170969 |
|
|
Aug 06 08:25:52 PM PDT 24 |
Aug 06 08:37:06 PM PDT 24 |
4209052480 ps |
T390 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.2350391535 |
|
|
Aug 06 08:26:40 PM PDT 24 |
Aug 06 10:12:22 PM PDT 24 |
24937043072 ps |
T59 |
/workspace/coverage/default/2.chip_sw_sleep_pin_wake.3034942908 |
|
|
Aug 06 08:32:27 PM PDT 24 |
Aug 06 08:40:56 PM PDT 24 |
7094462952 ps |
T187 |
/workspace/coverage/default/2.chip_sw_flash_rma_unlocked.3188966742 |
|
|
Aug 06 08:22:50 PM PDT 24 |
Aug 06 09:50:25 PM PDT 24 |
44991303760 ps |
T154 |
/workspace/coverage/default/0.chip_plic_all_irqs_10.1427948473 |
|
|
Aug 06 08:22:56 PM PDT 24 |
Aug 06 08:32:25 PM PDT 24 |
3225975760 ps |
T132 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.2867945797 |
|
|
Aug 06 08:23:24 PM PDT 24 |
Aug 06 08:31:39 PM PDT 24 |
6649723470 ps |
T770 |
/workspace/coverage/default/70.chip_sw_all_escalation_resets.1811781957 |
|
|
Aug 06 08:46:45 PM PDT 24 |
Aug 06 08:57:09 PM PDT 24 |
5253068364 ps |
T950 |
/workspace/coverage/default/0.chip_sw_entropy_src_ast_rng_req.173273080 |
|
|
Aug 06 08:24:20 PM PDT 24 |
Aug 06 08:27:58 PM PDT 24 |
2410259792 ps |
T450 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_smoketest.1115908195 |
|
|
Aug 06 08:28:49 PM PDT 24 |
Aug 06 08:32:57 PM PDT 24 |
2707820634 ps |
T237 |
/workspace/coverage/default/0.chip_sw_rstmgr_cpu_info.4188235422 |
|
|
Aug 06 08:25:39 PM PDT 24 |
Aug 06 08:37:42 PM PDT 24 |
5471792870 ps |
T789 |
/workspace/coverage/default/93.chip_sw_all_escalation_resets.2655307007 |
|
|
Aug 06 08:46:51 PM PDT 24 |
Aug 06 08:55:28 PM PDT 24 |
4421330500 ps |
T951 |
/workspace/coverage/default/1.chip_sw_aes_enc_jitter_en.1233874303 |
|
|
Aug 06 08:23:32 PM PDT 24 |
Aug 06 08:27:51 PM PDT 24 |
3390335384 ps |
T229 |
/workspace/coverage/default/1.chip_sw_plic_sw_irq.3690730138 |
|
|
Aug 06 08:26:20 PM PDT 24 |
Aug 06 08:31:49 PM PDT 24 |
3522218374 ps |
T952 |
/workspace/coverage/default/1.chip_sw_aon_timer_smoketest.4233832817 |
|
|
Aug 06 08:29:36 PM PDT 24 |
Aug 06 08:33:46 PM PDT 24 |
3030034008 ps |
T113 |
/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.3686048344 |
|
|
Aug 06 08:33:07 PM PDT 24 |
Aug 06 09:42:09 PM PDT 24 |
18806300869 ps |
T712 |
/workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.3118244545 |
|
|
Aug 06 08:43:36 PM PDT 24 |
Aug 06 08:49:41 PM PDT 24 |
4417068620 ps |
T953 |
/workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_no_meas.1445922898 |
|
|
Aug 06 08:43:42 PM PDT 24 |
Aug 06 09:43:36 PM PDT 24 |
15148317802 ps |
T123 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.937116881 |
|
|
Aug 06 08:24:25 PM PDT 24 |
Aug 06 08:35:20 PM PDT 24 |
3662108280 ps |
T116 |
/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en.1099350520 |
|
|
Aug 06 08:35:13 PM PDT 24 |
Aug 06 09:05:57 PM PDT 24 |
9016228870 ps |
T769 |
/workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.3793124626 |
|
|
Aug 06 08:45:00 PM PDT 24 |
Aug 06 08:53:10 PM PDT 24 |
4040998600 ps |
T954 |
/workspace/coverage/default/2.chip_sw_flash_scrambling_smoketest.1179987255 |
|
|
Aug 06 08:41:28 PM PDT 24 |
Aug 06 08:45:54 PM PDT 24 |
3276636900 ps |
T124 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.2593208143 |
|
|
Aug 06 08:23:51 PM PDT 24 |
Aug 06 08:36:43 PM PDT 24 |
4435013360 ps |
T328 |
/workspace/coverage/default/5.chip_sw_uart_rand_baudrate.3177335610 |
|
|
Aug 06 08:42:00 PM PDT 24 |
Aug 06 08:51:45 PM PDT 24 |
4927294352 ps |
T955 |
/workspace/coverage/default/0.chip_sw_aes_entropy.3090768908 |
|
|
Aug 06 08:26:20 PM PDT 24 |
Aug 06 08:31:19 PM PDT 24 |
2697291056 ps |
T727 |
/workspace/coverage/default/26.chip_sw_all_escalation_resets.3037791985 |
|
|
Aug 06 08:45:50 PM PDT 24 |
Aug 06 08:59:05 PM PDT 24 |
4568438964 ps |
T956 |
/workspace/coverage/default/1.chip_sw_aes_idle.1155758124 |
|
|
Aug 06 08:19:42 PM PDT 24 |
Aug 06 08:23:08 PM PDT 24 |
2798908340 ps |
T957 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_write_clear.2411034672 |
|
|
Aug 06 08:26:36 PM PDT 24 |
Aug 06 08:32:30 PM PDT 24 |
2854264664 ps |
T182 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.3370348338 |
|
|
Aug 06 08:23:09 PM PDT 24 |
Aug 06 08:39:04 PM PDT 24 |
8971710498 ps |
T366 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_ops.2395211140 |
|
|
Aug 06 08:26:48 PM PDT 24 |
Aug 06 08:38:33 PM PDT 24 |
3568573220 ps |
T238 |
/workspace/coverage/default/45.chip_sw_all_escalation_resets.860435786 |
|
|
Aug 06 08:51:35 PM PDT 24 |
Aug 06 09:00:46 PM PDT 24 |
4750467852 ps |
T748 |
/workspace/coverage/default/1.chip_sw_sleep_pwm_pulses.2017314981 |
|
|
Aug 06 08:19:26 PM PDT 24 |
Aug 06 08:34:09 PM PDT 24 |
9402051928 ps |
T334 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx2.682290594 |
|
|
Aug 06 08:24:05 PM PDT 24 |
Aug 06 08:32:20 PM PDT 24 |
4395816126 ps |
T333 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.2762918583 |
|
|
Aug 06 08:40:22 PM PDT 24 |
Aug 06 08:54:53 PM PDT 24 |
4403959832 ps |
T958 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_hmac_trans.3525281537 |
|
|
Aug 06 08:23:52 PM PDT 24 |
Aug 06 08:31:30 PM PDT 24 |
4875261560 ps |
T959 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.2781707624 |
|
|
Aug 06 08:23:29 PM PDT 24 |
Aug 06 08:32:24 PM PDT 24 |
5821063744 ps |
T157 |
/workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.3423125783 |
|
|
Aug 06 08:41:54 PM PDT 24 |
Aug 06 08:49:05 PM PDT 24 |
4349552516 ps |
T302 |
/workspace/coverage/default/8.chip_sw_lc_ctrl_transition.3751151116 |
|
|
Aug 06 08:40:53 PM PDT 24 |
Aug 06 08:50:49 PM PDT 24 |
6614951804 ps |
T52 |
/workspace/coverage/default/2.chip_sw_spi_device_pinmux_sleep_retention.2291341449 |
|
|
Aug 06 08:28:15 PM PDT 24 |
Aug 06 08:33:23 PM PDT 24 |
3173468687 ps |
T117 |
/workspace/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.11306690 |
|
|
Aug 06 08:24:29 PM PDT 24 |
Aug 06 08:48:52 PM PDT 24 |
7555415769 ps |
T413 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.270465390 |
|
|
Aug 06 08:26:52 PM PDT 24 |
Aug 06 09:18:45 PM PDT 24 |
12016977200 ps |
T11 |
/workspace/coverage/default/0.chip_sw_spi_host_tx_rx.2893779472 |
|
|
Aug 06 08:21:27 PM PDT 24 |
Aug 06 08:27:30 PM PDT 24 |
3067706856 ps |
T414 |
/workspace/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.2913982902 |
|
|
Aug 06 08:23:29 PM PDT 24 |
Aug 06 08:36:26 PM PDT 24 |
6352046608 ps |
T415 |
/workspace/coverage/default/1.chip_sw_kmac_entropy.1506740365 |
|
|
Aug 06 08:22:51 PM PDT 24 |
Aug 06 08:26:58 PM PDT 24 |
2628306968 ps |
T416 |
/workspace/coverage/default/11.chip_sw_uart_rand_baudrate.3081965505 |
|
|
Aug 06 08:41:35 PM PDT 24 |
Aug 06 08:53:41 PM PDT 24 |
4014302920 ps |
T417 |
/workspace/coverage/default/0.rom_e2e_smoke.2556241995 |
|
|
Aug 06 08:28:19 PM PDT 24 |
Aug 06 09:29:49 PM PDT 24 |
15547870600 ps |
T354 |
/workspace/coverage/default/87.chip_sw_all_escalation_resets.94104492 |
|
|
Aug 06 08:46:46 PM PDT 24 |
Aug 06 08:55:30 PM PDT 24 |
4701091486 ps |
T418 |
/workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.3210209975 |
|
|
Aug 06 08:48:05 PM PDT 24 |
Aug 06 08:54:59 PM PDT 24 |
3940006862 ps |
T370 |
/workspace/coverage/default/3.chip_tap_straps_prod.3931366151 |
|
|
Aug 06 08:40:04 PM PDT 24 |
Aug 06 08:42:19 PM PDT 24 |
3145154977 ps |
T185 |
/workspace/coverage/default/1.chip_sw_csrng_fuse_en_sw_app_read_test.1225722118 |
|
|
Aug 06 08:26:56 PM PDT 24 |
Aug 06 08:37:09 PM PDT 24 |
5530425160 ps |
T960 |
/workspace/coverage/default/0.chip_sw_entropy_src_smoketest.3625137282 |
|
|
Aug 06 08:24:20 PM PDT 24 |
Aug 06 08:35:09 PM PDT 24 |
4369721992 ps |
T961 |
/workspace/coverage/default/2.chip_sw_csrng_smoketest.175700657 |
|
|
Aug 06 08:41:31 PM PDT 24 |
Aug 06 08:45:26 PM PDT 24 |
2949409704 ps |
T962 |
/workspace/coverage/default/0.chip_sw_rv_timer_smoketest.623749274 |
|
|
Aug 06 08:19:40 PM PDT 24 |
Aug 06 08:23:11 PM PDT 24 |
3233345116 ps |
T963 |
/workspace/coverage/default/2.chip_sw_aon_timer_irq.3188464772 |
|
|
Aug 06 08:32:27 PM PDT 24 |
Aug 06 08:38:36 PM PDT 24 |
4134191696 ps |
T8 |
/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.2344124600 |
|
|
Aug 06 08:27:31 PM PDT 24 |
Aug 06 08:33:19 PM PDT 24 |
3027533520 ps |
T387 |
/workspace/coverage/default/2.chip_sw_rstmgr_sw_rst.3893070529 |
|
|
Aug 06 08:25:11 PM PDT 24 |
Aug 06 08:28:33 PM PDT 24 |
2501706120 ps |
T964 |
/workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_meas.4261996107 |
|
|
Aug 06 08:27:08 PM PDT 24 |
Aug 06 09:37:50 PM PDT 24 |
14824797208 ps |
T345 |
/workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en.866910678 |
|
|
Aug 06 08:40:24 PM PDT 24 |
Aug 06 08:46:00 PM PDT 24 |
2727581987 ps |
T293 |
/workspace/coverage/default/0.chip_sw_flash_init.490742604 |
|
|
Aug 06 08:18:28 PM PDT 24 |
Aug 06 08:59:00 PM PDT 24 |
19890007496 ps |
T965 |
/workspace/coverage/default/18.chip_sw_uart_rand_baudrate.3462608706 |
|
|
Aug 06 08:43:48 PM PDT 24 |
Aug 06 08:53:27 PM PDT 24 |
4281922296 ps |
T177 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.1596317779 |
|
|
Aug 06 08:21:40 PM PDT 24 |
Aug 06 08:24:33 PM PDT 24 |
3358300630 ps |
T451 |
/workspace/coverage/default/2.chip_sw_sram_ctrl_smoketest.2863395427 |
|
|
Aug 06 08:39:54 PM PDT 24 |
Aug 06 08:42:53 PM PDT 24 |
2456049200 ps |
T732 |
/workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.3723439987 |
|
|
Aug 06 08:41:52 PM PDT 24 |
Aug 06 08:47:34 PM PDT 24 |
3504206024 ps |
T206 |
/workspace/coverage/default/2.chip_sw_inject_scramble_seed.3583083943 |
|
|
Aug 06 08:25:14 PM PDT 24 |
Aug 06 11:29:07 PM PDT 24 |
66003267989 ps |
T966 |
/workspace/coverage/default/1.chip_sw_clkmgr_sleep_frequency.2677202043 |
|
|
Aug 06 08:28:29 PM PDT 24 |
Aug 06 08:40:24 PM PDT 24 |
4375027368 ps |
T967 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_clock_freqs.157183088 |
|
|
Aug 06 08:29:42 PM PDT 24 |
Aug 06 08:50:19 PM PDT 24 |
6257126416 ps |
T968 |
/workspace/coverage/default/0.chip_sw_aes_enc.2233511012 |
|
|
Aug 06 08:26:28 PM PDT 24 |
Aug 06 08:31:50 PM PDT 24 |
2395087834 ps |
T278 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_dev.114428673 |
|
|
Aug 06 08:26:21 PM PDT 24 |
Aug 06 08:54:44 PM PDT 24 |
9092644262 ps |
T355 |
/workspace/coverage/default/27.chip_sw_all_escalation_resets.2363412973 |
|
|
Aug 06 08:44:47 PM PDT 24 |
Aug 06 08:55:03 PM PDT 24 |
5931195000 ps |
T969 |
/workspace/coverage/default/2.rom_e2e_static_critical.2864328182 |
|
|
Aug 06 08:45:42 PM PDT 24 |
Aug 06 09:47:33 PM PDT 24 |
17033206280 ps |
T970 |
/workspace/coverage/default/1.chip_sw_clkmgr_jitter_frequency.1398478488 |
|
|
Aug 06 08:23:19 PM PDT 24 |
Aug 06 08:29:48 PM PDT 24 |
2567529454 ps |
T971 |
/workspace/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.287733577 |
|
|
Aug 06 08:26:40 PM PDT 24 |
Aug 06 08:33:36 PM PDT 24 |
7907310672 ps |
T972 |
/workspace/coverage/default/1.rom_e2e_asm_init_rma.1065179034 |
|
|
Aug 06 08:31:50 PM PDT 24 |
Aug 06 09:49:37 PM PDT 24 |
15154060132 ps |
T223 |
/workspace/coverage/default/0.chip_sw_alert_handler_escalation.903458363 |
|
|
Aug 06 08:26:40 PM PDT 24 |
Aug 06 08:36:38 PM PDT 24 |
4344569692 ps |
T973 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_mem_protection.904143306 |
|
|
Aug 06 08:25:56 PM PDT 24 |
Aug 06 08:43:57 PM PDT 24 |
5510807160 ps |
T974 |
/workspace/coverage/default/0.chip_sw_pwrmgr_smoketest.3934432561 |
|
|
Aug 06 08:28:06 PM PDT 24 |
Aug 06 08:37:33 PM PDT 24 |
6673147384 ps |
T391 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.1548176664 |
|
|
Aug 06 08:33:06 PM PDT 24 |
Aug 06 10:31:27 PM PDT 24 |
24560839704 ps |
T824 |
/workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.3381494484 |
|
|
Aug 06 08:47:41 PM PDT 24 |
Aug 06 08:54:24 PM PDT 24 |
3513550224 ps |
T244 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.1814491430 |
|
|
Aug 06 08:27:43 PM PDT 24 |
Aug 06 09:36:13 PM PDT 24 |
14855750950 ps |
T150 |
/workspace/coverage/default/2.chip_sw_exit_test_unlocked_bootstrap.815034275 |
|
|
Aug 06 08:25:56 PM PDT 24 |
Aug 06 11:38:53 PM PDT 24 |
57740161270 ps |
T21 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.3915438369 |
|
|
Aug 06 08:25:20 PM PDT 24 |
Aug 06 09:21:24 PM PDT 24 |
21101850156 ps |
T975 |
/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_por_reset.2282475686 |
|
|
Aug 06 08:25:15 PM PDT 24 |
Aug 06 08:42:39 PM PDT 24 |
8659207994 ps |
T976 |
/workspace/coverage/default/0.chip_sw_clkmgr_jitter.867558130 |
|
|
Aug 06 08:27:21 PM PDT 24 |
Aug 06 08:31:57 PM PDT 24 |
3416181611 ps |
T216 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.3600893200 |
|
|
Aug 06 08:19:48 PM PDT 24 |
Aug 06 09:19:09 PM PDT 24 |
20366892525 ps |
T209 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_inputs.1244896490 |
|
|
Aug 06 08:33:04 PM PDT 24 |
Aug 06 08:40:21 PM PDT 24 |
3365314441 ps |
T245 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock.2656706651 |
|
|
Aug 06 08:28:46 PM PDT 24 |
Aug 06 08:31:03 PM PDT 24 |
2418476402 ps |
T737 |
/workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.4029387204 |
|
|
Aug 06 08:47:57 PM PDT 24 |
Aug 06 08:55:49 PM PDT 24 |
4416261616 ps |
T210 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_reset.2290465052 |
|
|
Aug 06 08:24:24 PM PDT 24 |
Aug 06 08:56:30 PM PDT 24 |
24745890248 ps |
T977 |
/workspace/coverage/default/3.chip_sw_lc_ctrl_transition.2370204796 |
|
|
Aug 06 08:42:56 PM PDT 24 |
Aug 06 08:52:04 PM PDT 24 |
6432975431 ps |
T733 |
/workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.196381655 |
|
|
Aug 06 08:43:27 PM PDT 24 |
Aug 06 08:51:24 PM PDT 24 |
4128444854 ps |
T459 |
/workspace/coverage/default/2.chip_sw_otbn_smoketest.2290068796 |
|
|
Aug 06 08:39:23 PM PDT 24 |
Aug 06 09:03:15 PM PDT 24 |
7562516594 ps |
T160 |
/workspace/coverage/default/82.chip_sw_all_escalation_resets.1787662061 |
|
|
Aug 06 08:46:47 PM PDT 24 |
Aug 06 08:58:34 PM PDT 24 |
5136439428 ps |
T239 |
/workspace/coverage/default/62.chip_sw_all_escalation_resets.1852391771 |
|
|
Aug 06 08:45:12 PM PDT 24 |
Aug 06 08:56:37 PM PDT 24 |
5732298012 ps |
T178 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.1334001824 |
|
|
Aug 06 08:24:44 PM PDT 24 |
Aug 06 08:38:55 PM PDT 24 |
6103064428 ps |
T978 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.3539777108 |
|
|
Aug 06 08:23:04 PM PDT 24 |
Aug 06 08:35:19 PM PDT 24 |
5095616664 ps |
T364 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.3546172112 |
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|
Aug 06 08:26:00 PM PDT 24 |
Aug 06 08:32:29 PM PDT 24 |
3905625780 ps |