Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	3518	1			T77	1		T227	7		T421	20
all_values[1]	3587	1			T77	2		T227	7		T421	27
all_values[2]	3481	1			T77	3		T227	8		T421	17
all_values[3]	3601	1			T77	1		T227	14		T421	23
all_values[4]	3521	1			T77	1		T227	5		T421	31
all_values[5]	3595	1			T77	1		T227	14		T421	20
all_values[6]	3511	1			T77	1		T227	6		T421	26
all_values[7]	3598	1			T227	6		T421	20		T495	1
all_values[8]	3581	1			T77	4		T227	10		T421	21
all_values[9]	3584	1			T77	1		T227	15		T421	22
all_values[10]	3598	1			T77	1		T227	8		T421	21
all_values[11]	3557	1			T77	5		T227	4		T421	22
all_values[12]	3625	1			T77	1		T227	10		T421	23
all_values[13]	3435	1			T77	2		T227	9		T421	23
all_values[14]	3508	1			T77	1		T227	3		T421	28
all_values[15]	3553	1			T77	2		T227	11		T421	18
all_values[16]	3585	1			T77	4		T227	11		T421	12
all_values[17]	3571	1			T77	2		T227	7		T421	20
all_values[18]	3634	1			T77	2		T227	5		T421	26
all_values[19]	3627	1			T77	1		T227	6		T421	20
all_values[20]	3671	1			T77	1		T227	6		T421	25
all_values[21]	3514	1			T77	3		T227	6		T421	14
all_values[22]	3589	1			T227	15		T421	18		T495	1
all_values[23]	3591	1			T77	1		T227	3		T421	20
all_values[24]	3583	1			T77	3		T227	11		T421	23
all_values[25]	3456	1			T77	1		T227	10		T421	21
all_values[26]	3517	1			T77	2		T227	8		T421	28
all_values[27]	3721	1			T77	1		T227	1		T421	32
all_values[28]	3665	1			T77	4		T227	10		T421	13
all_values[29]	3680	1			T77	1		T227	4		T421	18
all_values[30]	3559	1			T77	3		T227	12		T421	20
all_values[31]	3618	1			T77	3		T227	10		T421	19
all_values[32]	3583	1			T77	1		T227	7		T421	19
all_values[33]	3552	1			T77	2		T227	9		T421	13
all_values[34]	3552	1			T77	2		T227	5		T421	28
all_values[35]	3509	1			T227	6		T421	16		T495	1
all_values[36]	3577	1			T77	2		T227	6		T421	23
all_values[37]	3563	1			T77	2		T227	7		T421	19
all_values[38]	3555	1			T77	4		T227	6		T421	23
all_values[39]	3512	1			T77	1		T227	2		T421	20
all_values[40]	3567	1			T77	4		T227	9		T421	15
all_values[41]	3610	1			T77	5		T227	6		T421	19
all_values[42]	3441	1			T77	2		T227	8		T421	25
all_values[43]	3522	1			T77	1		T227	8		T421	26
all_values[44]	3645	1			T227	8		T421	30		T556	23
all_values[45]	3562	1			T77	2		T227	3		T421	24
all_values[46]	3492	1			T77	2		T227	8		T421	24
all_values[47]	3551	1			T227	8		T421	16		T495	1
all_values[48]	3645	1			T227	12		T421	22		T556	20
all_values[49]	3499	1			T77	4		T227	6		T421	21
all_values[50]	3497	1			T77	1		T227	11		T421	23
all_values[51]	3592	1			T77	6		T227	6		T421	24
all_values[52]	3644	1			T227	9		T421	25		T495	2
all_values[53]	3514	1			T77	4		T227	5		T421	23
all_values[54]	3451	1			T77	1		T227	10		T421	17
all_values[55]	3563	1			T77	2		T227	5		T421	19
all_values[56]	3603	1			T77	2		T227	5		T421	21
all_values[57]	3627	1			T77	1		T227	11		T421	19
all_values[58]	3575	1			T77	2		T227	10		T421	26
all_values[59]	3528	1			T77	1		T227	7		T421	18
all_values[60]	3621	1			T77	2		T227	7		T421	20
all_values[61]	3553	1			T77	1		T227	5		T421	21
all_values[62]	3583	1			T227	6		T421	28		T556	20
all_values[63]	3652	1			T77	1		T227	4		T421	20