Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.gpio_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	149095	1			T81	102		T82	388		T85	77
values[2]	10287	1			T81	3		T82	8		T85	1
values[3]	4092	1			T461	85		T494	102		T470	2
values[4]	2701	1			T461	70		T494	79		T470	1
values[5]	1722	1			T461	71		T494	57		T422	5
values[6]	1166	1			T461	28		T494	23		T422	3
values[7]	854	1			T461	17		T494	26		T422	2
values[8]	696	1			T461	9		T494	19		T422	2
values[9]	507	1			T494	8		T422	8		T546	18
values[10]	532	1			T494	3		T422	4		T546	8
values[11]	416	1			T422	4		T546	4		T874	16
values[12]	358	1			T422	1		T546	7		T874	18
values[13]	377	1			T422	2		T546	11		T874	19
values[14]	391	1			T422	2		T546	23		T874	16
values[15]	311	1			T422	1		T546	26		T874	7
values[16]	274	1			T422	2		T546	12		T874	7
values[17]	322	1			T422	2		T546	8		T874	9
values[18]	336	1			T422	3		T546	11		T874	13
values[19]	341	1			T422	9		T546	7		T874	14
values[20]	378	1			T422	4		T546	9		T874	18
values[21]	339	1			T422	2		T546	8		T874	9
values[22]	330	1			T422	1		T546	7		T874	10
values[23]	363	1			T422	2		T546	7		T874	22
values[24]	328	1			T422	1		T546	8		T874	9
values[25]	320	1			T422	3		T546	8		T874	9
values[26]	371	1			T422	7		T546	11		T874	14
values[27]	388	1			T422	13		T546	7		T874	13
values[28]	322	1			T422	2		T546	6		T874	24
values[29]	303	1			T422	1		T546	9		T874	18
values[30]	320	1			T422	2		T546	12		T874	15
values[31]	320	1			T422	7		T546	5		T874	19
values[32]	320	1			T422	4		T546	8		T874	21
values[33]	381	1			T422	1		T546	4		T874	12
values[34]	352	1			T422	1		T546	7		T874	20
values[35]	316	1			T422	2		T546	5		T874	28
values[36]	334	1			T422	2		T546	4		T874	15
values[37]	307	1			T422	2		T546	7		T874	11
values[38]	313	1			T422	1		T546	5		T874	9
values[39]	322	1			T422	2		T546	7		T874	15
values[40]	276	1			T422	4		T546	7		T874	4
values[41]	287	1			T422	2		T546	8		T874	5
values[42]	311	1			T422	9		T546	5		T874	6
values[43]	315	1			T422	2		T546	7		T874	12
values[44]	352	1			T422	5		T546	3		T874	5
values[45]	344	1			T422	5		T546	8		T874	13
values[46]	300	1			T422	2		T546	5		T874	7
values[47]	311	1			T422	7		T546	8		T874	4
values[48]	293	1			T422	1		T546	5		T874	8
values[49]	309	1			T422	3		T546	8		T874	9
values[50]	275	1			T422	1		T546	7		T874	4
values[51]	252	1			T422	1		T546	5		T874	8
values[52]	283	1			T422	3		T546	5		T874	14
values[53]	270	1			T422	6		T546	5		T874	21
values[54]	234	1			T422	3		T546	9		T874	5
values[55]	210	1			T422	1		T546	11		T874	2
values[56]	233	1			T422	1		T546	16		T874	3
values[57]	243	1			T422	6		T546	13		T481	1
values[58]	225	1			T422	2		T546	9		T481	1
values[59]	199	1			T422	2		T546	5		T481	1
values[60]	210	1			T422	1		T546	8		T481	1
values[61]	194	1			T422	2		T546	12		T481	1
values[62]	160	1			T422	2		T546	14		T481	1
values[63]	175	1			T422	6		T546	7		T481	1
values[64]	197	1			T422	4		T546	2		T481	1
values[65]	257	1			T422	2		T546	3		T481	1
values[66]	238	1			T422	1		T546	8		T481	1
values[67]	231	1			T422	1		T546	5		T481	1
values[68]	232	1			T422	2		T546	7		T481	1
values[69]	186	1			T422	2		T546	10		T481	1
values[70]	195	1			T422	2		T546	11		T481	1
values[71]	182	1			T422	5		T546	16		T481	1
values[72]	186	1			T422	5		T546	11		T481	1
values[73]	165	1			T422	5		T546	8		T481	1
values[74]	145	1			T422	5		T546	7		T481	1
values[75]	128	1			T422	5		T546	12		T481	1
values[76]	123	1			T422	3		T546	12		T481	1
values[77]	142	1			T422	2		T546	16		T481	1
values[78]	144	1			T422	5		T546	19		T481	2
values[79]	156	1			T422	2		T546	19		T481	1
values[80]	131	1			T422	1		T546	17		T481	1
values[81]	114	1			T422	1		T546	15		T481	1
values[82]	106	1			T422	1		T546	7		T481	1
values[83]	108	1			T422	3		T546	10		T481	1
values[84]	111	1			T422	5		T546	13		T481	1
values[85]	128	1			T422	5		T546	21		T481	1
values[86]	124	1			T422	3		T546	13		T481	1
values[87]	98	1			T422	9		T546	11		T481	1
values[88]	89	1			T422	5		T546	5		T481	1
values[89]	80	1			T422	3		T546	1		T481	1
values[90]	72	1			T422	3		T546	1		T481	1
values[91]	91	1			T422	3		T546	2		T481	1
values[92]	83	1			T422	4		T546	3		T481	1
values[93]	88	1			T422	2		T546	5		T481	1
values[94]	80	1			T422	3		T546	1		T481	1
values[95]	75	1			T422	6		T546	2		T481	1
values[96]	76	1			T422	1		T546	2		T481	1
values[97]	90	1			T422	3		T546	5		T481	1
values[98]	94	1			T422	4		T546	3		T481	1
values[99]	88	1			T422	4		T546	6		T481	1
values[100]	92	1			T422	10		T546	12		T481	2
values[101]	87	1			T422	6		T546	11		T481	5
values[102]	85	1			T422	6		T546	8		T481	1
values[103]	86	1			T422	3		T546	3		T481	1
values[104]	81	1			T422	2		T546	2		T481	1
values[105]	83	1			T422	2		T546	2		T481	2
values[106]	55	1			T422	2		T546	1		T481	1
values[107]	60	1			T422	1		T546	1		T481	5
values[108]	61	1			T422	2		T546	3		T481	5
values[109]	56	1			T422	3		T546	1		T481	2
values[110]	59	1			T422	6		T546	1		T481	1
values[111]	65	1			T422	3		T546	3		T481	1
values[112]	75	1			T422	3		T546	4		T481	2
values[113]	62	1			T422	2		T546	2		T481	1
values[114]	63	1			T422	5		T546	1		T481	1
values[115]	54	1			T422	5		T546	3		T481	2
values[116]	66	1			T422	1		T546	1		T481	3
values[117]	74	1			T422	1		T546	2		T481	1
values[118]	63	1			T422	4		T546	1		T481	1
values[119]	63	1			T422	3		T546	5		T481	3
values[120]	51	1			T422	4		T546	3		T481	2
values[121]	65	1			T422	3		T546	4		T481	2
values[122]	59	1			T422	1		T546	4		T481	3
values[123]	62	1			T422	3		T546	3		T481	1
values[124]	82	1			T422	5		T546	9		T481	3
values[125]	72	1			T422	1		T546	21		T481	1
values[126]	117	1			T422	2		T546	27		T481	1
values[127]	798	1			T546	51		T481	37		T881	33
values[128]	7238	1			T546	32		T481	335		T881	417