Total Coverage Summary 

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.03	95.50	93.78	95.28		94.53	97.53	99.55

Total tests in report: 2934

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Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
38.96	38.96	45.69	45.69	44.87	44.87	25.33	25.33			58.75	58.75	58.92	58.92	0.19	0.19	/workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.3550888756
50.35	11.40	56.54	10.86	59.66	14.79	30.90	5.57			69.67	10.92	84.09	25.17	1.26	1.07	/workspace/coverage/cover_reg_top/15.chip_csr_rw.1988797229
56.85	6.49	62.91	6.37	62.06	2.40	32.97	2.06			69.74	0.07	84.09	0.00	29.33	28.07	/workspace/coverage/cover_reg_top/79.xbar_stress_all_with_rand_reset.2856419170
63.29	6.44	75.01	12.10	70.44	8.38	39.51	6.54			80.65	10.90	84.44	0.35	29.68	0.35	/workspace/coverage/default/2.chip_jtag_csr_rw.284781311
66.84	3.55	75.01	0.00	70.60	0.17	39.51	0.00			80.65	0.00	84.44	0.00	50.82	21.14	/workspace/coverage/cover_reg_top/38.xbar_access_same_device_slow_rsp.4294381634
70.24	3.40	77.89	2.89	72.23	1.62	50.34	10.83			81.70	1.05	88.46	4.02	50.82	0.00	/workspace/coverage/default/1.chip_sw_power_virus.2368530446
73.18	2.94	77.89	0.00	72.23	0.01	67.79	17.45			81.70	0.01	88.64	0.17	50.83	0.01	/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.3047260654
75.63	2.45	82.50	4.61	76.02	3.79	70.92	3.13			83.32	1.61	90.21	1.57	50.83	0.00	/workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.1866522709
77.66	2.02	82.50	0.00	76.02	0.00	70.92	0.00			83.32	0.00	90.21	0.00	62.97	12.14	/workspace/coverage/cover_reg_top/84.xbar_access_same_device_slow_rsp.420694511
79.52	1.86	82.50	0.00	76.18	0.16	70.92	0.00			83.35	0.03	90.21	0.00	73.94	10.97	/workspace/coverage/cover_reg_top/71.xbar_access_same_device_slow_rsp.1894760103
80.99	1.47	82.65	0.15	76.29	0.11	79.15	8.23			83.52	0.17	90.38	0.17	73.94	0.00	/workspace/coverage/default/1.chip_sw_lc_walkthrough_dev.1210041914
82.33	1.34	85.75	3.10	78.34	2.05	79.63	0.48			85.91	2.39	90.38	0.00	73.94	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_0.1796495661
83.55	1.22	87.32	1.57	79.40	1.06	82.10	2.46			87.22	1.31	90.73	0.35	74.50	0.56	/workspace/coverage/default/2.chip_sw_rstmgr_alert_info.1900303772
84.69	1.14	88.70	1.38	82.13	2.72	82.33	0.24			89.73	2.51	90.73	0.00	74.50	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.1545278496
85.76	1.07	88.70	0.01	82.52	0.39	83.07	0.74			89.76	0.03	90.73	0.00	79.78	5.28	/workspace/coverage/cover_reg_top/25.xbar_stress_all_with_reset_error.1978084708
86.66	0.90	88.70	0.00	82.52	0.00	83.07	0.00			89.76	0.00	90.73	0.00	85.18	5.40	/workspace/coverage/cover_reg_top/91.xbar_access_same_device_slow_rsp.4277302466
87.48	0.82	89.42	0.72	82.68	0.17	83.09	0.01			89.94	0.18	94.58	3.85	85.18	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.2575629997
88.26	0.78	90.28	0.86	83.35	0.66	83.84	0.76			90.74	0.80	96.15	1.57	85.18	0.00	/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.3239905442
88.97	0.72	90.28	0.00	83.35	0.01	83.84	0.00			90.74	0.00	96.15	0.00	89.47	4.29	/workspace/coverage/cover_reg_top/36.xbar_access_same_device.3091137278
89.69	0.72	91.87	1.59	84.46	1.11	84.17	0.32			92.01	1.27	96.15	0.00	89.47	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_20.3987772086
90.27	0.58	91.98	0.11	84.46	0.00	87.20	3.04			92.01	0.00	96.15	0.00	89.81	0.34	/workspace/coverage/default/0.chip_jtag_csr_rw.291715905
90.83	0.56	92.47	0.50	86.37	1.91	87.28	0.07			92.28	0.28	96.15	0.00	90.40	0.59	/workspace/coverage/cover_reg_top/13.chip_csr_mem_rw_with_rand_reset.3526451409
91.14	0.32	92.87	0.40	86.55	0.18	88.33	1.05			92.37	0.09	96.33	0.17	90.40	0.00	/workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_meas.845842105
91.46	0.31	92.88	0.01	88.36	1.81	88.33	0.00			92.37	0.00	96.33	0.00	90.46	0.06	/workspace/coverage/cover_reg_top/21.chip_tl_errors.3034686391
91.76	0.31	92.88	0.00	88.40	0.04	88.33	0.00			92.37	0.00	96.33	0.00	92.27	1.81	/workspace/coverage/cover_reg_top/52.xbar_access_same_device_slow_rsp.710178479
92.04	0.27	92.88	0.00	88.40	0.00	89.27	0.94			92.37	0.00	96.33	0.00	92.97	0.70	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.2605346577
92.29	0.25	93.39	0.51	88.83	0.43	89.38	0.11			92.81	0.44	96.33	0.00	92.97	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_10.3383158656
92.50	0.22	93.39	0.00	88.84	0.01	89.38	0.00			92.81	0.00	96.33	0.00	94.27	1.29	/workspace/coverage/cover_reg_top/21.xbar_stress_all_with_reset_error.1370281227
92.72	0.21	93.76	0.37	89.18	0.34	89.73	0.34			93.04	0.23	96.33	0.00	94.27	0.00	/workspace/coverage/default/1.chip_sw_gpio.2427456150
92.93	0.21	93.76	0.00	89.19	0.01	89.73	0.00			93.04	0.00	96.33	0.00	95.54	1.27	/workspace/coverage/cover_reg_top/20.xbar_random_large_delays.3636110291
93.14	0.21	93.76	0.00	89.19	0.00	89.73	0.00			93.04	0.00	96.33	0.00	96.78	1.25	/workspace/coverage/cover_reg_top/94.xbar_access_same_device_slow_rsp.3418424899
93.32	0.19	93.77	0.01	89.19	0.01	90.84	1.11			93.04	0.00	96.33	0.00	96.78	0.00	/workspace/coverage/default/3.chip_sw_csrng_edn_concurrency.802204123
93.51	0.18	93.77	0.00	89.19	0.01	90.84	0.00			93.04	0.00	96.33	0.00	97.87	1.09	/workspace/coverage/cover_reg_top/43.xbar_stress_all_with_error.3457647890
93.68	0.17	93.88	0.12	90.07	0.87	90.85	0.01			93.05	0.02	96.33	0.00	97.87	0.00	/workspace/coverage/cover_reg_top/3.chip_same_csr_outstanding.1790021926
93.82	0.15	94.09	0.21	90.39	0.32	91.20	0.35			93.05	0.00	96.33	0.00	97.87	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3775861132
93.97	0.14	94.11	0.02	90.79	0.40	91.20	0.01			93.50	0.45	96.33	0.00	97.87	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.3248963779
94.08	0.11	94.17	0.06	90.87	0.09	91.47	0.27			93.57	0.06	96.50	0.17	97.87	0.00	/workspace/coverage/default/3.chip_sw_data_integrity_escalation.2341023581
94.18	0.11	94.17	0.00	91.51	0.63	91.47	0.00			93.57	0.00	96.50	0.00	97.87	0.00	/workspace/coverage/cover_reg_top/15.chip_tl_errors.1275039288
94.28	0.10	94.17	0.00	91.51	0.00	92.06	0.59			93.57	0.00	96.50	0.00	97.87	0.00	/workspace/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.229890263
94.37	0.09	94.17	0.00	91.51	0.00	92.57	0.51			93.57	0.00	96.50	0.00	97.87	0.00	/workspace/coverage/default/0.chip_sw_flash_rma_unlocked.1752272360
94.45	0.08	94.24	0.07	91.74	0.23	92.57	0.00			93.75	0.19	96.50	0.00	97.87	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_retention.3168139230
94.52	0.07	94.24	0.00	91.74	0.00	93.02	0.44			93.75	0.00	96.50	0.00	97.87	0.00	/workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.2119701574
94.59	0.07	94.24	0.00	91.74	0.00	93.43	0.41			93.75	0.00	96.50	0.00	97.87	0.00	/workspace/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.593573309
94.66	0.07	94.24	0.01	91.92	0.18	93.44	0.01			93.96	0.21	96.50	0.00	97.87	0.00	/workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.85584589
94.71	0.05	94.24	0.00	91.95	0.02	93.56	0.12			93.96	0.00	96.50	0.00	98.06	0.19	/workspace/coverage/default/0.chip_sw_alert_test.845592612
94.77	0.05	94.24	0.00	92.00	0.05	93.56	0.00			93.98	0.02	96.50	0.00	98.31	0.25	/workspace/coverage/cover_reg_top/73.xbar_stress_all_with_rand_reset.3711740460
94.81	0.05	94.27	0.03	92.03	0.02	93.57	0.01			94.01	0.03	96.68	0.17	98.32	0.01	/workspace/coverage/default/16.chip_sw_all_escalation_resets.1267382774
94.86	0.05	94.37	0.10	92.08	0.06	93.64	0.07			94.06	0.05	96.68	0.00	98.32	0.00	/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx1.1365978626
94.90	0.04	94.38	0.01	92.10	0.01	93.67	0.03			94.07	0.01	96.85	0.17	98.33	0.01	/workspace/coverage/default/37.chip_sw_all_escalation_resets.2682988632
94.94	0.04	94.38	0.00	92.10	0.00	93.91	0.24			94.07	0.00	96.85	0.00	98.33	0.00	/workspace/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.2881585842
94.98	0.04	94.39	0.01	92.11	0.01	93.91	0.00			94.09	0.02	97.03	0.17	98.34	0.01	/workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.3154402642
95.02	0.04	94.39	0.01	92.21	0.10	93.91	0.00			94.21	0.11	97.03	0.00	98.34	0.00	/workspace/coverage/default/0.chip_sw_spi_device_pinmux_sleep_retention.2741308536
95.05	0.04	94.42	0.03	92.21	0.01	94.09	0.17			94.21	0.00	97.03	0.00	98.36	0.01	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.2778423354
95.09	0.04	94.42	0.01	92.22	0.01	94.09	0.01			94.22	0.01	97.20	0.17	98.37	0.01	/workspace/coverage/default/21.chip_sw_all_escalation_resets.3952548961
95.12	0.04	94.43	0.01	92.24	0.01	94.09	0.00			94.22	0.01	97.38	0.17	98.38	0.01	/workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.2900349765
95.16	0.03	94.43	0.00	92.44	0.20	94.09	0.00			94.22	0.00	97.38	0.00	98.38	0.00	/workspace/coverage/cover_reg_top/7.chip_tl_errors.1032044496
95.19	0.03	94.49	0.06	92.47	0.03	94.17	0.08			94.26	0.03	97.38	0.00	98.38	0.00	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.2684189147
95.22	0.03	94.52	0.03	92.52	0.04	94.24	0.07			94.30	0.04	97.38	0.00	98.38	0.00	/workspace/coverage/default/0.chip_sw_usbdev_pincfg.1399166720
95.25	0.03	94.52	0.00	92.52	0.00	94.24	0.00			94.30	0.00	97.55	0.17	98.38	0.00	/workspace/coverage/default/1.chip_sw_data_integrity_escalation.3778101343
95.28	0.03	94.52	0.00	92.60	0.08	94.24	0.00			94.31	0.02	97.55	0.00	98.44	0.06	/workspace/coverage/cover_reg_top/12.xbar_access_same_device.249544657
95.30	0.03	94.58	0.06	92.63	0.03	94.25	0.01			94.36	0.05	97.55	0.00	98.44	0.00	/workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.1575451213
95.33	0.03	94.58	0.00	92.78	0.15	94.25	0.00			94.36	0.00	97.55	0.00	98.44	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_0.1728635932
95.35	0.02	94.66	0.07	92.78	0.00	94.32	0.07			94.37	0.01	97.55	0.00	98.44	0.00	/workspace/coverage/default/0.chip_tap_straps_testunlock0.4207920842
95.38	0.02	94.72	0.07	92.83	0.05	94.32	0.00			94.39	0.02	97.55	0.00	98.44	0.00	/workspace/coverage/default/2.chip_sw_sleep_pin_wake.1962372455
95.40	0.02	94.72	0.00	92.83	0.00	94.45	0.13			94.39	0.00	97.55	0.00	98.44	0.00	/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.548837843
95.42	0.02	94.79	0.07	92.87	0.05	94.45	0.00			94.41	0.02	97.55	0.00	98.44	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_wake.815633984
95.44	0.02	94.79	0.00	92.97	0.10	94.45	0.00			94.43	0.02	97.55	0.00	98.45	0.01	/workspace/coverage/cover_reg_top/56.xbar_stress_all.4079163845
95.46	0.02	94.80	0.01	92.98	0.01	94.54	0.09			94.43	0.01	97.55	0.00	98.45	0.00	/workspace/coverage/cover_reg_top/2.chip_csr_hw_reset.627896136
95.47	0.01	94.80	0.00	92.99	0.01	94.54	0.00			94.43	0.00	97.55	0.00	98.53	0.08	/workspace/coverage/cover_reg_top/92.xbar_stress_all_with_rand_reset.1982614191
95.49	0.01	94.80	0.00	92.99	0.00	94.63	0.09			94.43	0.00	97.55	0.00	98.53	0.00	/workspace/coverage/default/1.chip_sw_flash_rma_unlocked.1390369357
95.50	0.01	94.80	0.00	93.02	0.04	94.63	0.00			94.45	0.02	97.55	0.00	98.57	0.04	/workspace/coverage/cover_reg_top/39.xbar_access_same_device_slow_rsp.737544581
95.52	0.01	94.83	0.03	93.04	0.02	94.66	0.03			94.46	0.01	97.55	0.00	98.57	0.00	/workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.4179629268
95.53	0.01	94.83	0.00	93.04	0.00	94.74	0.08			94.46	0.00	97.55	0.00	98.57	0.00	/workspace/coverage/default/6.chip_sw_lc_ctrl_transition.777455155
95.54	0.01	94.83	0.00	93.11	0.07	94.74	0.00			94.46	0.00	97.55	0.00	98.57	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_20.1847658734
95.55	0.01	94.83	0.01	93.13	0.02	94.79	0.05			94.46	0.00	97.55	0.00	98.57	0.00	/workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.3108996875
95.56	0.01	94.83	0.00	93.13	0.00	94.79	0.00			94.46	0.00	97.55	0.00	98.63	0.06	/workspace/coverage/cover_reg_top/40.xbar_stress_all_with_reset_error.2267751127
95.57	0.01	94.83	0.00	93.15	0.02	94.82	0.04			94.46	0.00	97.55	0.00	98.63	0.00	/workspace/coverage/default/10.chip_sw_uart_rand_baudrate.369484445
95.58	0.01	94.83	0.00	93.20	0.05	94.82	0.00			94.46	0.00	97.55	0.00	98.64	0.01	/workspace/coverage/cover_reg_top/20.chip_tl_errors.3907909109
95.59	0.01	94.83	0.00	93.20	0.00	94.88	0.05			94.46	0.00	97.55	0.00	98.64	0.00	/workspace/coverage/default/2.chip_sw_flash_init.1048621238
95.60	0.01	94.85	0.02	93.21	0.01	94.89	0.01			94.47	0.02	97.55	0.00	98.64	0.00	/workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.4099091130
95.61	0.01	94.87	0.02	93.21	0.01	94.89	0.01			94.49	0.02	97.55	0.00	98.64	0.00	/workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.3637914602
95.62	0.01	94.89	0.02	93.22	0.01	94.89	0.01			94.51	0.02	97.55	0.00	98.64	0.00	/workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.2727947445
95.62	0.01	94.89	0.00	93.22	0.00	94.93	0.04			94.51	0.00	97.55	0.00	98.64	0.00	/workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.1441458485
95.63	0.01	94.89	0.00	93.26	0.04	94.93	0.00			94.51	0.00	97.55	0.00	98.64	0.00	/workspace/coverage/cover_reg_top/86.xbar_stress_all.4024987505
95.64	0.01	94.89	0.00	93.30	0.04	94.93	0.00			94.51	0.00	97.55	0.00	98.64	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_0.1671807186
95.64	0.01	94.89	0.00	93.35	0.04	94.93	0.00			94.51	0.00	97.55	0.00	98.64	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_10.3444051864
95.65	0.01	94.89	0.00	93.38	0.04	94.94	0.01			94.51	0.00	97.55	0.00	98.64	0.00	/workspace/coverage/default/1.chip_sw_flash_ctrl_ops.3687640704
95.66	0.01	94.89	0.01	93.41	0.02	94.95	0.01			94.51	0.00	97.55	0.00	98.64	0.00	/workspace/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.4043010356
95.66	0.01	94.89	0.00	93.41	0.01	94.95	0.00			94.51	0.00	97.55	0.00	98.67	0.04	/workspace/coverage/cover_reg_top/48.xbar_stress_all_with_reset_error.1081584533
95.67	0.01	94.89	0.00	93.41	0.00	94.98	0.03			94.51	0.00	97.55	0.00	98.68	0.01	/workspace/coverage/default/8.chip_sw_all_escalation_resets.2085103260
95.68	0.01	94.89	0.00	93.45	0.04	94.98	0.00			94.51	0.00	97.55	0.00	98.68	0.00	/workspace/coverage/cover_reg_top/9.chip_tl_errors.206973179
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95.69	0.01	94.89	0.00	93.46	0.01	94.98	0.00			94.51	0.00	97.55	0.00	98.74	0.02	/workspace/coverage/cover_reg_top/15.xbar_stress_all.3751233994
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95.70	0.01	94.89	0.00	93.48	0.03	95.01	0.00			94.51	0.00	97.55	0.00	98.74	0.00	/workspace/coverage/cover_reg_top/7.xbar_stress_all.393823505
95.70	0.01	94.89	0.00	93.48	0.00	95.04	0.03			94.51	0.00	97.55	0.00	98.74	0.00	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.1890169735
95.71	0.01	94.89	0.00	93.49	0.01	95.04	0.00			94.51	0.00	97.55	0.00	98.77	0.02	/workspace/coverage/cover_reg_top/78.xbar_stress_all_with_reset_error.3717555603
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95.73	0.01	94.90	0.00	93.57	0.01	95.09	0.01			94.51	0.00	97.55	0.00	98.78	0.01	/workspace/coverage/default/60.chip_sw_all_escalation_resets.783259834
95.74	0.01	94.90	0.01	93.57	0.00	95.11	0.02			94.51	0.00	97.55	0.00	98.78	0.00	/workspace/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.4050945279
95.74	0.01	94.90	0.00	93.58	0.01	95.12	0.01			94.51	0.00	97.55	0.00	98.78	0.00	/workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.2259063945
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95.75	0.01	94.90	0.00	93.58	0.00	95.16	0.02			94.51	0.00	97.55	0.00	98.78	0.00	/workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.3905211962
95.75	0.01	94.90	0.00	93.58	0.00	95.18	0.02			94.51	0.00	97.55	0.00	98.78	0.00	/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.1918304654
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95.76	0.01	94.90	0.00	93.61	0.01	95.18	0.00			94.51	0.00	97.55	0.00	98.79	0.00	/workspace/coverage/cover_reg_top/49.xbar_stress_all_with_rand_reset.1621077688
95.76	0.01	94.90	0.00	93.63	0.01	95.18	0.00			94.51	0.00	97.55	0.00	98.79	0.00	/workspace/coverage/cover_reg_top/5.xbar_stress_all.1723928013
95.76	0.01	94.90	0.00	93.63	0.00	95.18	0.00			94.51	0.00	97.55	0.00	98.80	0.01	/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.3534379575
95.76	0.01	94.90	0.00	93.63	0.00	95.18	0.00			94.51	0.00	97.55	0.00	98.81	0.01	/workspace/coverage/cover_reg_top/48.xbar_stress_all_with_rand_reset.2035277326
95.76	0.01	94.90	0.00	93.63	0.00	95.18	0.00			94.51	0.00	97.55	0.00	98.83	0.01	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.3212742942
95.77	0.01	94.90	0.00	93.63	0.00	95.18	0.00			94.51	0.00	97.55	0.00	98.84	0.01	/workspace/coverage/default/0.chip_sw_all_escalation_resets.1278575790
95.77	0.01	94.90	0.00	93.63	0.00	95.18	0.00			94.51	0.00	97.55	0.00	98.85	0.01	/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.3116838191
95.77	0.01	94.90	0.00	93.63	0.00	95.18	0.00			94.51	0.00	97.55	0.00	98.86	0.01	/workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.1163691510
95.77	0.01	94.90	0.00	93.63	0.00	95.18	0.00			94.51	0.00	97.55	0.00	98.87	0.01	/workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.150471555
95.77	0.01	94.90	0.00	93.63	0.00	95.18	0.00			94.51	0.00	97.55	0.00	98.88	0.01	/workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.1860516347
95.78	0.01	94.90	0.00	93.63	0.00	95.18	0.00			94.51	0.00	97.55	0.00	98.90	0.01	/workspace/coverage/default/12.chip_sw_all_escalation_resets.2467616547
95.78	0.01	94.90	0.00	93.63	0.00	95.18	0.00			94.51	0.00	97.55	0.00	98.91	0.01	/workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.2477019416
95.78	0.01	94.90	0.00	93.63	0.00	95.18	0.00			94.51	0.00	97.55	0.00	98.92	0.01	/workspace/coverage/default/13.chip_sw_all_escalation_resets.1712799597
95.78	0.01	94.90	0.00	93.63	0.00	95.18	0.00			94.51	0.00	97.55	0.00	98.93	0.01	/workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.223684572
95.78	0.01	94.90	0.00	93.63	0.00	95.18	0.00			94.51	0.00	97.55	0.00	98.94	0.01	/workspace/coverage/default/14.chip_sw_all_escalation_resets.3784342494
95.79	0.01	94.90	0.00	93.63	0.00	95.18	0.00			94.51	0.00	97.55	0.00	98.95	0.01	/workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.4106566584
95.79	0.01	94.90	0.00	93.63	0.00	95.18	0.00			94.51	0.00	97.55	0.00	98.97	0.01	/workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.3857605913
95.79	0.01	94.90	0.00	93.63	0.00	95.18	0.00			94.51	0.00	97.55	0.00	98.98	0.01	/workspace/coverage/default/17.chip_sw_all_escalation_resets.4262012067
95.79	0.01	94.90	0.00	93.63	0.00	95.18	0.00			94.51	0.00	97.55	0.00	98.99	0.01	/workspace/coverage/default/18.chip_sw_all_escalation_resets.189948303
95.79	0.01	94.90	0.00	93.63	0.00	95.18	0.00			94.51	0.00	97.55	0.00	99.00	0.01	/workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.1880573671
95.80	0.01	94.90	0.00	93.63	0.00	95.18	0.00			94.51	0.00	97.55	0.00	99.01	0.01	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.2962875644
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95.80	0.01	94.90	0.00	93.63	0.00	95.18	0.00			94.51	0.00	97.55	0.00	99.04	0.01	/workspace/coverage/default/20.chip_sw_all_escalation_resets.1731056149
95.80	0.01	94.90	0.00	93.63	0.00	95.18	0.00			94.51	0.00	97.55	0.00	99.05	0.01	/workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.692890986
95.80	0.01	94.90	0.00	93.63	0.00	95.18	0.00			94.51	0.00	97.55	0.00	99.06	0.01	/workspace/coverage/default/22.chip_sw_all_escalation_resets.3651625414
95.81	0.01	94.90	0.00	93.63	0.00	95.18	0.00			94.51	0.00	97.55	0.00	99.07	0.01	/workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.3511782874
95.81	0.01	94.90	0.00	93.63	0.00	95.18	0.00			94.51	0.00	97.55	0.00	99.08	0.01	/workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.916204679
95.81	0.01	94.90	0.00	93.63	0.00	95.18	0.00			94.51	0.00	97.55	0.00	99.10	0.01	/workspace/coverage/default/26.chip_sw_all_escalation_resets.798354282
95.81	0.01	94.90	0.00	93.63	0.00	95.18	0.00			94.51	0.00	97.55	0.00	99.11	0.01	/workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.356364599
95.81	0.01	94.90	0.00	93.63	0.00	95.18	0.00			94.51	0.00	97.55	0.00	99.12	0.01	/workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.729272555
95.82	0.01	94.90	0.00	93.63	0.00	95.18	0.00			94.51	0.00	97.55	0.00	99.13	0.01	/workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.1672632305
95.82	0.01	94.90	0.00	93.63	0.00	95.18	0.00			94.51	0.00	97.55	0.00	99.14	0.01	/workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.1656068353
95.82	0.01	94.90	0.00	93.63	0.00	95.18	0.00			94.51	0.00	97.55	0.00	99.15	0.01	/workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.3927602848
95.82	0.01	94.90	0.00	93.63	0.00	95.18	0.00			94.51	0.00	97.55	0.00	99.17	0.01	/workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.1697230995
95.82	0.01	94.90	0.00	93.63	0.00	95.18	0.00			94.51	0.00	97.55	0.00	99.18	0.01	/workspace/coverage/default/32.chip_sw_all_escalation_resets.1061843964
95.83	0.01	94.90	0.00	93.63	0.00	95.18	0.00			94.51	0.00	97.55	0.00	99.19	0.01	/workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.967690516
95.83	0.01	94.90	0.00	93.63	0.00	95.18	0.00			94.51	0.00	97.55	0.00	99.20	0.01	/workspace/coverage/default/33.chip_sw_all_escalation_resets.1833876305
95.83	0.01	94.90	0.00	93.63	0.00	95.18	0.00			94.51	0.00	97.55	0.00	99.21	0.01	/workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.4194646830
95.83	0.01	94.90	0.00	93.63	0.00	95.18	0.00			94.51	0.00	97.55	0.00	99.22	0.01	/workspace/coverage/default/38.chip_sw_all_escalation_resets.4227718259
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95.84	0.01	94.90	0.00	93.63	0.00	95.18	0.00			94.51	0.00	97.55	0.00	99.26	0.01	/workspace/coverage/default/40.chip_sw_all_escalation_resets.1471767678
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95.89	0.01	94.90	0.00	93.63	0.00	95.19	0.01			94.51	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/default/0.rom_e2e_jtag_debug_rma.3550106707
95.89	0.01	94.90	0.00	93.64	0.01	95.19	0.00			94.51	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_entropy_src_csrng.3678537962
95.89	0.01	94.90	0.00	93.65	0.01	95.19	0.00			94.51	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.3667128182
95.89	0.01	94.90	0.00	93.66	0.01	95.19	0.00			94.51	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.1603939528
95.90	0.01	94.90	0.00	93.67	0.01	95.19	0.00			94.51	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.2990385676
95.90	0.01	94.90	0.00	93.68	0.01	95.19	0.00			94.51	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.60262969
95.90	0.01	94.90	0.00	93.69	0.01	95.19	0.00			94.51	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_10.2945360113
95.90	0.01	94.91	0.01	93.69	0.00	95.20	0.01			94.51	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/default/84.chip_sw_all_escalation_resets.833390139
95.90	0.01	94.92	0.01	93.69	0.00	95.20	0.00			94.51	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_plic_sw_irq.1893555426
95.90	0.01	94.92	0.00	93.69	0.00	95.20	0.01			94.51	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_aon_timer_smoketest.2316245560
95.91	0.01	94.92	0.00	93.69	0.00	95.21	0.01			94.51	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_exit_test_unlocked_bootstrap.235699448
95.91	0.01	94.92	0.00	93.69	0.00	95.22	0.01			94.51	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.3749968902
95.91	0.01	94.92	0.00	93.69	0.00	95.23	0.01			94.51	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.896833185
95.91	0.01	94.92	0.00	93.69	0.00	95.23	0.00			94.52	0.01	97.55	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.3739757376
95.91	0.01	94.92	0.00	93.69	0.00	95.23	0.00			94.52	0.01	97.55	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.2771375324
95.91	0.01	94.92	0.00	93.69	0.00	95.23	0.00			94.53	0.01	97.55	0.00	99.55	0.00	/workspace/coverage/default/3.chip_tap_straps_dev.3644794109
95.91	0.01	94.92	0.00	93.70	0.01	95.23	0.00			94.53	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/cover_reg_top/10.chip_tl_errors.4286352605
95.91	0.01	94.92	0.00	93.70	0.01	95.23	0.00			94.53	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/cover_reg_top/11.xbar_same_source.114389675
95.92	0.01	94.92	0.00	93.71	0.01	95.23	0.00			94.53	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/cover_reg_top/14.xbar_stress_all.4145148034
95.92	0.01	94.92	0.00	93.72	0.01	95.23	0.00			94.53	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_rstmgr_alert_info.3853515936
95.92	0.01	94.92	0.00	93.72	0.00	95.24	0.01			94.53	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2735019470
95.92	0.01	94.92	0.01	93.72	0.00	95.24	0.01			94.53	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_spi_host_tx_rx.1550419700
95.92	0.01	94.92	0.00	93.72	0.00	95.25	0.01			94.53	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.563053958
95.92	0.01	94.92	0.00	93.72	0.00	95.25	0.01			94.53	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.1744979800
95.92	0.01	94.92	0.00	93.72	0.00	95.26	0.01			94.53	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_flash_init.1479547611
95.92	0.01	94.92	0.00	93.72	0.00	95.26	0.01			94.53	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_lc_ctrl_program_error.3701015559
95.92	0.01	94.92	0.00	93.72	0.00	95.27	0.01			94.53	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2830908774
95.92	0.01	94.92	0.00	93.72	0.00	95.27	0.01			94.53	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/default/2.chip_sw_keymgr_sideload_aes.206067196
95.92	0.01	94.92	0.00	93.72	0.01	95.27	0.00			94.53	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/cover_reg_top/0.chip_csr_mem_rw_with_rand_reset.2214887554
95.93	0.01	94.92	0.00	93.72	0.01	95.27	0.00			94.53	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/cover_reg_top/0.chip_tl_errors.4030080473
95.93	0.01	94.92	0.00	93.73	0.01	95.27	0.00			94.53	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.4274688428
95.93	0.01	94.92	0.00	93.73	0.01	95.27	0.00			94.53	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.3810230352
95.93	0.01	94.92	0.00	93.73	0.01	95.27	0.00			94.53	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/cover_reg_top/17.chip_tl_errors.3207318299
95.93	0.01	94.92	0.00	93.74	0.01	95.27	0.00			94.53	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/cover_reg_top/23.xbar_stress_all_with_error.1520927987
95.93	0.01	94.92	0.00	93.74	0.01	95.27	0.00			94.53	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/cover_reg_top/43.xbar_stress_all_with_reset_error.1074444150
95.93	0.01	94.92	0.00	93.75	0.01	95.27	0.00			94.53	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/cover_reg_top/62.xbar_stress_all_with_reset_error.155695281
95.93	0.01	94.92	0.00	93.75	0.01	95.27	0.00			94.53	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/cover_reg_top/83.xbar_stress_all_with_reset_error.217514242
95.93	0.01	94.92	0.00	93.75	0.01	95.27	0.00			94.53	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/cover_reg_top/99.xbar_stress_all_with_error.1000708102
95.93	0.01	94.92	0.00	93.76	0.01	95.27	0.00			94.53	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.1668308740
95.93	0.01	94.92	0.00	93.76	0.01	95.27	0.00			94.53	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.1283668394
95.93	0.01	94.92	0.00	93.76	0.01	95.27	0.00			94.53	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.1064791553
95.93	0.01	94.92	0.00	93.77	0.01	95.27	0.00			94.53	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/default/1.chip_sw_i2c_device_tx_rx.3436149891
95.93	0.01	94.92	0.00	93.77	0.01	95.27	0.00			94.53	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/default/1.chip_sw_pwrmgr_lowpower_cancel.1609957208
95.93	0.01	94.92	0.00	93.77	0.01	95.27	0.00			94.53	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/default/2.chip_sw_gpio.767361904
95.93	0.01	94.92	0.00	93.78	0.01	95.27	0.00			94.53	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.683793118
95.93	0.01	94.92	0.00	93.78	0.00	95.27	0.01			94.53	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_edn_boot_mode.2205022615
95.93	0.01	94.92	0.00	93.78	0.00	95.27	0.01			94.53	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.3822597670
95.94	0.01	94.92	0.00	93.78	0.00	95.28	0.01			94.53	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.451703197
95.94	0.01	94.92	0.00	93.78	0.00	95.28	0.01			94.53	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.1649076971
95.94	0.01	94.92	0.00	93.78	0.00	95.28	0.01			94.53	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.1688430928
95.94	0.01	94.92	0.00	93.78	0.00	95.28	0.01			94.53	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.1433903396
95.94	0.01	94.92	0.00	93.78	0.00	95.28	0.01			94.53	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.1162929125

---

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.chip_csr_bit_bash.1652011610
/workspace/coverage/cover_reg_top/0.chip_csr_hw_reset.2380321553
/workspace/coverage/cover_reg_top/0.chip_csr_rw.2952403302
/workspace/coverage/cover_reg_top/0.chip_prim_tl_access.2547666487
/workspace/coverage/cover_reg_top/0.chip_same_csr_outstanding.4074911297
/workspace/coverage/cover_reg_top/0.xbar_access_same_device.1573311445
/workspace/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.1210477005
/workspace/coverage/cover_reg_top/0.xbar_error_random.3818268597
/workspace/coverage/cover_reg_top/0.xbar_random.2689276314
/workspace/coverage/cover_reg_top/0.xbar_random_large_delays.2822498355
/workspace/coverage/cover_reg_top/0.xbar_random_slow_rsp.1936279819
/workspace/coverage/cover_reg_top/0.xbar_random_zero_delays.793354669
/workspace/coverage/cover_reg_top/0.xbar_same_source.1168119764
/workspace/coverage/cover_reg_top/0.xbar_smoke.687747718
/workspace/coverage/cover_reg_top/0.xbar_smoke_large_delays.388730154
/workspace/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.1172100423
/workspace/coverage/cover_reg_top/0.xbar_smoke_zero_delays.2170819073
/workspace/coverage/cover_reg_top/0.xbar_stress_all.2377667580
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_error.2041568030
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.3026735050
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.2051996318
/workspace/coverage/cover_reg_top/0.xbar_unmapped_addr.2072647302
/workspace/coverage/cover_reg_top/1.chip_csr_aliasing.1520494108
/workspace/coverage/cover_reg_top/1.chip_csr_bit_bash.2290893356
/workspace/coverage/cover_reg_top/1.chip_csr_hw_reset.536068188
/workspace/coverage/cover_reg_top/1.chip_csr_mem_rw_with_rand_reset.1467999568
/workspace/coverage/cover_reg_top/1.chip_csr_rw.3211502133
/workspace/coverage/cover_reg_top/1.chip_prim_tl_access.3389027273
/workspace/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.4140222755
/workspace/coverage/cover_reg_top/1.chip_same_csr_outstanding.3594853290
/workspace/coverage/cover_reg_top/1.chip_tl_errors.4226962208
/workspace/coverage/cover_reg_top/1.xbar_access_same_device.1099875566
/workspace/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.3006655580
/workspace/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.1037486329
/workspace/coverage/cover_reg_top/1.xbar_error_random.553300154
/workspace/coverage/cover_reg_top/1.xbar_random.2493299773
/workspace/coverage/cover_reg_top/1.xbar_random_large_delays.4182750308
/workspace/coverage/cover_reg_top/1.xbar_random_slow_rsp.3300574184
/workspace/coverage/cover_reg_top/1.xbar_random_zero_delays.1699939807
/workspace/coverage/cover_reg_top/1.xbar_same_source.814754827
/workspace/coverage/cover_reg_top/1.xbar_smoke.129768642
/workspace/coverage/cover_reg_top/1.xbar_smoke_large_delays.1490741828
/workspace/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.1906893202
/workspace/coverage/cover_reg_top/1.xbar_smoke_zero_delays.3026137805
/workspace/coverage/cover_reg_top/1.xbar_stress_all.3229672061
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_error.865283289
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.4128786378
/workspace/coverage/cover_reg_top/1.xbar_unmapped_addr.1910926858
/workspace/coverage/cover_reg_top/10.chip_csr_mem_rw_with_rand_reset.931440861
/workspace/coverage/cover_reg_top/10.chip_csr_rw.3498837815
/workspace/coverage/cover_reg_top/10.chip_same_csr_outstanding.1035274578
/workspace/coverage/cover_reg_top/10.xbar_access_same_device.1156278905
/workspace/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.323819458
/workspace/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.2136474648
/workspace/coverage/cover_reg_top/10.xbar_error_random.77840446
/workspace/coverage/cover_reg_top/10.xbar_random.158484498
/workspace/coverage/cover_reg_top/10.xbar_random_large_delays.3601420259
/workspace/coverage/cover_reg_top/10.xbar_random_slow_rsp.2523988743
/workspace/coverage/cover_reg_top/10.xbar_random_zero_delays.2673907594
/workspace/coverage/cover_reg_top/10.xbar_same_source.748751884
/workspace/coverage/cover_reg_top/10.xbar_smoke.4234754349
/workspace/coverage/cover_reg_top/10.xbar_smoke_large_delays.4091683212
/workspace/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.2567143841
/workspace/coverage/cover_reg_top/10.xbar_smoke_zero_delays.3281376231
/workspace/coverage/cover_reg_top/10.xbar_stress_all.31667297
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_error.338503036
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.1645438042
/workspace/coverage/cover_reg_top/10.xbar_unmapped_addr.202861622
/workspace/coverage/cover_reg_top/11.chip_csr_mem_rw_with_rand_reset.966850572
/workspace/coverage/cover_reg_top/11.chip_csr_rw.2574401184
/workspace/coverage/cover_reg_top/11.chip_same_csr_outstanding.748976268
/workspace/coverage/cover_reg_top/11.chip_tl_errors.2036490226
/workspace/coverage/cover_reg_top/11.xbar_access_same_device.1534316401
/workspace/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.3633176457
/workspace/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.1767745214
/workspace/coverage/cover_reg_top/11.xbar_error_random.3698459654
/workspace/coverage/cover_reg_top/11.xbar_random.3771286721
/workspace/coverage/cover_reg_top/11.xbar_random_large_delays.3683821480
/workspace/coverage/cover_reg_top/11.xbar_random_slow_rsp.1757776260
/workspace/coverage/cover_reg_top/11.xbar_random_zero_delays.160695259
/workspace/coverage/cover_reg_top/11.xbar_smoke.4175164402
/workspace/coverage/cover_reg_top/11.xbar_smoke_large_delays.2665390259
/workspace/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.2256903885
/workspace/coverage/cover_reg_top/11.xbar_smoke_zero_delays.2035963679
/workspace/coverage/cover_reg_top/11.xbar_stress_all.1409774671
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_error.663757581
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.1615168347
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.3612004726
/workspace/coverage/cover_reg_top/11.xbar_unmapped_addr.194225100
/workspace/coverage/cover_reg_top/12.chip_csr_mem_rw_with_rand_reset.3078607763
/workspace/coverage/cover_reg_top/12.chip_csr_rw.4179736995
/workspace/coverage/cover_reg_top/12.chip_same_csr_outstanding.1501193203
/workspace/coverage/cover_reg_top/12.chip_tl_errors.1760770445
/workspace/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.1463737799
/workspace/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.32407606
/workspace/coverage/cover_reg_top/12.xbar_error_random.22388705
/workspace/coverage/cover_reg_top/12.xbar_random.3392641533
/workspace/coverage/cover_reg_top/12.xbar_random_large_delays.1979432494
/workspace/coverage/cover_reg_top/12.xbar_random_slow_rsp.976100615
/workspace/coverage/cover_reg_top/12.xbar_random_zero_delays.1830923507
/workspace/coverage/cover_reg_top/12.xbar_same_source.4187346235
/workspace/coverage/cover_reg_top/12.xbar_smoke.2425829571
/workspace/coverage/cover_reg_top/12.xbar_smoke_large_delays.235714342
/workspace/coverage/cover_reg_top/12.xbar_smoke_slow_rsp.356368570
/workspace/coverage/cover_reg_top/12.xbar_smoke_zero_delays.2140223024
/workspace/coverage/cover_reg_top/12.xbar_stress_all.479611580
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_error.2167861450
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_rand_reset.2727713273
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_reset_error.1123566009
/workspace/coverage/cover_reg_top/12.xbar_unmapped_addr.2436142390
/workspace/coverage/cover_reg_top/13.chip_csr_rw.444926060
/workspace/coverage/cover_reg_top/13.chip_same_csr_outstanding.1065523956
/workspace/coverage/cover_reg_top/13.chip_tl_errors.4084983190
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/workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.926170934
/workspace/coverage/default/34.chip_sw_all_escalation_resets.929788888
/workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.3252358042
/workspace/coverage/default/35.chip_sw_all_escalation_resets.2668853325
/workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.1475914502
/workspace/coverage/default/36.chip_sw_all_escalation_resets.4055220373
/workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.1213721897
/workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.4044444511
/workspace/coverage/default/39.chip_sw_all_escalation_resets.155362856
/workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.1213919496
/workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.1163497224
/workspace/coverage/default/4.chip_sw_csrng_edn_concurrency.1861360321
/workspace/coverage/default/4.chip_sw_data_integrity_escalation.1469626635
/workspace/coverage/default/4.chip_sw_lc_ctrl_transition.4207510551
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/workspace/coverage/default/4.chip_sw_uart_rand_baudrate.2592750632
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/workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.553912160
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/workspace/coverage/default/44.chip_sw_all_escalation_resets.3721819382
/workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.2373259212
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/workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.1540389297
/workspace/coverage/default/49.chip_sw_all_escalation_resets.1020611818
/workspace/coverage/default/5.chip_sw_all_escalation_resets.2225472973
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/workspace/coverage/default/5.chip_sw_lc_ctrl_transition.3125730802
/workspace/coverage/default/5.chip_sw_uart_rand_baudrate.1694779413
/workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.2520840780
/workspace/coverage/default/50.chip_sw_all_escalation_resets.2275468451
/workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.3096828338
/workspace/coverage/default/51.chip_sw_all_escalation_resets.2884666613
/workspace/coverage/default/52.chip_sw_all_escalation_resets.1255629260
/workspace/coverage/default/53.chip_sw_all_escalation_resets.2608674636
/workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.3951492608
/workspace/coverage/default/54.chip_sw_all_escalation_resets.1175685291
/workspace/coverage/default/55.chip_sw_all_escalation_resets.1724671535
/workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.3626350951
/workspace/coverage/default/56.chip_sw_all_escalation_resets.1149119758
/workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.1327546334
/workspace/coverage/default/57.chip_sw_all_escalation_resets.3835762312
/workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.617848859
/workspace/coverage/default/59.chip_sw_all_escalation_resets.185193126
/workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.3332605344
/workspace/coverage/default/6.chip_sw_all_escalation_resets.593554043
/workspace/coverage/default/6.chip_sw_csrng_edn_concurrency.77306471
/workspace/coverage/default/6.chip_sw_uart_rand_baudrate.1960092356
/workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.729033506
/workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.2764940147
/workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.3720920042
/workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.3386465049
/workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.101876178
/workspace/coverage/default/64.chip_sw_all_escalation_resets.1578762893
/workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.2967343053
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/workspace/coverage/default/66.chip_sw_all_escalation_resets.4178539396
/workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.2213049526
/workspace/coverage/default/67.chip_sw_all_escalation_resets.2155367222
/workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.2923813657
/workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.2756868225
/workspace/coverage/default/69.chip_sw_all_escalation_resets.2190392640
/workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.4028209609
/workspace/coverage/default/7.chip_sw_all_escalation_resets.3397685587
/workspace/coverage/default/7.chip_sw_csrng_edn_concurrency.3340508502
/workspace/coverage/default/7.chip_sw_lc_ctrl_transition.3319760240
/workspace/coverage/default/7.chip_sw_uart_rand_baudrate.918800647
/workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.3883901058
/workspace/coverage/default/70.chip_sw_all_escalation_resets.3514036844
/workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.1844398837
/workspace/coverage/default/71.chip_sw_all_escalation_resets.3150589624
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/workspace/coverage/default/73.chip_sw_all_escalation_resets.2747798239
/workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.1526921510
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/workspace/coverage/default/75.chip_sw_all_escalation_resets.3469554741
/workspace/coverage/default/76.chip_sw_all_escalation_resets.1674913473
/workspace/coverage/default/77.chip_sw_all_escalation_resets.3190627785
/workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.1002859065
/workspace/coverage/default/79.chip_sw_all_escalation_resets.2140596107
/workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.2171688923
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/workspace/coverage/default/8.chip_sw_lc_ctrl_transition.618040374
/workspace/coverage/default/8.chip_sw_uart_rand_baudrate.1603218030
/workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.3839697823
/workspace/coverage/default/80.chip_sw_all_escalation_resets.398655837
/workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.1193446908
/workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.118791591
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/workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.1936889040
/workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.1730964378
/workspace/coverage/default/85.chip_sw_all_escalation_resets.3064313654
/workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.4150106249
/workspace/coverage/default/86.chip_sw_all_escalation_resets.1194494158
/workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.1444720240
/workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.1718615570
/workspace/coverage/default/88.chip_sw_all_escalation_resets.1000287413
/workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.4236366109
/workspace/coverage/default/89.chip_sw_all_escalation_resets.1342874874
/workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.4098775560
/workspace/coverage/default/9.chip_sw_all_escalation_resets.201768206
/workspace/coverage/default/9.chip_sw_csrng_edn_concurrency.1401776569
/workspace/coverage/default/9.chip_sw_lc_ctrl_transition.271647999
/workspace/coverage/default/9.chip_sw_uart_rand_baudrate.3643215645
/workspace/coverage/default/90.chip_sw_all_escalation_resets.3711080636
/workspace/coverage/default/91.chip_sw_all_escalation_resets.1227646615
/workspace/coverage/default/92.chip_sw_all_escalation_resets.473173902
/workspace/coverage/default/93.chip_sw_all_escalation_resets.1638663196
/workspace/coverage/default/94.chip_sw_all_escalation_resets.2868578904
/workspace/coverage/default/95.chip_sw_all_escalation_resets.858196365
/workspace/coverage/default/96.chip_sw_all_escalation_resets.4000482079
/workspace/coverage/default/97.chip_sw_all_escalation_resets.3700624680
/workspace/coverage/default/98.chip_sw_all_escalation_resets.685482017
/workspace/coverage/default/99.chip_sw_all_escalation_resets.2364363338
/workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.4119287746
/workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.613844756
/workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.1524005084
/workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.4279961317
/workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.1692664782
/workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.2263809568
/workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.729632491

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Total test records in report: 2934

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TEST NO	TEST LOCATION	TEST NAME	STATUS	STARTED	FINISHED	SIMULATION TIME
T1	/workspace/coverage/default/4.chip_sw_csrng_edn_concurrency.1861360321			Aug 07 08:22:54 PM PDT 24	Aug 07 09:08:58 PM PDT 24	11172499424 ps
T2	/workspace/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.1994225074			Aug 07 07:54:20 PM PDT 24	Aug 07 08:02:19 PM PDT 24	4817876292 ps
T3	/workspace/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.1433903396			Aug 07 07:58:20 PM PDT 24	Aug 07 08:01:24 PM PDT 24	3000806112 ps
T4	/workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.729272555			Aug 07 08:26:15 PM PDT 24	Aug 07 08:32:47 PM PDT 24	4185843520 ps
T5	/workspace/coverage/default/10.chip_sw_uart_rand_baudrate.369484445			Aug 07 08:24:26 PM PDT 24	Aug 07 08:51:38 PM PDT 24	8329403884 ps
T6	/workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.3550888756			Aug 07 08:27:03 PM PDT 24	Aug 07 08:34:55 PM PDT 24	3531634632 ps
T7	/workspace/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.235311586			Aug 07 08:14:42 PM PDT 24	Aug 07 08:50:15 PM PDT 24	23382215254 ps
T48	/workspace/coverage/default/0.rom_e2e_jtag_debug_rma.3550106707			Aug 07 07:58:10 PM PDT 24	Aug 07 08:35:54 PM PDT 24	10735584626 ps
T49	/workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_meas.845842105			Aug 07 08:11:50 PM PDT 24	Aug 07 09:14:09 PM PDT 24	15472966200 ps
T90	/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx2.3752409466			Aug 07 07:58:32 PM PDT 24	Aug 07 08:09:13 PM PDT 24	5055700920 ps
T134	/workspace/coverage/default/3.chip_sw_csrng_edn_concurrency.802204123			Aug 07 08:20:28 PM PDT 24	Aug 07 10:01:03 PM PDT 24	27824744220 ps
T36	/workspace/coverage/default/2.chip_sw_rstmgr_alert_info.1900303772			Aug 07 08:10:50 PM PDT 24	Aug 07 08:41:24 PM PDT 24	11627266700 ps
T13	/workspace/coverage/default/1.chip_sw_power_virus.2368530446			Aug 07 08:13:33 PM PDT 24	Aug 07 08:39:33 PM PDT 24	5913526716 ps
T86	/workspace/coverage/default/2.chip_sw_alert_handler_entropy.2291327177			Aug 07 08:12:40 PM PDT 24	Aug 07 08:18:36 PM PDT 24	4048397861 ps
T53	/workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.3372918410			Aug 07 07:51:32 PM PDT 24	Aug 07 07:53:30 PM PDT 24	2795434750 ps
T68	/workspace/coverage/default/25.chip_sw_all_escalation_resets.2653710206			Aug 07 08:24:54 PM PDT 24	Aug 07 08:37:18 PM PDT 24	5722742936 ps
T718	/workspace/coverage/default/1.chip_sw_aes_entropy.1477300351			Aug 07 08:02:53 PM PDT 24	Aug 07 08:07:31 PM PDT 24	3123512060 ps
T219	/workspace/coverage/default/0.chip_sw_pattgen_ios.2834601277			Aug 07 07:53:42 PM PDT 24	Aug 07 07:57:01 PM PDT 24	2998212152 ps
T329	/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.3116838191			Aug 07 08:02:18 PM PDT 24	Aug 07 08:08:15 PM PDT 24	3653975260 ps
T212	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.1542493637			Aug 07 07:53:31 PM PDT 24	Aug 07 08:04:31 PM PDT 24	4364015269 ps
T129	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2830908774			Aug 07 07:52:54 PM PDT 24	Aug 07 08:02:40 PM PDT 24	6490170350 ps
T220	/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx2.1896225297			Aug 07 08:09:20 PM PDT 24	Aug 07 08:21:49 PM PDT 24	4593291870 ps
T158	/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.3047260654			Aug 07 08:00:50 PM PDT 24	Aug 07 08:22:45 PM PDT 24	6731636212 ps
T19	/workspace/coverage/default/0.chip_sw_usbdev_config_host.1666097207			Aug 07 07:51:28 PM PDT 24	Aug 07 08:25:37 PM PDT 24	8205377560 ps
T69	/workspace/coverage/default/8.chip_sw_all_escalation_resets.2085103260			Aug 07 08:22:37 PM PDT 24	Aug 07 08:37:47 PM PDT 24	6365766844 ps
T8	/workspace/coverage/default/1.chip_sw_rom_ctrl_integrity_check.3675914710			Aug 07 08:04:26 PM PDT 24	Aug 07 08:14:16 PM PDT 24	7943799649 ps
T203	/workspace/coverage/default/3.chip_sw_data_integrity_escalation.2341023581			Aug 07 08:19:53 PM PDT 24	Aug 07 08:33:34 PM PDT 24	6256109694 ps
T284	/workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.101876178			Aug 07 08:28:46 PM PDT 24	Aug 07 08:36:54 PM PDT 24	3651979340 ps
T285	/workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.4150106249			Aug 07 08:32:30 PM PDT 24	Aug 07 08:38:46 PM PDT 24	3780941520 ps
T9	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.148666243			Aug 07 07:59:11 PM PDT 24	Aug 07 08:56:40 PM PDT 24	14665607496 ps
T171	/workspace/coverage/default/0.rom_e2e_asm_init_test_unlocked0.955755834			Aug 07 08:01:25 PM PDT 24	Aug 07 08:58:07 PM PDT 24	11232411184 ps
T263	/workspace/coverage/default/97.chip_sw_all_escalation_resets.3700624680			Aug 07 08:31:50 PM PDT 24	Aug 07 08:41:56 PM PDT 24	5763428616 ps
T46	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.2778423354			Aug 07 08:04:12 PM PDT 24	Aug 07 09:51:06 PM PDT 24	23612976676 ps
T163	/workspace/coverage/default/35.chip_sw_all_escalation_resets.2668853325			Aug 07 08:25:14 PM PDT 24	Aug 07 08:36:46 PM PDT 24	5449705338 ps
T286	/workspace/coverage/default/0.chip_sw_aes_masking_off.3584292679			Aug 07 07:52:47 PM PDT 24	Aug 07 07:58:45 PM PDT 24	3439034857 ps
T130	/workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.2699107037			Aug 07 08:19:58 PM PDT 24	Aug 07 08:26:40 PM PDT 24	7232603824 ps
T258	/workspace/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.4050945279			Aug 07 08:11:21 PM PDT 24	Aug 07 08:34:07 PM PDT 24	9823916232 ps
T217	/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx1.3708233039			Aug 07 08:20:01 PM PDT 24	Aug 07 08:30:11 PM PDT 24	4554065592 ps
T380	/workspace/coverage/default/0.chip_sw_kmac_entropy.4128895103			Aug 07 07:52:28 PM PDT 24	Aug 07 07:56:56 PM PDT 24	2653211384 ps
T224	/workspace/coverage/default/7.chip_sw_all_escalation_resets.3397685587			Aug 07 08:21:55 PM PDT 24	Aug 07 08:35:34 PM PDT 24	6291698008 ps
T918	/workspace/coverage/default/1.chip_sw_aes_smoketest.971449016			Aug 07 08:07:23 PM PDT 24	Aug 07 08:13:01 PM PDT 24	3457073900 ps
T174	/workspace/coverage/default/2.chip_sw_flash_init.1048621238			Aug 07 08:10:46 PM PDT 24	Aug 07 08:49:11 PM PDT 24	20487204090 ps
T245	/workspace/coverage/default/4.chip_sw_data_integrity_escalation.1469626635			Aug 07 08:22:58 PM PDT 24	Aug 07 08:33:17 PM PDT 24	4643005208 ps
T218	/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx1.1365978626			Aug 07 08:09:18 PM PDT 24	Aug 07 08:21:12 PM PDT 24	4554370820 ps
T50	/workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.2771375324			Aug 07 07:58:28 PM PDT 24	Aug 07 08:09:41 PM PDT 24	5202615191 ps
T20	/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.3239905442			Aug 07 08:05:39 PM PDT 24	Aug 07 08:39:29 PM PDT 24	23252133704 ps
T108	/workspace/coverage/default/0.chip_sw_aon_timer_smoketest.2316245560			Aug 07 07:56:55 PM PDT 24	Aug 07 08:00:50 PM PDT 24	3269508406 ps
T21	/workspace/coverage/default/0.chip_sw_usbdev_pullup.2753141483			Aug 07 07:53:31 PM PDT 24	Aug 07 07:57:56 PM PDT 24	2983146600 ps
T51	/workspace/coverage/default/6.chip_sw_lc_ctrl_transition.777455155			Aug 07 08:22:55 PM PDT 24	Aug 07 08:33:11 PM PDT 24	6554901997 ps
T109	/workspace/coverage/default/1.chip_sw_plic_sw_irq.241597765			Aug 07 08:04:26 PM PDT 24	Aug 07 08:07:43 PM PDT 24	2708800860 ps
T110	/workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.3927602848			Aug 07 08:28:07 PM PDT 24	Aug 07 08:34:36 PM PDT 24	3292060806 ps
T111	/workspace/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.4133145383			Aug 07 08:12:57 PM PDT 24	Aug 07 08:16:53 PM PDT 24	2844840321 ps
T112	/workspace/coverage/default/1.chip_sw_kmac_smoketest.995482095			Aug 07 08:08:24 PM PDT 24	Aug 07 08:13:31 PM PDT 24	2759639984 ps
T113	/workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.488199007			Aug 07 08:19:40 PM PDT 24	Aug 07 08:28:33 PM PDT 24	5010317004 ps
T16	/workspace/coverage/default/2.chip_sw_gpio_smoketest.3239513158			Aug 07 08:19:52 PM PDT 24	Aug 07 08:25:41 PM PDT 24	3220162279 ps
T173	/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_dev.2134173217			Aug 07 08:10:22 PM PDT 24	Aug 07 08:32:41 PM PDT 24	8856951364 ps
T52	/workspace/coverage/default/13.chip_sw_lc_ctrl_transition.3003565986			Aug 07 08:23:23 PM PDT 24	Aug 07 08:35:35 PM PDT 24	12557955747 ps
T919	/workspace/coverage/default/0.chip_sw_otp_ctrl_ecc_error_vendor_test.2814738047			Aug 07 07:52:24 PM PDT 24	Aug 07 07:57:17 PM PDT 24	3241042329 ps
T67	/workspace/coverage/default/2.chip_sw_lc_walkthrough_rma.1285261444			Aug 07 08:10:31 PM PDT 24	Aug 07 09:37:53 PM PDT 24	47883921040 ps
T170	/workspace/coverage/default/1.chip_sw_lc_walkthrough_dev.1210041914			Aug 07 07:59:32 PM PDT 24	Aug 07 09:37:11 PM PDT 24	47843090026 ps
T124	/workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.3216249652			Aug 07 08:06:33 PM PDT 24	Aug 07 08:30:14 PM PDT 24	7796678520 ps
T313	/workspace/coverage/default/37.chip_sw_all_escalation_resets.2682988632			Aug 07 08:26:22 PM PDT 24	Aug 07 08:34:34 PM PDT 24	4575857902 ps
T17	/workspace/coverage/default/2.chip_sw_uart_tx_rx_bootstrap.3043787625			Aug 07 08:08:54 PM PDT 24	Aug 08 12:07:28 AM PDT 24	78601979416 ps
T162	/workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.1822945989			Aug 07 08:31:03 PM PDT 24	Aug 07 08:38:23 PM PDT 24	3874662408 ps
T125	/workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.1062851018			Aug 07 07:56:45 PM PDT 24	Aug 07 08:00:56 PM PDT 24	2664694390 ps
T920	/workspace/coverage/default/2.chip_sw_aes_enc_jitter_en_reduced_freq.3793543937			Aug 07 08:17:10 PM PDT 24	Aug 07 08:21:39 PM PDT 24	2670712269 ps
T74	/workspace/coverage/default/4.chip_tap_straps_testunlock0.882272566			Aug 07 08:20:31 PM PDT 24	Aug 07 08:23:08 PM PDT 24	2878895312 ps
T921	/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.143485177			Aug 07 07:58:12 PM PDT 24	Aug 07 08:11:07 PM PDT 24	4165681136 ps
T322	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops.4104375907			Aug 07 07:53:34 PM PDT 24	Aug 07 08:04:33 PM PDT 24	4394072052 ps
T172	/workspace/coverage/default/0.chip_sw_lc_walkthrough_rma.3383977555			Aug 07 07:51:56 PM PDT 24	Aug 07 09:33:18 PM PDT 24	47871006360 ps
T763	/workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.2171688923			Aug 07 08:26:04 PM PDT 24	Aug 07 08:34:14 PM PDT 24	4120258456 ps
T225	/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_prod.1578280727			Aug 07 07:51:46 PM PDT 24	Aug 07 08:15:20 PM PDT 24	8168164340 ps
T126	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.1974280353			Aug 07 08:06:46 PM PDT 24	Aug 07 08:17:00 PM PDT 24	5118091424 ps
T922	/workspace/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.3293140775			Aug 07 08:01:33 PM PDT 24	Aug 07 08:07:14 PM PDT 24	5912638528 ps
T923	/workspace/coverage/default/2.chip_sw_aes_enc_jitter_en.1969853740			Aug 07 08:12:39 PM PDT 24	Aug 07 08:17:31 PM PDT 24	3549833848 ps
T22	/workspace/coverage/default/1.chip_sw_pwrmgr_usbdev_smoketest.2864978379			Aug 07 08:16:22 PM PDT 24	Aug 07 08:21:55 PM PDT 24	5944207080 ps
T164	/workspace/coverage/default/9.chip_sw_all_escalation_resets.201768206			Aug 07 08:22:10 PM PDT 24	Aug 07 08:30:56 PM PDT 24	5003825586 ps
T363	/workspace/coverage/default/45.chip_sw_all_escalation_resets.2863050516			Aug 07 08:27:13 PM PDT 24	Aug 07 08:40:45 PM PDT 24	5922870588 ps
T247	/workspace/coverage/default/16.chip_sw_all_escalation_resets.1267382774			Aug 07 08:23:53 PM PDT 24	Aug 07 08:34:10 PM PDT 24	5483241560 ps
T119	/workspace/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2123608729			Aug 07 08:01:19 PM PDT 24	Aug 07 08:11:13 PM PDT 24	18994195888 ps
T179	/workspace/coverage/default/0.chip_sw_lc_ctrl_transition.2564494697			Aug 07 07:53:45 PM PDT 24	Aug 07 08:01:07 PM PDT 24	5468482516 ps
T347	/workspace/coverage/default/0.chip_sw_aon_timer_irq.912528163			Aug 07 07:52:43 PM PDT 24	Aug 07 08:00:04 PM PDT 24	3665246476 ps
T127	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.1483976004			Aug 07 07:52:33 PM PDT 24	Aug 07 08:03:04 PM PDT 24	4886356536 ps
T337	/workspace/coverage/default/1.chip_sw_rv_plic_smoketest.698771845			Aug 07 08:08:28 PM PDT 24	Aug 07 08:11:35 PM PDT 24	2849713600 ps
T131	/workspace/coverage/default/1.chip_sw_entropy_src_csrng.1567851983			Aug 07 08:02:57 PM PDT 24	Aug 07 08:26:35 PM PDT 24	5971937852 ps
T18	/workspace/coverage/default/3.chip_sw_uart_rand_baudrate.3745563775			Aug 07 08:20:31 PM PDT 24	Aug 07 08:30:03 PM PDT 24	3991929478 ps
T226	/workspace/coverage/default/2.chip_sw_keymgr_sideload_kmac.3542944199			Aug 07 08:14:34 PM PDT 24	Aug 07 08:56:37 PM PDT 24	12448157388 ps
T23	/workspace/coverage/default/2.chip_jtag_csr_rw.284781311			Aug 07 08:09:35 PM PDT 24	Aug 07 08:51:00 PM PDT 24	19182838075 ps
T924	/workspace/coverage/default/1.chip_sw_clkmgr_jitter_frequency.2111452717			Aug 07 08:04:47 PM PDT 24	Aug 07 08:13:30 PM PDT 24	3670442872 ps
T28	/workspace/coverage/default/0.chip_sw_gpio_smoketest.1304678424			Aug 07 07:55:44 PM PDT 24	Aug 07 07:59:24 PM PDT 24	2581036559 ps
T312	/workspace/coverage/default/0.chip_sw_uart_tx_rx.1587112436			Aug 07 07:52:05 PM PDT 24	Aug 07 08:04:30 PM PDT 24	4694433358 ps
T246	/workspace/coverage/default/0.chip_sw_otbn_mem_scramble.3685394168			Aug 07 07:51:14 PM PDT 24	Aug 07 07:58:52 PM PDT 24	3778146568 ps
T715	/workspace/coverage/default/0.chip_sw_alert_handler_ping_ok.865808612			Aug 07 07:52:41 PM PDT 24	Aug 07 08:18:21 PM PDT 24	7290640134 ps
T925	/workspace/coverage/default/1.chip_sw_clkmgr_smoketest.2190136214			Aug 07 08:07:29 PM PDT 24	Aug 07 08:10:31 PM PDT 24	2503873320 ps
T411	/workspace/coverage/default/0.chip_sw_kmac_app_rom.3602333398			Aug 07 07:53:38 PM PDT 24	Aug 07 07:56:42 PM PDT 24	2360570646 ps
T367	/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset.3141355832			Aug 07 08:11:14 PM PDT 24	Aug 07 09:06:50 PM PDT 24	31170255530 ps
T228	/workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.1936889040			Aug 07 08:29:57 PM PDT 24	Aug 07 08:36:49 PM PDT 24	4606120440 ps
T750	/workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.118791591			Aug 07 08:31:01 PM PDT 24	Aug 07 08:37:50 PM PDT 24	3991789510 ps
T262	/workspace/coverage/default/2.chip_sw_rv_core_ibex_rnd.2382596120			Aug 07 08:12:03 PM PDT 24	Aug 07 08:30:04 PM PDT 24	5194757362 ps
T316	/workspace/coverage/default/40.chip_sw_all_escalation_resets.1471767678			Aug 07 08:26:22 PM PDT 24	Aug 07 08:37:50 PM PDT 24	4717164888 ps
T399	/workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.3511782874			Aug 07 08:25:55 PM PDT 24	Aug 07 08:32:10 PM PDT 24	3711277464 ps
T320	/workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.3108996875			Aug 07 08:10:04 PM PDT 24	Aug 07 08:21:53 PM PDT 24	4304146971 ps
T43	/workspace/coverage/default/0.chip_sw_spi_device_tpm.2493079811			Aug 07 07:54:54 PM PDT 24	Aug 07 08:02:16 PM PDT 24	3567045009 ps
T827	/workspace/coverage/default/82.chip_sw_all_escalation_resets.3387992797			Aug 07 08:29:38 PM PDT 24	Aug 07 08:41:04 PM PDT 24	4721783740 ps
T132	/workspace/coverage/default/0.chip_sw_edn_auto_mode.3149508301			Aug 07 07:53:17 PM PDT 24	Aug 07 08:33:56 PM PDT 24	7154395140 ps
T709	/workspace/coverage/default/32.chip_sw_all_escalation_resets.1061843964			Aug 07 08:24:38 PM PDT 24	Aug 07 08:34:43 PM PDT 24	5259336364 ps
T185	/workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.2259063945			Aug 07 07:55:21 PM PDT 24	Aug 07 08:07:42 PM PDT 24	8170147620 ps
T926	/workspace/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.2036673446			Aug 07 08:16:38 PM PDT 24	Aug 07 08:23:34 PM PDT 24	4024703696 ps
T229	/workspace/coverage/default/0.chip_sw_alert_handler_escalation.1619069819			Aug 07 07:52:35 PM PDT 24	Aug 07 08:01:13 PM PDT 24	4305225560 ps
T356	/workspace/coverage/default/1.chip_sw_uart_rand_baudrate.1160143436			Aug 07 07:57:39 PM PDT 24	Aug 07 08:07:48 PM PDT 24	4350991928 ps
T783	/workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.1799215845			Aug 07 08:24:50 PM PDT 24	Aug 07 08:32:38 PM PDT 24	4076373280 ps
T83	/workspace/coverage/default/0.rom_e2e_jtag_inject_test_unlocked0.1711702166			Aug 07 07:55:08 PM PDT 24	Aug 07 08:55:43 PM PDT 24	29027064566 ps
T338	/workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3531545151			Aug 07 08:16:37 PM PDT 24	Aug 07 08:33:36 PM PDT 24	8507623398 ps
T828	/workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.356364599			Aug 07 08:26:17 PM PDT 24	Aug 07 08:34:55 PM PDT 24	3573982216 ps
T927	/workspace/coverage/default/2.chip_sw_entropy_src_kat_test.568516864			Aug 07 08:13:09 PM PDT 24	Aug 07 08:18:01 PM PDT 24	2932906086 ps
T928	/workspace/coverage/default/0.chip_sw_csrng_kat_test.2371035048			Aug 07 07:54:12 PM PDT 24	Aug 07 07:58:25 PM PDT 24	2986743068 ps
T791	/workspace/coverage/default/73.chip_sw_all_escalation_resets.2747798239			Aug 07 08:29:27 PM PDT 24	Aug 07 08:38:03 PM PDT 24	4934042824 ps
T929	/workspace/coverage/default/0.chip_sw_kmac_mode_cshake.1213481207			Aug 07 07:53:44 PM PDT 24	Aug 07 07:58:06 PM PDT 24	3162566964 ps
T353	/workspace/coverage/default/1.chip_sw_flash_ctrl_ops.3687640704			Aug 07 07:59:19 PM PDT 24	Aug 07 08:08:42 PM PDT 24	4795820856 ps
T14	/workspace/coverage/default/2.chip_sw_power_virus.1184337332			Aug 07 08:23:08 PM PDT 24	Aug 07 08:47:42 PM PDT 24	5693333760 ps
T930	/workspace/coverage/default/2.chip_sw_entropy_src_ast_rng_req.3757193015			Aug 07 08:14:29 PM PDT 24	Aug 07 08:18:14 PM PDT 24	2623426228 ps
T120	/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.1918304654			Aug 07 07:54:12 PM PDT 24	Aug 08 01:41:22 AM PDT 24	141739647815 ps
T213	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.3690246373			Aug 07 08:01:02 PM PDT 24	Aug 07 08:11:51 PM PDT 24	4651584663 ps
T931	/workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.4012895961			Aug 07 08:06:47 PM PDT 24	Aug 07 08:11:18 PM PDT 24	3340253461 ps
T65	/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.2068280635			Aug 07 08:05:43 PM PDT 24	Aug 07 08:13:23 PM PDT 24	6864872676 ps
T47	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.2001059412			Aug 07 07:59:25 PM PDT 24	Aug 07 09:09:18 PM PDT 24	14522965584 ps
T368	/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.3504447571			Aug 07 08:01:48 PM PDT 24	Aug 07 09:00:04 PM PDT 24	51221746431 ps
T829	/workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.1526921510			Aug 07 08:29:29 PM PDT 24	Aug 07 08:35:36 PM PDT 24	3800545592 ps
T932	/workspace/coverage/default/0.chip_sw_csrng_smoketest.785278356			Aug 07 07:56:35 PM PDT 24	Aug 07 08:00:34 PM PDT 24	2663326400 ps
T24	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_outputs.1923851070			Aug 07 08:01:30 PM PDT 24	Aug 07 08:08:45 PM PDT 24	4041356416 ps
T378	/workspace/coverage/default/0.rom_e2e_asm_init_prod_end.2533801594			Aug 07 07:58:22 PM PDT 24	Aug 07 09:08:51 PM PDT 24	15177689124 ps
T790	/workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.2398636006			Aug 07 07:53:30 PM PDT 24	Aug 07 08:16:06 PM PDT 24	5541967314 ps
T761	/workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.2967343053			Aug 07 08:29:32 PM PDT 24	Aug 07 08:37:04 PM PDT 24	3956504432 ps
T227	/workspace/coverage/default/2.chip_sw_keymgr_sideload_aes.206067196			Aug 07 08:13:55 PM PDT 24	Aug 07 09:01:07 PM PDT 24	12088742104 ps
T230	/workspace/coverage/default/2.chip_sw_alert_handler_escalation.3220201068			Aug 07 08:13:00 PM PDT 24	Aug 07 08:26:32 PM PDT 24	5985255390 ps
T395	/workspace/coverage/default/0.chip_sw_rstmgr_sw_rst.1191421431			Aug 07 07:55:03 PM PDT 24	Aug 07 08:00:25 PM PDT 24	3091198220 ps
T365	/workspace/coverage/default/60.chip_sw_all_escalation_resets.783259834			Aug 07 08:29:09 PM PDT 24	Aug 07 08:39:42 PM PDT 24	6027957144 ps
T933	/workspace/coverage/default/9.chip_sw_csrng_edn_concurrency.1401776569			Aug 07 08:25:57 PM PDT 24	Aug 07 09:42:44 PM PDT 24	22255491300 ps
T248	/workspace/coverage/default/89.chip_sw_all_escalation_resets.1342874874			Aug 07 08:31:52 PM PDT 24	Aug 07 08:44:12 PM PDT 24	4574872096 ps
T359	/workspace/coverage/default/55.chip_sw_all_escalation_resets.1724671535			Aug 07 08:27:30 PM PDT 24	Aug 07 08:41:56 PM PDT 24	5624410322 ps
T180	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_lc.1036079661			Aug 07 08:07:22 PM PDT 24	Aug 07 08:18:56 PM PDT 24	9091311479 ps
T271	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.2987200632			Aug 07 08:04:12 PM PDT 24	Aug 07 09:30:34 PM PDT 24	18190019272 ps
T178	/workspace/coverage/default/1.chip_sw_flash_init_reduced_freq.4004399761			Aug 07 08:07:43 PM PDT 24	Aug 07 08:51:35 PM PDT 24	20334768236 ps
T934	/workspace/coverage/default/1.chip_sw_csrng_edn_concurrency.137755555			Aug 07 08:03:50 PM PDT 24	Aug 07 09:22:46 PM PDT 24	18782523400 ps
T753	/workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.1510331958			Aug 07 08:23:00 PM PDT 24	Aug 07 08:30:47 PM PDT 24	3619506272 ps
T231	/workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.3822597670			Aug 07 07:52:59 PM PDT 24	Aug 07 09:17:01 PM PDT 24	15640830704 ps
T29	/workspace/coverage/default/1.chip_sw_gpio.2427456150			Aug 07 07:56:41 PM PDT 24	Aug 07 08:03:24 PM PDT 24	4030648026 ps
T324	/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.2121420880			Aug 07 07:57:55 PM PDT 24	Aug 07 08:10:21 PM PDT 24	4595490776 ps
T935	/workspace/coverage/default/1.chip_sw_uart_smoketest.758983748			Aug 07 08:09:49 PM PDT 24	Aug 07 08:14:18 PM PDT 24	3500333570 ps
T75	/workspace/coverage/default/0.chip_tap_straps_rma.1230141038			Aug 07 07:55:37 PM PDT 24	Aug 07 08:11:35 PM PDT 24	9018354944 ps
T764	/workspace/coverage/default/50.chip_sw_all_escalation_resets.2275468451			Aug 07 08:27:01 PM PDT 24	Aug 07 08:38:53 PM PDT 24	5876832514 ps
T133	/workspace/coverage/default/2.chip_sw_edn_kat.4011059429			Aug 07 08:14:48 PM PDT 24	Aug 07 08:24:32 PM PDT 24	3222623780 ps
T73	/workspace/coverage/default/0.chip_jtag_csr_rw.291715905			Aug 07 07:45:42 PM PDT 24	Aug 07 08:02:39 PM PDT 24	10489678480 ps
T25	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.2684189147			Aug 07 08:00:39 PM PDT 24	Aug 07 08:26:49 PM PDT 24	22184022776 ps
T369	/workspace/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.4120154691			Aug 07 07:52:35 PM PDT 24	Aug 07 07:59:38 PM PDT 24	3347660296 ps
T181	/workspace/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.593573309			Aug 07 07:52:26 PM PDT 24	Aug 07 07:54:35 PM PDT 24	3330645536 ps
T123	/workspace/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.994482256			Aug 07 08:03:47 PM PDT 24	Aug 07 08:18:29 PM PDT 24	5811580064 ps
T936	/workspace/coverage/default/2.chip_sw_kmac_smoketest.120965854			Aug 07 08:19:18 PM PDT 24	Aug 07 08:23:31 PM PDT 24	2325994560 ps
T937	/workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.2964824197			Aug 07 08:30:27 PM PDT 24	Aug 07 08:36:37 PM PDT 24	3738242904 ps
T362	/workspace/coverage/default/6.chip_sw_uart_rand_baudrate.1960092356			Aug 07 08:22:14 PM PDT 24	Aug 07 08:32:10 PM PDT 24	4024010280 ps
T410	/workspace/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.2473940322			Aug 07 08:19:55 PM PDT 24	Aug 07 08:25:27 PM PDT 24	4657756080 ps
T787	/workspace/coverage/default/53.chip_sw_all_escalation_resets.2608674636			Aug 07 08:28:05 PM PDT 24	Aug 07 08:37:16 PM PDT 24	4866161788 ps
T192	/workspace/coverage/default/2.chip_sw_csrng_fuse_en_sw_app_read_test.2677232165			Aug 07 08:13:14 PM PDT 24	Aug 07 08:25:26 PM PDT 24	5462652148 ps
T938	/workspace/coverage/default/1.chip_sw_flash_ctrl_access.1476321399			Aug 07 07:57:25 PM PDT 24	Aug 07 08:12:59 PM PDT 24	5289474620 ps
T311	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.1744979800			Aug 07 07:53:57 PM PDT 24	Aug 07 08:26:55 PM PDT 24	9202720504 ps
T789	/workspace/coverage/default/0.chip_sw_flash_crash_alert.747852613			Aug 07 07:56:40 PM PDT 24	Aug 07 08:07:34 PM PDT 24	4417702672 ps
T558	/workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.1151564603			Aug 07 07:53:14 PM PDT 24	Aug 07 08:04:39 PM PDT 24	7750094908 ps
T752	/workspace/coverage/default/0.chip_sw_sleep_pwm_pulses.3736655338			Aug 07 07:51:18 PM PDT 24	Aug 07 08:18:37 PM PDT 24	8914949000 ps
T233	/workspace/coverage/default/2.chip_sw_keymgr_sideload_otbn.1101223335			Aug 07 08:14:31 PM PDT 24	Aug 07 09:23:10 PM PDT 24	14795162566 ps
T259	/workspace/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.1580839169			Aug 07 08:18:31 PM PDT 24	Aug 07 08:26:17 PM PDT 24	4341911346 ps
T760	/workspace/coverage/default/1.chip_sw_clkmgr_reset_frequency.3335787631			Aug 07 08:07:28 PM PDT 24	Aug 07 08:14:29 PM PDT 24	3728357544 ps
T716	/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_por_reset.53121669			Aug 07 08:00:08 PM PDT 24	Aug 07 08:10:35 PM PDT 24	5496618650 ps
T216	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.3814889272			Aug 07 07:53:15 PM PDT 24	Aug 07 08:23:47 PM PDT 24	7927329366 ps
T237	/workspace/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.229890263			Aug 07 07:51:05 PM PDT 24	Aug 07 07:58:05 PM PDT 24	4750876116 ps
T396	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.947168164			Aug 07 08:01:24 PM PDT 24	Aug 07 09:55:56 PM PDT 24	23359058420 ps
T708	/workspace/coverage/default/95.chip_sw_all_escalation_resets.858196365			Aug 07 08:31:26 PM PDT 24	Aug 07 08:40:43 PM PDT 24	5360129474 ps
T401	/workspace/coverage/default/0.chip_sw_usb_ast_clk_calib.848366504			Aug 07 07:53:20 PM PDT 24	Aug 07 07:57:43 PM PDT 24	3038066273 ps
T364	/workspace/coverage/default/36.chip_sw_all_escalation_resets.4055220373			Aug 07 08:26:45 PM PDT 24	Aug 07 08:40:43 PM PDT 24	4419383720 ps
T939	/workspace/coverage/default/1.chip_sw_lc_ctrl_transition.2566699360			Aug 07 07:59:43 PM PDT 24	Aug 07 08:18:48 PM PDT 24	12135267321 ps
T940	/workspace/coverage/default/0.chip_sw_rstmgr_sw_req.3815721236			Aug 07 07:51:32 PM PDT 24	Aug 07 08:01:27 PM PDT 24	4170657200 ps
T749	/workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.1844398837			Aug 07 08:28:42 PM PDT 24	Aug 07 08:34:57 PM PDT 24	4171531490 ps
T559	/workspace/coverage/default/2.chip_sw_otp_ctrl_smoketest.1471605354			Aug 07 08:20:32 PM PDT 24	Aug 07 08:24:22 PM PDT 24	2333480120 ps
T941	/workspace/coverage/default/2.chip_sw_hmac_smoketest.1002798681			Aug 07 08:19:47 PM PDT 24	Aug 07 08:26:21 PM PDT 24	3665184264 ps
T942	/workspace/coverage/default/0.chip_sw_pwrmgr_wdog_reset.115795577			Aug 07 07:51:30 PM PDT 24	Aug 07 08:01:14 PM PDT 24	4193756360 ps
T37	/workspace/coverage/default/0.chip_sw_spi_host_tx_rx.1550419700			Aug 07 07:50:38 PM PDT 24	Aug 07 07:55:51 PM PDT 24	2891972060 ps
T332	/workspace/coverage/default/4.chip_sw_uart_rand_baudrate.2592750632			Aug 07 08:21:00 PM PDT 24	Aug 07 08:30:41 PM PDT 24	4245565544 ps
T943	/workspace/coverage/default/2.chip_sw_clkmgr_sleep_frequency.2844996413			Aug 07 08:16:04 PM PDT 24	Aug 07 08:27:23 PM PDT 24	4404759040 ps
T10	/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.1545278496			Aug 07 07:51:53 PM PDT 24	Aug 07 07:56:34 PM PDT 24	3159288666 ps
T944	/workspace/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.3729466983			Aug 07 08:01:53 PM PDT 24	Aug 07 08:27:18 PM PDT 24	8672001800 ps
T244	/workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.2923813657			Aug 07 08:31:01 PM PDT 24	Aug 07 08:37:36 PM PDT 24	3307714380 ps
T193	/workspace/coverage/default/1.chip_sw_csrng_fuse_en_sw_app_read_test.98111130			Aug 07 08:03:37 PM PDT 24	Aug 07 08:11:46 PM PDT 24	5109350210 ps
T751	/workspace/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.206257684			Aug 07 08:16:15 PM PDT 24	Aug 07 08:27:11 PM PDT 24	4692842368 ps
T945	/workspace/coverage/default/2.chip_sw_aes_smoketest.30580428			Aug 07 08:21:27 PM PDT 24	Aug 07 08:27:34 PM PDT 24	2328204734 ps
T946	/workspace/coverage/default/2.chip_sw_csrng_smoketest.1743977275			Aug 07 08:19:40 PM PDT 24	Aug 07 08:24:09 PM PDT 24	3142491710 ps
T84	/workspace/coverage/default/2.chip_jtag_mem_access.590736108			Aug 07 08:09:18 PM PDT 24	Aug 07 08:35:46 PM PDT 24	14326924758 ps
T187	/workspace/coverage/default/1.chip_sw_sram_ctrl_execution_main.451455902			Aug 07 08:04:21 PM PDT 24	Aug 07 08:19:41 PM PDT 24	6609668867 ps
T303	/workspace/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.896833185			Aug 07 07:52:38 PM PDT 24	Aug 07 08:02:17 PM PDT 24	5626896700 ps
T304	/workspace/coverage/default/1.chip_sw_rv_core_ibex_rnd.1178843613			Aug 07 08:02:33 PM PDT 24	Aug 07 08:21:39 PM PDT 24	5995297796 ps
T305	/workspace/coverage/default/96.chip_sw_all_escalation_resets.4000482079			Aug 07 08:31:38 PM PDT 24	Aug 07 08:43:36 PM PDT 24	5712437468 ps
T306	/workspace/coverage/default/0.chip_sw_example_flash.3798972425			Aug 07 07:53:33 PM PDT 24	Aug 07 07:56:18 PM PDT 24	3068481008 ps
T15	/workspace/coverage/default/1.chip_sw_spi_device_pass_through_collision.1559001851			Aug 07 07:59:39 PM PDT 24	Aug 07 08:09:04 PM PDT 24	4556243424 ps
T307	/workspace/coverage/default/0.chip_sw_alert_handler_ping_timeout.1640654586			Aug 07 07:52:23 PM PDT 24	Aug 07 08:01:23 PM PDT 24	4773839910 ps
T308	/workspace/coverage/default/81.chip_sw_all_escalation_resets.1631851423			Aug 07 08:31:37 PM PDT 24	Aug 07 08:40:55 PM PDT 24	4738527128 ps
T309	/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_prod.298192158			Aug 07 08:11:12 PM PDT 24	Aug 07 08:35:39 PM PDT 24	7400965720 ps
T310	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.377395542			Aug 07 08:02:50 PM PDT 24	Aug 07 09:49:21 PM PDT 24	24545677558 ps
T357	/workspace/coverage/default/2.chip_sw_pattgen_ios.2669766984			Aug 07 08:09:13 PM PDT 24	Aug 07 08:13:33 PM PDT 24	3045962386 ps
T762	/workspace/coverage/default/91.chip_sw_all_escalation_resets.1227646615			Aug 07 08:30:38 PM PDT 24	Aug 07 08:42:29 PM PDT 24	6178783688 ps
T947	/workspace/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.119246160			Aug 07 07:51:40 PM PDT 24	Aug 07 08:10:38 PM PDT 24	5350054193 ps
T948	/workspace/coverage/default/0.rom_e2e_smoke.2960466305			Aug 07 07:58:52 PM PDT 24	Aug 07 09:11:40 PM PDT 24	14881506448 ps
T333	/workspace/coverage/default/14.chip_sw_uart_rand_baudrate.1997962453			Aug 07 08:25:21 PM PDT 24	Aug 07 08:37:03 PM PDT 24	3888918100 ps
T222	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.2018316093			Aug 07 08:12:06 PM PDT 24	Aug 07 09:08:46 PM PDT 24	20986263067 ps
T824	/workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.2373259212			Aug 07 08:26:50 PM PDT 24	Aug 07 08:34:39 PM PDT 24	4414214340 ps
T457	/workspace/coverage/default/1.chip_sw_sram_ctrl_smoketest.2370953040			Aug 07 08:09:47 PM PDT 24	Aug 07 08:13:59 PM PDT 24	3461338770 ps
T949	/workspace/coverage/default/2.chip_sw_clkmgr_off_hmac_trans.992871879			Aug 07 08:16:27 PM PDT 24	Aug 07 08:23:21 PM PDT 24	5183935416 ps
T76	/workspace/coverage/default/3.chip_tap_straps_dev.3644794109			Aug 07 08:20:36 PM PDT 24	Aug 07 08:45:15 PM PDT 24	13152237260 ps
T272	/workspace/coverage/default/0.rom_e2e_shutdown_exception_c.1398671464			Aug 07 07:57:59 PM PDT 24	Aug 07 09:04:19 PM PDT 24	14812543430 ps
T950	/workspace/coverage/default/19.chip_sw_uart_rand_baudrate.2444556740			Aug 07 08:24:20 PM PDT 24	Aug 07 08:52:04 PM PDT 24	8068521812 ps
T87	/workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.3951492608			Aug 07 08:27:28 PM PDT 24	Aug 07 08:35:05 PM PDT 24	3805595862 ps
T97	/workspace/coverage/default/1.chip_sw_edn_kat.732786748			Aug 07 08:03:57 PM PDT 24	Aug 07 08:15:32 PM PDT 24	3609067640 ps
T98	/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.548837843			Aug 07 07:53:35 PM PDT 24	Aug 07 08:29:12 PM PDT 24	12478480411 ps
T99	/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.1870764165			Aug 07 08:19:16 PM PDT 24	Aug 07 08:27:51 PM PDT 24	5107402553 ps
T100	/workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.970402981			Aug 07 08:27:32 PM PDT 24	Aug 07 08:36:17 PM PDT 24	4392577940 ps
T101	/workspace/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.4194559938			Aug 07 07:52:22 PM PDT 24	Aug 07 08:00:27 PM PDT 24	5300012892 ps
T102	/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_prod.4077719764			Aug 07 08:05:39 PM PDT 24	Aug 07 08:42:32 PM PDT 24	10598957364 ps
T103	/workspace/coverage/default/2.chip_sw_flash_ctrl_mem_protection.1053506878			Aug 07 08:18:21 PM PDT 24	Aug 07 08:39:15 PM PDT 24	5412991112 ps
T104	/workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.2629595256			Aug 07 07:54:43 PM PDT 24	Aug 07 08:02:13 PM PDT 24	5185609760 ps
T105	/workspace/coverage/default/0.chip_sw_flash_ctrl_write_clear.2462678963			Aug 07 07:54:04 PM PDT 24	Aug 07 08:00:10 PM PDT 24	2628567800 ps
T951	/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_prod.1916534977			Aug 07 08:14:18 PM PDT 24	Aug 07 08:47:01 PM PDT 24	8024949176 ps
T952	/workspace/coverage/default/0.chip_sw_aes_entropy.319603909			Aug 07 07:51:38 PM PDT 24	Aug 07 07:55:30 PM PDT 24	2710278440 ps
T837	/workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.4044444511			Aug 07 08:25:24 PM PDT 24	Aug 07 08:35:02 PM PDT 24	4262487920 ps
T30	/workspace/coverage/default/0.chip_sw_gpio.1960504736			Aug 07 07:50:18 PM PDT 24	Aug 07 07:57:33 PM PDT 24	4497948400 ps
T953	/workspace/coverage/default/1.chip_sw_otp_ctrl_smoketest.2107955941			Aug 07 08:09:20 PM PDT 24	Aug 07 08:15:04 PM PDT 24	2980710308 ps
T954	/workspace/coverage/default/2.chip_sw_edn_entropy_reqs.2725524334			Aug 07 08:14:18 PM PDT 24	Aug 07 08:31:15 PM PDT 24	6307687040 ps
T250	/workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.3479544401			Aug 07 08:27:17 PM PDT 24	Aug 07 08:33:38 PM PDT 24	3259449710 ps
T289	/workspace/coverage/default/10.chip_sw_lc_ctrl_transition.2716206207			Aug 07 08:25:04 PM PDT 24	Aug 07 08:33:46 PM PDT 24	6212321013 ps
T38	/workspace/coverage/default/1.chip_sw_spi_host_tx_rx.124648439			Aug 07 07:57:07 PM PDT 24	Aug 07 08:01:46 PM PDT 24	3238903920 ps
T153	/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.451703197			Aug 07 07:52:28 PM PDT 24	Aug 07 08:55:16 PM PDT 24	16710774404 ps
T290	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2318763925			Aug 07 07:53:09 PM PDT 24	Aug 07 08:14:57 PM PDT 24	17728536194 ps
T291	/workspace/coverage/default/1.chip_sw_clkmgr_sleep_frequency.3977545363			Aug 07 08:05:29 PM PDT 24	Aug 07 08:16:34 PM PDT 24	5542159102 ps
T156	/workspace/coverage/default/0.chip_sw_exit_test_unlocked_bootstrap.235699448			Aug 07 07:51:37 PM PDT 24	Aug 07 10:57:12 PM PDT 24	58729672243 ps
T292	/workspace/coverage/default/0.chip_sw_aes_enc.1966618000			Aug 07 07:52:43 PM PDT 24	Aug 07 07:57:11 PM PDT 24	3346940184 ps
T293	/workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.2935350875			Aug 07 08:04:20 PM PDT 24	Aug 07 08:18:06 PM PDT 24	8652878568 ps
T294	/workspace/coverage/default/8.chip_sw_lc_ctrl_transition.618040374			Aug 07 08:22:15 PM PDT 24	Aug 07 08:40:22 PM PDT 24	9384886698 ps
T31	/workspace/coverage/default/2.chip_sw_gpio.767361904			Aug 07 08:09:33 PM PDT 24	Aug 07 08:18:14 PM PDT 24	4061083992 ps
T955	/workspace/coverage/default/5.chip_sw_lc_ctrl_transition.3125730802			Aug 07 08:21:13 PM PDT 24	Aug 07 08:30:07 PM PDT 24	6161941656 ps
T188	/workspace/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.50539268			Aug 07 08:18:36 PM PDT 24	Aug 07 08:23:48 PM PDT 24	2682266399 ps
T88	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.2605346577			Aug 07 08:16:03 PM PDT 24	Aug 07 08:36:02 PM PDT 24	10658646578 ps
T298	/workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.3332605344			Aug 07 08:21:14 PM PDT 24	Aug 07 08:30:14 PM PDT 24	4120924356 ps
T182	/workspace/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.4020410416			Aug 07 07:51:24 PM PDT 24	Aug 07 07:55:52 PM PDT 24	3512264425 ps
T26	/workspace/coverage/default/0.chip_sw_usbdev_stream.613807873			Aug 07 07:50:42 PM PDT 24	Aug 07 08:48:28 PM PDT 24	18737799498 ps