Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__regs_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	171355	1			T81	84		T82	463		T85	76
values[2]	4649	1			T81	1		T82	51		T85	4
values[3]	2214	1			T82	19		T645	1		T724	72
values[4]	1672	1			T82	29		T724	38		T684	73
values[5]	1394	1			T82	23		T724	38		T684	65
values[6]	1280	1			T82	21		T724	14		T684	65
values[7]	1106	1			T82	16		T724	6		T684	52
values[8]	978	1			T82	6		T724	20		T684	62
values[9]	1024	1			T82	17		T724	16		T684	67
values[10]	825	1			T82	30		T724	8		T684	40
values[11]	765	1			T82	29		T724	1		T684	43
values[12]	656	1			T82	39		T684	33		T888	1
values[13]	618	1			T82	27		T684	23		T888	1
values[14]	630	1			T82	27		T684	33		T888	1
values[15]	699	1			T82	54		T684	42		T888	1
values[16]	591	1			T82	39		T684	33		T888	1
values[17]	597	1			T82	34		T684	35		T888	1
values[18]	521	1			T82	20		T684	30		T888	1
values[19]	470	1			T82	20		T684	22		T888	1
values[20]	472	1			T82	12		T684	26		T888	1
values[21]	387	1			T82	2		T684	25		T888	1
values[22]	361	1			T684	35		T888	1		T481	1
values[23]	283	1			T684	16		T888	1		T481	1
values[24]	235	1			T684	12		T888	1		T481	1
values[25]	198	1			T684	10		T888	1		T481	1
values[26]	210	1			T684	16		T888	1		T481	1
values[27]	196	1			T684	6		T888	1		T481	1
values[28]	162	1			T684	1		T888	1		T481	1
values[29]	172	1			T888	1		T481	1		T536	3
values[30]	186	1			T888	1		T481	1		T536	3
values[31]	171	1			T888	1		T481	1		T536	3
values[32]	183	1			T888	1		T481	1		T536	4
values[33]	188	1			T888	1		T481	1		T536	3
values[34]	169	1			T888	1		T481	1		T536	2
values[35]	159	1			T888	1		T481	1		T536	1
values[36]	165	1			T888	1		T481	1		T536	1
values[37]	162	1			T888	1		T481	1		T536	1
values[38]	170	1			T888	1		T481	1		T536	4
values[39]	104	1			T888	1		T481	1		T536	1
values[40]	118	1			T888	1		T481	1		T536	2
values[41]	145	1			T888	1		T481	2		T536	3
values[42]	169	1			T888	1		T481	1		T536	1
values[43]	160	1			T888	1		T481	1		T536	2
values[44]	131	1			T888	1		T481	1		T536	3
values[45]	96	1			T888	1		T481	1		T536	2
values[46]	96	1			T888	1		T481	1		T536	1
values[47]	90	1			T888	1		T481	1		T536	3
values[48]	76	1			T888	1		T481	1		T536	1
values[49]	106	1			T888	1		T481	1		T536	4
values[50]	100	1			T888	1		T481	1		T536	4
values[51]	86	1			T888	1		T481	1		T536	4
values[52]	89	1			T888	1		T481	1		T536	2
values[53]	85	1			T888	1		T481	1		T536	1
values[54]	79	1			T888	1		T481	1		T536	2
values[55]	108	1			T888	1		T481	1		T536	4
values[56]	99	1			T888	1		T481	1		T536	2
values[57]	104	1			T888	1		T481	1		T536	5
values[58]	73	1			T888	1		T481	1		T536	5
values[59]	62	1			T888	1		T481	1		T536	2
values[60]	70	1			T888	1		T481	1		T536	1
values[61]	68	1			T888	1		T481	1		T536	1
values[62]	59	1			T888	1		T481	1		T536	3
values[63]	70	1			T888	1		T481	1		T536	1
values[64]	77	1			T888	1		T481	1		T536	1
values[65]	70	1			T888	1		T481	1		T536	2
values[66]	95	1			T888	1		T481	1		T536	4
values[67]	64	1			T888	1		T481	1		T536	1
values[68]	78	1			T888	1		T481	1		T536	4
values[69]	78	1			T888	1		T481	1		T536	5
values[70]	75	1			T888	1		T481	1		T536	1
values[71]	77	1			T888	1		T481	1		T536	4
values[72]	74	1			T888	1		T481	1		T536	6
values[73]	83	1			T888	1		T481	1		T536	8
values[74]	80	1			T888	2		T481	1		T536	4
values[75]	79	1			T888	1		T481	1		T536	6
values[76]	78	1			T888	1		T481	1		T536	2
values[77]	86	1			T888	1		T481	3		T536	2
values[78]	82	1			T888	1		T481	2		T536	1
values[79]	89	1			T888	1		T481	7		T536	3
values[80]	106	1			T888	1		T481	11		T536	5
values[81]	96	1			T888	1		T481	10		T536	9
values[82]	82	1			T888	1		T481	2		T536	7
values[83]	78	1			T888	1		T481	1		T536	1
values[84]	77	1			T888	1		T481	5		T536	1
values[85]	80	1			T888	1		T481	7		T536	3
values[86]	75	1			T888	1		T481	7		T536	6
values[87]	75	1			T888	1		T481	4		T536	2
values[88]	76	1			T888	1		T481	4		T536	2
values[89]	86	1			T888	1		T481	5		T536	2
values[90]	86	1			T888	1		T481	4		T536	4
values[91]	86	1			T888	1		T481	1		T536	4
values[92]	74	1			T888	1		T481	5		T536	1
values[93]	85	1			T888	1		T481	6		T536	1
values[94]	91	1			T888	1		T481	2		T536	6
values[95]	102	1			T888	1		T481	1		T536	10
values[96]	90	1			T888	1		T481	4		T536	6
values[97]	85	1			T888	1		T481	6		T536	5
values[98]	115	1			T888	1		T481	5		T536	5
values[99]	81	1			T888	1		T481	7		T536	2
values[100]	97	1			T888	1		T481	6		T536	5
values[101]	86	1			T888	1		T481	1		T536	8
values[102]	110	1			T888	1		T481	3		T536	5
values[103]	97	1			T888	1		T481	1		T536	5
values[104]	96	1			T888	1		T481	2		T536	10
values[105]	95	1			T888	1		T481	1		T536	3
values[106]	116	1			T888	1		T481	1		T536	1
values[107]	106	1			T888	1		T481	2		T536	8
values[108]	117	1			T888	2		T481	1		T536	4
values[109]	123	1			T888	4		T481	2		T536	3
values[110]	100	1			T888	3		T481	1		T536	6
values[111]	110	1			T888	1		T481	3		T536	6
values[112]	121	1			T888	2		T481	2		T536	6
values[113]	110	1			T888	2		T481	1		T536	2
values[114]	107	1			T888	2		T481	1		T536	2
values[115]	131	1			T888	1		T481	2		T536	3
values[116]	121	1			T888	3		T481	5		T536	3
values[117]	132	1			T888	1		T481	1		T536	4
values[118]	151	1			T888	2		T481	1		T536	4
values[119]	128	1			T888	6		T481	1		T536	4
values[120]	129	1			T888	4		T481	1		T536	10
values[121]	152	1			T888	7		T481	1		T536	8
values[122]	150	1			T888	5		T481	1		T536	2
values[123]	173	1			T888	1		T481	2		T536	9
values[124]	207	1			T888	2		T481	2		T536	9
values[125]	371	1			T888	2		T481	2		T536	19
values[126]	817	1			T888	16		T481	17		T536	56
values[127]	3210	1			T888	111		T481	93		T536	43
values[128]	5567	1			T888	189		T481	164		T536	3