Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.uart0_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	143008	1			T81	118		T82	391		T85	96
values[2]	8287	1			T81	9		T82	9		T253	1
values[3]	2941	1			T560	10		T571	1		T724	3
values[4]	1757	1			T560	5		T724	9		T422	40
values[5]	1078	1			T560	2		T724	8		T422	23
values[6]	803	1			T560	1		T724	4		T422	11
values[7]	706	1			T560	1		T724	1		T422	4
values[8]	575	1			T560	1		T724	1		T422	3
values[9]	580	1			T560	2		T724	2		T456	13
values[10]	487	1			T560	2		T724	3		T456	4
values[11]	429	1			T560	4		T724	2		T456	6
values[12]	424	1			T560	2		T724	1		T456	7
values[13]	405	1			T560	6		T724	2		T456	7
values[14]	385	1			T560	1		T724	1		T456	4
values[15]	370	1			T560	1		T724	5		T456	10
values[16]	326	1			T560	2		T724	6		T456	5
values[17]	354	1			T560	1		T724	1		T456	9
values[18]	378	1			T560	1		T724	1		T456	6
values[19]	353	1			T560	2		T724	2		T456	12
values[20]	380	1			T560	3		T724	4		T456	3
values[21]	393	1			T560	4		T724	3		T456	8
values[22]	372	1			T560	4		T724	1		T456	8
values[23]	442	1			T560	3		T724	6		T456	13
values[24]	410	1			T560	1		T724	3		T456	6
values[25]	336	1			T560	4		T724	2		T456	4
values[26]	363	1			T560	8		T724	3		T456	5
values[27]	323	1			T560	5		T724	1		T456	4
values[28]	320	1			T560	2		T724	2		T456	14
values[29]	328	1			T560	4		T724	1		T456	3
values[30]	349	1			T560	1		T724	2		T456	12
values[31]	380	1			T560	5		T724	3		T456	5
values[32]	398	1			T560	4		T724	11		T456	8
values[33]	339	1			T560	2		T724	4		T456	4
values[34]	381	1			T560	1		T724	4		T456	8
values[35]	365	1			T560	2		T724	3		T456	2
values[36]	355	1			T560	3		T724	2		T456	3
values[37]	337	1			T560	2		T724	2		T456	8
values[38]	393	1			T560	3		T724	2		T456	7
values[39]	360	1			T560	5		T724	2		T456	11
values[40]	367	1			T560	1		T724	2		T456	4
values[41]	360	1			T560	2		T724	4		T456	8
values[42]	315	1			T560	2		T724	4		T456	7
values[43]	335	1			T560	1		T724	4		T456	9
values[44]	337	1			T560	5		T724	1		T456	5
values[45]	326	1			T560	4		T724	1		T456	6
values[46]	357	1			T560	5		T724	7		T456	19
values[47]	357	1			T560	3		T724	3		T456	19
values[48]	319	1			T560	2		T724	1		T456	13
values[49]	315	1			T560	7		T724	1		T456	10
values[50]	327	1			T560	6		T724	2		T456	6
values[51]	314	1			T560	20		T724	3		T456	7
values[52]	342	1			T560	8		T724	1		T456	3
values[53]	334	1			T560	1		T724	1		T467	14
values[54]	295	1			T560	1		T724	2		T467	6
values[55]	323	1			T560	4		T724	6		T467	10
values[56]	300	1			T560	1		T724	4		T467	5
values[57]	319	1			T560	6		T724	1		T467	8
values[58]	262	1			T560	4		T724	4		T467	9
values[59]	245	1			T560	2		T724	4		T467	10
values[60]	253	1			T560	2		T724	3		T467	5
values[61]	228	1			T560	3		T724	3		T467	17
values[62]	209	1			T560	3		T724	3		T467	2
values[63]	201	1			T560	3		T724	13		T467	3
values[64]	199	1			T560	3		T724	8		T887	8
values[65]	172	1			T560	1		T724	7		T887	6
values[66]	203	1			T560	5		T724	6		T887	19
values[67]	133	1			T560	1		T724	6		T887	4
values[68]	190	1			T560	3		T724	1		T887	3
values[69]	152	1			T560	1		T724	1		T887	4
values[70]	142	1			T560	3		T724	5		T887	6
values[71]	145	1			T560	6		T724	3		T887	10
values[72]	91	1			T560	3		T724	1		T887	4
values[73]	91	1			T560	1		T724	4		T481	1
values[74]	85	1			T560	3		T724	1		T481	1
values[75]	82	1			T560	6		T724	4		T481	1
values[76]	82	1			T560	5		T724	3		T481	1
values[77]	100	1			T560	8		T724	4		T481	1
values[78]	92	1			T560	1		T724	10		T481	1
values[79]	84	1			T560	1		T724	5		T481	1
values[80]	78	1			T560	3		T724	4		T481	1
values[81]	123	1			T560	2		T724	21		T481	1
values[82]	103	1			T560	2		T724	14		T481	1
values[83]	95	1			T560	5		T724	4		T481	1
values[84]	97	1			T560	4		T724	5		T481	1
values[85]	104	1			T560	2		T724	9		T481	1
values[86]	127	1			T560	11		T724	9		T481	1
values[87]	101	1			T560	9		T724	2		T481	1
values[88]	95	1			T560	7		T724	3		T481	1
values[89]	84	1			T560	3		T724	4		T481	1
values[90]	79	1			T560	2		T724	4		T481	1
values[91]	85	1			T560	3		T724	6		T481	1
values[92]	89	1			T560	5		T724	8		T481	1
values[93]	80	1			T560	3		T724	4		T481	1
values[94]	82	1			T560	1		T724	2		T481	2
values[95]	86	1			T560	5		T724	6		T481	3
values[96]	70	1			T560	4		T724	3		T481	3
values[97]	70	1			T560	5		T724	2		T481	1
values[98]	82	1			T560	3		T724	5		T481	4
values[99]	82	1			T560	10		T724	3		T481	4
values[100]	92	1			T560	5		T724	4		T481	4
values[101]	89	1			T560	1		T724	7		T481	1
values[102]	96	1			T560	5		T724	4		T481	4
values[103]	101	1			T560	3		T724	7		T481	3
values[104]	90	1			T560	4		T724	8		T481	2
values[105]	91	1			T560	2		T724	11		T481	2
values[106]	92	1			T560	2		T724	7		T481	2
values[107]	97	1			T560	3		T724	1		T481	1
values[108]	90	1			T560	12		T481	1		T870	2
values[109]	82	1			T560	3		T481	1		T870	3
values[110]	73	1			T560	5		T481	1		T870	2
values[111]	79	1			T560	6		T481	1		T870	2
values[112]	81	1			T560	4		T481	3		T870	4
values[113]	88	1			T560	2		T481	2		T870	2
values[114]	93	1			T560	3		T481	1		T870	4
values[115]	89	1			T560	3		T481	3		T870	6
values[116]	75	1			T560	2		T481	1		T870	3
values[117]	87	1			T560	3		T481	1		T870	9
values[118]	68	1			T560	7		T481	1		T870	1
values[119]	84	1			T560	11		T481	4		T870	3
values[120]	68	1			T560	3		T481	1		T870	2
values[121]	61	1			T560	3		T481	3		T870	3
values[122]	55	1			T560	8		T481	1		T870	2
values[123]	89	1			T560	14		T481	1		T870	2
values[124]	74	1			T560	6		T481	1		T870	8
values[125]	92	1			T560	4		T481	1		T870	9
values[126]	120	1			T560	4		T481	1		T870	11
values[127]	600	1			T560	1		T481	27		T870	25
values[128]	4104	1			T481	307		T870	17		T879	2