Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.usbdev_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	148359	1			T81	240		T82	461		T85	107
values[2]	9762	1			T81	146		T82	108		T85	2
values[3]	4920	1			T81	129		T82	102		T461	70
values[4]	2822	1			T81	57		T82	56		T461	64
values[5]	1879	1			T81	4		T82	15		T461	57
values[6]	1392	1			T81	1		T82	1		T461	41
values[7]	1134	1			T461	24		T467	17		T873	1
values[8]	987	1			T461	11		T467	4		T873	1
values[9]	858	1			T467	15		T873	1		T546	33
values[10]	744	1			T467	13		T873	1		T546	17
values[11]	713	1			T873	1		T766	7		T497	5
values[12]	578	1			T873	1		T766	4		T497	15
values[13]	582	1			T873	1		T766	14		T497	3
values[14]	628	1			T873	1		T766	25		T497	9
values[15]	574	1			T873	1		T766	6		T497	18
values[16]	648	1			T873	1		T766	3		T497	6
values[17]	597	1			T873	1		T766	10		T497	13
values[18]	622	1			T873	1		T766	17		T497	9
values[19]	631	1			T873	1		T766	23		T497	7
values[20]	525	1			T873	1		T766	5		T497	7
values[21]	539	1			T873	1		T766	4		T497	20
values[22]	523	1			T873	1		T766	9		T497	5
values[23]	590	1			T873	1		T766	8		T497	7
values[24]	534	1			T873	1		T766	14		T497	6
values[25]	505	1			T873	1		T766	5		T497	8
values[26]	469	1			T873	1		T766	12		T497	11
values[27]	527	1			T873	1		T766	7		T497	4
values[28]	584	1			T873	1		T766	11		T497	4
values[29]	470	1			T873	1		T766	7		T896	3
values[30]	517	1			T873	1		T766	26		T896	10
values[31]	535	1			T873	2		T766	17		T896	18
values[32]	553	1			T873	1		T766	13		T896	14
values[33]	566	1			T873	1		T766	4		T896	15
values[34]	535	1			T873	1		T766	5		T896	14
values[35]	462	1			T873	1		T766	27		T896	7
values[36]	526	1			T873	1		T766	13		T896	9
values[37]	457	1			T873	1		T766	13		T896	8
values[38]	538	1			T873	1		T766	10		T896	6
values[39]	479	1			T873	1		T766	9		T896	12
values[40]	433	1			T873	1		T766	5		T896	6
values[41]	481	1			T873	1		T766	11		T896	12
values[42]	457	1			T873	1		T766	6		T896	3
values[43]	423	1			T873	1		T766	9		T896	4
values[44]	292	1			T873	1		T766	8		T896	4
values[45]	321	1			T873	1		T766	16		T896	8
values[46]	351	1			T873	1		T766	9		T896	4
values[47]	268	1			T873	1		T766	8		T896	13
values[48]	275	1			T873	1		T766	7		T887	13
values[49]	257	1			T873	1		T887	8		T505	16
values[50]	155	1			T873	1		T887	4		T505	4
values[51]	177	1			T873	1		T887	1		T505	4
values[52]	202	1			T873	1		T505	7		T536	17
values[53]	127	1			T873	1		T505	7		T536	4
values[54]	135	1			T873	1		T505	20		T536	8
values[55]	157	1			T873	1		T505	4		T536	4
values[56]	123	1			T873	1		T505	3		T536	7
values[57]	105	1			T873	1		T505	5		T536	6
values[58]	85	1			T873	1		T505	7		T536	8
values[59]	130	1			T873	1		T505	19		T536	5
values[60]	93	1			T873	2		T536	7		T519	1
values[61]	79	1			T873	1		T536	9		T519	1
values[62]	101	1			T873	1		T536	6		T519	1
values[63]	71	1			T873	1		T536	5		T519	1
values[64]	99	1			T873	1		T536	15		T519	1
values[65]	115	1			T873	1		T536	23		T519	1
values[66]	90	1			T873	1		T536	12		T519	1
values[67]	70	1			T873	1		T536	5		T519	1
values[68]	88	1			T873	1		T536	6		T519	1
values[69]	68	1			T873	1		T536	7		T519	1
values[70]	59	1			T873	1		T536	4		T519	1
values[71]	66	1			T873	1		T536	6		T519	1
values[72]	55	1			T873	1		T536	7		T519	1
values[73]	73	1			T873	1		T536	6		T519	1
values[74]	60	1			T873	1		T536	2		T519	1
values[75]	91	1			T873	1		T536	4		T519	1
values[76]	106	1			T873	1		T536	18		T519	1
values[77]	119	1			T873	1		T536	17		T519	1
values[78]	102	1			T873	1		T536	16		T519	1
values[79]	123	1			T873	1		T536	18		T519	1
values[80]	98	1			T873	1		T536	2		T519	1
values[81]	81	1			T873	1		T536	5		T519	1
values[82]	77	1			T873	1		T536	9		T519	1
values[83]	84	1			T873	1		T536	2		T519	1
values[84]	66	1			T873	1		T536	3		T519	1
values[85]	59	1			T873	1		T536	1		T519	1
values[86]	58	1			T873	1		T536	3		T519	1
values[87]	51	1			T873	1		T536	4		T519	1
values[88]	65	1			T873	1		T536	6		T519	1
values[89]	83	1			T873	1		T536	12		T519	1
values[90]	91	1			T873	1		T536	18		T519	1
values[91]	82	1			T873	1		T536	3		T519	1
values[92]	59	1			T873	1		T536	3		T519	1
values[93]	61	1			T873	1		T536	5		T519	1
values[94]	71	1			T873	1		T536	3		T519	1
values[95]	50	1			T873	1		T519	1		T542	1
values[96]	54	1			T873	1		T519	1		T542	1
values[97]	37	1			T873	1		T519	1		T542	1
values[98]	56	1			T873	1		T519	1		T542	1
values[99]	54	1			T873	1		T519	1		T542	1
values[100]	80	1			T873	1		T519	1		T542	1
values[101]	62	1			T873	1		T519	1		T542	1
values[102]	41	1			T873	1		T519	1		T542	1
values[103]	56	1			T873	2		T519	1		T542	1
values[104]	48	1			T873	1		T519	3		T542	1
values[105]	55	1			T873	1		T519	3		T542	1
values[106]	64	1			T873	1		T519	1		T542	1
values[107]	59	1			T873	1		T519	1		T542	1
values[108]	55	1			T873	1		T519	3		T542	1
values[109]	47	1			T873	1		T519	1		T542	1
values[110]	57	1			T873	1		T519	1		T542	1
values[111]	68	1			T873	1		T519	2		T542	2
values[112]	57	1			T873	1		T519	2		T542	5
values[113]	55	1			T873	1		T519	1		T542	4
values[114]	52	1			T873	1		T519	3		T542	2
values[115]	41	1			T873	1		T519	1		T542	2
values[116]	41	1			T873	1		T519	1		T542	1
values[117]	45	1			T873	1		T519	3		T542	2
values[118]	48	1			T873	3		T519	2		T542	5
values[119]	51	1			T873	5		T519	1		T542	2
values[120]	45	1			T873	3		T519	5		T542	1
values[121]	51	1			T873	1		T519	3		T542	1
values[122]	60	1			T873	1		T519	3		T542	1
values[123]	49	1			T873	1		T519	4		T542	2
values[124]	43	1			T873	1		T519	2		T542	4
values[125]	54	1			T873	2		T519	1		T542	1
values[126]	96	1			T873	1		T519	5		T542	5
values[127]	973	1			T873	38		T519	51		T542	50
values[128]	4419	1			T873	240		T519	283		T542	288