Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	50	0	50	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	50	0	50	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	50	0	50	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	533	1			T81	3		T82	2		T724	1
all_values[1]	515	1			T81	6		T461	1		T494	1
all_values[2]	450	1			T81	6		T82	2		T495	2
all_values[3]	504	1			T81	4		T82	4		T461	1
all_values[4]	508	1			T81	4		T82	4		T495	2
all_values[5]	502	1			T81	4		T82	3		T494	1
all_values[6]	516	1			T81	5		T82	6		T461	1
all_values[7]	513	1			T81	6		T82	2		T461	1
all_values[8]	539	1			T81	4		T82	4		T495	2
all_values[9]	525	1			T81	1		T82	3		T569	4
all_values[10]	489	1			T81	5		T82	2		T494	1
all_values[11]	523	1			T81	4		T82	4		T461	2
all_values[12]	487	1			T81	1		T82	5		T495	1
all_values[13]	509	1			T81	5		T82	4		T495	3
all_values[14]	480	1			T81	4		T82	5		T494	1
all_values[15]	515	1			T81	3		T82	3		T495	1
all_values[16]	452	1			T81	3		T82	1		T495	2
all_values[17]	510	1			T81	6		T82	3		T461	1
all_values[18]	533	1			T81	3		T82	8		T495	1
all_values[19]	544	1			T81	2		T82	2		T495	2
all_values[20]	533	1			T81	3		T82	8		T495	2
all_values[21]	467	1			T81	5		T82	6		T495	1
all_values[22]	491	1			T81	3		T82	3		T461	1
all_values[23]	470	1			T81	4		T82	1		T495	3
all_values[24]	495	1			T81	4		T82	4		T495	3
all_values[25]	501	1			T81	4		T82	4		T494	1
all_values[26]	520	1			T81	3		T82	3		T495	2
all_values[27]	465	1			T81	2		T82	1		T461	1
all_values[28]	512	1			T81	6		T82	1		T495	3
all_values[29]	500	1			T81	4		T82	6		T495	2
all_values[30]	485	1			T81	3		T82	5		T495	2
all_values[31]	496	1			T81	3		T82	7		T495	2
all_values[32]	572	1			T81	2		T82	5		T461	1
all_values[33]	498	1			T81	5		T82	6		T461	1
all_values[34]	492	1			T81	3		T82	2		T461	1
all_values[35]	489	1			T81	6		T82	6		T494	1
all_values[36]	467	1			T81	4		T82	3		T461	2
all_values[37]	549	1			T81	3		T82	2		T495	2
all_values[38]	498	1			T82	1		T495	4		T512	1
all_values[39]	537	1			T81	4		T82	3		T495	3
all_values[40]	490	1			T81	5		T82	2		T495	1
all_values[41]	453	1			T81	4		T82	6		T560	1
all_values[42]	502	1			T81	3		T82	3		T569	2
all_values[43]	490	1			T81	6		T82	2		T495	2
all_values[44]	501	1			T81	6		T494	1		T512	1
all_values[45]	492	1			T81	3		T82	2		T494	1
all_values[46]	507	1			T81	6		T82	3		T495	1
all_values[47]	523	1			T81	6		T82	3		T462	1
all_values[48]	476	1			T81	3		T82	2		T495	2
all_values[49]	487	1			T81	6		T82	9		T495	4