Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	3721	1			T81	23		T82	27		T253	2
all_values[1]	3700	1			T81	29		T82	28		T253	2
all_values[2]	3686	1			T81	18		T82	37		T495	15
all_values[3]	3692	1			T81	22		T82	28		T253	2
all_values[4]	3727	1			T81	11		T82	22		T253	2
all_values[5]	3764	1			T81	24		T82	25		T253	1
all_values[6]	3709	1			T81	16		T82	20		T253	2
all_values[7]	3850	1			T81	29		T82	27		T494	1
all_values[8]	3648	1			T81	12		T82	25		T253	1
all_values[9]	3762	1			T81	14		T82	32		T253	1
all_values[10]	3735	1			T81	20		T82	25		T253	1
all_values[11]	3713	1			T81	18		T82	24		T253	4
all_values[12]	3719	1			T81	17		T82	20		T253	5
all_values[13]	3782	1			T81	35		T82	32		T253	3
all_values[14]	3763	1			T81	18		T82	22		T253	2
all_values[15]	3825	1			T81	18		T82	23		T495	17
all_values[16]	3724	1			T81	27		T82	28		T494	1
all_values[17]	3731	1			T81	16		T82	30		T253	2
all_values[18]	3640	1			T81	22		T82	28		T253	3
all_values[19]	3752	1			T81	23		T82	33		T253	2
all_values[20]	3754	1			T81	17		T82	27		T253	2
all_values[21]	3753	1			T81	25		T82	24		T253	3
all_values[22]	3684	1			T81	28		T82	26		T253	1
all_values[23]	3664	1			T81	14		T82	16		T495	18
all_values[24]	3729	1			T81	27		T82	22		T253	2
all_values[25]	3691	1			T81	16		T82	21		T253	1
all_values[26]	3774	1			T81	17		T82	20		T495	24
all_values[27]	3761	1			T81	14		T82	20		T495	26
all_values[28]	3752	1			T81	14		T82	28		T253	1
all_values[29]	3649	1			T81	24		T82	18		T494	2
all_values[30]	3830	1			T81	21		T82	25		T253	1
all_values[31]	3766	1			T81	30		T82	29		T253	2
all_values[32]	3799	1			T81	18		T82	28		T253	3
all_values[33]	3845	1			T81	19		T82	14		T495	15
all_values[34]	3679	1			T81	24		T82	24		T253	1
all_values[35]	3794	1			T81	14		T82	23		T253	2
all_values[36]	3800	1			T81	18		T82	25		T495	14
all_values[37]	3781	1			T81	11		T82	26		T253	2
all_values[38]	3747	1			T81	18		T82	18		T253	1
all_values[39]	3738	1			T81	22		T82	25		T253	3
all_values[40]	3743	1			T81	23		T82	31		T253	1
all_values[41]	3860	1			T81	13		T82	25		T494	1
all_values[42]	3766	1			T81	13		T82	26		T253	2
all_values[43]	3729	1			T81	11		T82	26		T253	2
all_values[44]	3695	1			T81	25		T82	25		T494	1
all_values[45]	3768	1			T81	32		T82	26		T253	1
all_values[46]	3857	1			T81	18		T82	32		T495	16
all_values[47]	3785	1			T81	19		T82	32		T495	18
all_values[48]	3752	1			T81	31		T82	23		T495	11
all_values[49]	3783	1			T81	22		T82	26		T253	1
all_values[50]	3773	1			T81	17		T82	30		T253	1
all_values[51]	3722	1			T81	18		T82	29		T253	3
all_values[52]	3780	1			T81	22		T82	24		T495	18
all_values[53]	3749	1			T81	29		T82	26		T253	1
all_values[54]	3759	1			T81	17		T82	18		T253	4
all_values[55]	3775	1			T81	25		T82	28		T495	17
all_values[56]	3784	1			T81	20		T82	25		T253	1
all_values[57]	3856	1			T81	21		T82	26		T253	3
all_values[58]	3775	1			T81	20		T82	27		T494	1
all_values[59]	3727	1			T81	33		T82	20		T253	1
all_values[60]	3797	1			T81	19		T82	30		T253	1
all_values[61]	3755	1			T81	18		T82	19		T494	1
all_values[62]	3767	1			T81	16		T82	26		T253	1
all_values[63]	3719	1			T81	23		T82	26		T253	2