LINE 18005
EXPRESSION (addr_hit[200] & reg_we & ((!reg_error)))
------1------ ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|---|---|---|---|
| 0 | 1 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | 1 | Covered | T23,T747,T748 |
| 1 | 1 | 0 | Covered | T574,T572,T577 |
| 1 | 1 | 1 | Covered | T109,T23,T255 |
LINE 18008
EXPRESSION (addr_hit[201] & reg_we & ((!reg_error)))
------1------ ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|---|---|---|---|
| 0 | 1 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | 1 | Covered | T23,T80,T563 |
| 1 | 1 | 0 | Covered | T563,T587,T577 |
| 1 | 1 | 1 | Covered | T23,T55,T56 |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |