Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.gpio_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	141177	1			T80	8		T81	175		T82	10
values[2]	12122	1			T81	1		T516	76		T511	8
values[3]	5057	1			T516	14		T511	15		T515	29
values[4]	3033	1			T516	5		T511	5		T515	9
values[5]	2002	1			T516	3		T511	3		T515	8
values[6]	1277	1			T516	16		T511	2		T515	5
values[7]	871	1			T516	12		T511	4		T429	41
values[8]	575	1			T516	3		T511	11		T429	26
values[9]	446	1			T516	5		T511	4		T429	23
values[10]	312	1			T516	6		T511	3		T429	17
values[11]	277	1			T516	7		T511	4		T429	7
values[12]	248	1			T516	3		T511	15		T528	6
values[13]	210	1			T516	9		T511	8		T528	7
values[14]	175	1			T516	10		T511	7		T528	7
values[15]	155	1			T516	12		T511	4		T528	10
values[16]	170	1			T516	2		T511	5		T528	6
values[17]	161	1			T511	9		T528	4		T472	1
values[18]	128	1			T511	5		T528	2		T472	3
values[19]	192	1			T511	5		T528	4		T472	3
values[20]	153	1			T511	8		T528	7		T472	2
values[21]	148	1			T511	7		T528	3		T472	1
values[22]	144	1			T511	8		T528	1		T472	2
values[23]	169	1			T511	6		T528	2		T472	2
values[24]	129	1			T511	9		T528	3		T472	1
values[25]	156	1			T511	6		T528	2		T472	4
values[26]	144	1			T511	13		T528	2		T472	2
values[27]	158	1			T511	6		T528	2		T472	1
values[28]	173	1			T511	4		T528	3		T472	3
values[29]	171	1			T511	11		T528	1		T472	4
values[30]	143	1			T511	18		T528	2		T472	1
values[31]	147	1			T511	10		T528	3		T472	2
values[32]	142	1			T511	6		T528	3		T472	3
values[33]	168	1			T511	7		T528	3		T472	3
values[34]	117	1			T511	3		T528	1		T472	1
values[35]	144	1			T511	6		T528	3		T472	4
values[36]	132	1			T511	7		T528	2		T472	1
values[37]	136	1			T511	6		T528	2		T472	2
values[38]	136	1			T511	5		T528	1		T472	3
values[39]	129	1			T511	5		T528	1		T796	1
values[40]	143	1			T511	14		T528	3		T796	1
values[41]	131	1			T511	5		T528	3		T796	1
values[42]	129	1			T511	3		T528	3		T796	1
values[43]	145	1			T511	9		T528	1		T796	1
values[44]	125	1			T511	5		T528	2		T796	1
values[45]	136	1			T511	4		T528	3		T796	1
values[46]	152	1			T511	4		T528	3		T796	1
values[47]	133	1			T511	5		T528	4		T796	1
values[48]	142	1			T511	5		T528	3		T796	1
values[49]	127	1			T511	13		T528	3		T796	1
values[50]	131	1			T511	5		T528	5		T796	1
values[51]	131	1			T511	6		T528	2		T796	1
values[52]	135	1			T511	16		T528	6		T796	1
values[53]	105	1			T511	10		T528	2		T796	1
values[54]	94	1			T511	9		T796	2		T797	3
values[55]	108	1			T511	3		T796	1		T797	9
values[56]	123	1			T796	1		T797	20		T798	4
values[57]	124	1			T796	1		T797	10		T798	3
values[58]	87	1			T796	1		T797	3		T798	5
values[59]	73	1			T796	1		T797	4		T798	4
values[60]	91	1			T796	1		T797	5		T798	12
values[61]	95	1			T796	1		T797	20		T798	8
values[62]	94	1			T796	1		T797	7		T798	8
values[63]	80	1			T796	1		T797	5		T798	4
values[64]	84	1			T796	1		T797	9		T798	11
values[65]	98	1			T796	1		T797	3		T798	22
values[66]	76	1			T796	1		T798	16		T499	1
values[67]	73	1			T796	1		T798	11		T499	1
values[68]	124	1			T796	1		T798	15		T499	4
values[69]	89	1			T796	1		T798	17		T499	12
values[70]	59	1			T796	1		T798	18		T499	10
values[71]	65	1			T796	1		T798	16		T499	8
values[72]	63	1			T796	1		T798	23		T499	3
values[73]	47	1			T796	1		T798	5		T499	1
values[74]	72	1			T796	1		T798	4		T499	6
values[75]	64	1			T796	1		T798	13		T499	4
values[76]	83	1			T796	1		T798	18		T499	9
values[77]	91	1			T796	1		T798	16		T499	5
values[78]	82	1			T796	1		T798	19		T499	5
values[79]	67	1			T796	1		T798	11		T499	7
values[80]	81	1			T796	1		T798	19		T499	12
values[81]	78	1			T796	1		T798	18		T499	7
values[82]	81	1			T796	1		T798	7		T499	13
values[83]	75	1			T796	1		T798	6		T499	7
values[84]	70	1			T796	1		T798	7		T499	4
values[85]	58	1			T796	1		T798	7		T499	10
values[86]	57	1			T796	1		T798	11		T499	5
values[87]	82	1			T796	1		T798	9		T499	6
values[88]	72	1			T796	1		T798	10		T499	2
values[89]	105	1			T796	1		T798	10		T499	1
values[90]	59	1			T796	1		T798	8		T499	2
values[91]	74	1			T796	1		T798	3		T499	3
values[92]	62	1			T796	1		T798	1		T499	3
values[93]	103	1			T796	1		T798	9		T499	5
values[94]	106	1			T796	1		T798	17		T499	1
values[95]	70	1			T796	1		T798	5		T499	1
values[96]	47	1			T796	1		T798	2		T499	2
values[97]	74	1			T796	1		T798	2		T499	5
values[98]	81	1			T796	1		T798	2		T499	10
values[99]	84	1			T796	1		T798	5		T499	14
values[100]	79	1			T796	1		T798	2		T499	6
values[101]	56	1			T796	1		T798	4		T499	4
values[102]	52	1			T796	1		T798	13		T499	3
values[103]	51	1			T796	1		T798	5		T499	3
values[104]	50	1			T796	1		T798	3		T499	2
values[105]	47	1			T796	1		T798	2		T499	2
values[106]	49	1			T796	1		T798	2		T499	2
values[107]	73	1			T796	1		T798	7		T499	11
values[108]	74	1			T796	1		T798	4		T499	11
values[109]	52	1			T796	1		T798	3		T499	4
values[110]	49	1			T796	1		T798	4		T499	3
values[111]	50	1			T796	3		T798	2		T499	5
values[112]	77	1			T796	2		T798	5		T499	3
values[113]	70	1			T796	1		T798	6		T499	8
values[114]	52	1			T796	1		T798	2		T499	6
values[115]	44	1			T796	2		T798	1		T499	2
values[116]	58	1			T796	4		T798	13		T499	4
values[117]	60	1			T796	1		T798	10		T499	9
values[118]	73	1			T796	2		T798	5		T499	10
values[119]	59	1			T796	1		T798	2		T499	15
values[120]	52	1			T796	1		T798	2		T499	8
values[121]	59	1			T796	2		T798	2		T499	7
values[122]	53	1			T796	1		T798	4		T499	6
values[123]	61	1			T796	3		T798	4		T499	6
values[124]	47	1			T796	1		T798	3		T499	2
values[125]	54	1			T796	2		T798	6		T499	5
values[126]	89	1			T796	2		T798	1		T499	1
values[127]	613	1			T796	33		T798	3		T799	37
values[128]	5119	1			T796	396		T799	241		T800	363