Total Coverage Summary 

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.28	95.50	94.47	95.47		95.36	97.35	99.52

Total tests in report: 2940

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Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
38.92	38.92	45.69	45.69	44.87	44.87	25.13	25.13			58.75	58.75	58.92	58.92	0.19	0.19	/workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.2361046186
48.05	9.13	53.67	7.99	54.13	9.26	27.80	2.67			67.03	8.28	85.14	26.22	0.53	0.34	/workspace/coverage/default/2.chip_jtag_csr_rw.2444428481
54.54	6.49	53.67	0.00	59.43	5.30	27.81	0.01			67.71	0.68	85.14	0.00	33.50	32.97	/workspace/coverage/cover_reg_top/89.xbar_stress_all_with_rand_reset.1934357731
60.11	5.57	65.71	12.04	67.44	8.01	30.42	2.62			78.47	10.76	85.14	0.00	33.50	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_0.2769122595
64.28	4.17	74.35	8.63	68.13	0.69	37.07	6.65			78.64	0.17	85.14	0.00	42.38	8.88	/workspace/coverage/cover_reg_top/9.xbar_stress_all_with_reset_error.2701780174
67.47	3.19	79.56	5.21	72.10	3.97	40.68	3.61			80.42	1.78	89.69	4.55	42.38	0.00	/workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.3231691112
70.56	3.09	79.56	0.00	72.10	0.00	40.68	0.00			80.42	0.00	89.69	0.00	60.92	18.54	/workspace/coverage/cover_reg_top/95.xbar_access_same_device_slow_rsp.792403767
73.39	2.83	79.56	0.00	72.10	0.00	57.60	16.92			80.42	0.00	89.69	0.00	60.97	0.05	/workspace/coverage/default/2.chip_sw_keymgr_sideload_otbn.2701610941
75.69	2.31	81.09	1.54	73.04	0.95	66.98	9.37			81.58	1.16	90.21	0.52	61.26	0.29	/workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.2730338489
77.96	2.26	83.48	2.39	79.17	6.13	67.28	0.30			85.53	3.95	90.21	0.00	62.06	0.80	/workspace/coverage/cover_reg_top/12.chip_csr_rw.2243926434
79.49	1.53	84.61	1.12	80.22	1.05	72.82	5.54			86.48	0.95	90.73	0.52	62.06	0.00	/workspace/coverage/default/1.rom_e2e_self_hash.4042426587
80.98	1.50	84.61	0.00	80.22	0.00	72.82	0.00			86.48	0.00	90.73	0.00	71.04	8.98	/workspace/coverage/cover_reg_top/55.xbar_access_same_device_slow_rsp.3837260629
82.41	1.43	87.02	2.42	81.45	1.23	75.95	3.13			87.24	0.75	91.78	1.05	71.04	0.00	/workspace/coverage/default/2.chip_sw_power_virus.838887118
83.55	1.14	87.02	0.00	81.45	0.00	75.95	0.00			87.24	0.00	91.78	0.00	77.85	6.81	/workspace/coverage/cover_reg_top/63.xbar_access_same_device_slow_rsp.2065002332
84.61	1.06	87.11	0.08	81.45	0.01	82.05	6.10			87.24	0.00	91.96	0.17	77.85	0.00	/workspace/coverage/default/2.chip_sw_lc_walkthrough_prodend.1692735963
85.49	0.88	87.11	0.00	81.45	0.00	82.05	0.00			87.24	0.00	91.96	0.00	83.12	5.26	/workspace/coverage/cover_reg_top/71.xbar_access_same_device_slow_rsp.662662876
86.32	0.83	88.08	0.98	83.21	1.76	82.09	0.04			89.45	2.22	91.96	0.00	83.12	0.00	/workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.2396898157
87.07	0.76	89.35	1.27	84.29	1.08	83.04	0.95			90.69	1.24	91.96	0.00	83.12	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_20.2375453425
87.81	0.73	89.65	0.30	84.41	0.12	83.05	0.01			90.81	0.11	95.80	3.85	83.12	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.391955705
88.51	0.70	91.36	1.71	85.33	0.92	83.98	0.93			91.46	0.65	95.80	0.00	83.12	0.00	/workspace/coverage/default/1.chip_sw_gpio_smoketest.4238044080
89.08	0.57	91.36	0.00	85.33	0.01	86.00	2.02			91.46	0.00	95.80	0.00	84.54	1.42	/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.1075799536
89.59	0.51	91.93	0.57	85.75	0.41	87.41	1.41			92.12	0.67	95.80	0.00	84.54	0.00	/workspace/coverage/default/1.chip_sw_entropy_src_csrng.728837433
90.10	0.51	91.93	0.00	85.75	0.00	87.41	0.00			92.12	0.00	95.80	0.00	87.59	3.05	/workspace/coverage/cover_reg_top/53.xbar_access_same_device_slow_rsp.3037514802
90.60	0.50	91.94	0.01	88.30	2.56	87.41	0.00			92.12	0.00	95.80	0.00	88.00	0.41	/workspace/coverage/cover_reg_top/16.chip_tl_errors.1985919039
91.08	0.48	92.56	0.62	88.82	0.52	88.02	0.61			92.71	0.59	96.33	0.52	88.03	0.02	/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.4006644140
91.54	0.46	92.56	0.00	88.83	0.01	88.02	0.00			92.71	0.00	96.33	0.00	90.78	2.75	/workspace/coverage/cover_reg_top/91.xbar_stress_all_with_error.2421845039
91.98	0.44	92.56	0.00	88.83	0.00	88.02	0.00			92.71	0.00	96.33	0.00	93.44	2.67	/workspace/coverage/cover_reg_top/64.xbar_access_same_device_slow_rsp.2927749514
92.34	0.36	93.07	0.51	89.31	0.48	88.72	0.71			93.18	0.46	96.33	0.00	93.44	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_10.2627638614
92.66	0.32	93.07	0.00	89.31	0.01	88.72	0.00			93.18	0.00	96.33	0.00	95.37	1.93	/workspace/coverage/cover_reg_top/30.xbar_stress_all_with_reset_error.2853371362
92.91	0.25	93.30	0.23	89.97	0.66	88.74	0.01			93.75	0.58	96.33	0.00	95.37	0.00	/workspace/coverage/default/1.chip_jtag_csr_rw.675442415
93.15	0.24	93.42	0.12	90.07	0.10	89.78	1.04			93.93	0.18	96.33	0.00	95.38	0.01	/workspace/coverage/default/2.chip_sw_exit_test_unlocked_bootstrap.2501372158
93.35	0.20	93.42	0.00	90.07	0.00	89.78	0.00			93.93	0.00	96.33	0.00	96.60	1.22	/workspace/coverage/cover_reg_top/22.xbar_access_same_device_slow_rsp.717860688
93.53	0.18	93.42	0.00	90.07	0.00	90.84	1.06			93.93	0.00	96.33	0.00	96.60	0.00	/workspace/coverage/default/0.chip_sw_flash_rma_unlocked.3261497798
93.70	0.17	93.42	0.00	90.07	0.00	91.87	1.03			93.93	0.00	96.33	0.00	96.60	0.00	/workspace/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.3332540522
93.85	0.15	93.62	0.21	90.39	0.32	92.22	0.35			93.93	0.00	96.33	0.00	96.60	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3684335951
93.99	0.14	93.75	0.12	90.39	0.00	92.31	0.09			93.93	0.00	96.33	0.00	97.23	0.62	/workspace/coverage/cover_reg_top/99.xbar_smoke_large_delays.858962037
94.13	0.14	93.90	0.15	90.88	0.49	92.34	0.03			93.95	0.02	96.33	0.00	97.37	0.14	/workspace/coverage/cover_reg_top/0.chip_same_csr_outstanding.765807935
94.25	0.13	94.04	0.14	91.01	0.13	92.66	0.33			94.08	0.13	96.33	0.00	97.40	0.04	/workspace/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.2727219461
94.38	0.12	94.08	0.04	91.14	0.13	92.95	0.29			94.17	0.10	96.50	0.17	97.40	0.00	/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.125627846
94.47	0.10	94.09	0.01	91.41	0.27	92.96	0.01			94.48	0.31	96.50	0.00	97.40	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.1643285832
94.56	0.09	94.09	0.00	91.41	0.00	93.48	0.52			94.48	0.00	96.50	0.00	97.40	0.00	/workspace/coverage/default/0.chip_sw_edn_sw_mode.1900447056
94.64	0.08	94.30	0.21	91.51	0.10	93.57	0.09			94.58	0.10	96.50	0.00	97.40	0.00	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_reset.1486336612
94.72	0.08	94.30	0.00	91.63	0.12	93.57	0.00			94.58	0.00	96.50	0.00	97.74	0.34	/workspace/coverage/cover_reg_top/73.xbar_stress_all_with_rand_reset.3880719684
94.80	0.08	94.45	0.15	91.81	0.17	93.57	0.00			94.72	0.14	96.50	0.00	97.74	0.00	/workspace/coverage/default/2.chip_sw_sleep_pin_retention.2237220488
94.87	0.07	94.45	0.00	92.23	0.43	93.57	0.00			94.72	0.00	96.50	0.00	97.74	0.00	/workspace/coverage/cover_reg_top/11.chip_tl_errors.3771310722
94.94	0.07	94.47	0.02	92.27	0.03	93.58	0.01			94.72	0.00	96.50	0.00	98.10	0.35	/workspace/coverage/default/1.chip_sw_alert_test.297417954
95.00	0.06	94.49	0.03	92.29	0.02	93.70	0.11			94.74	0.02	96.68	0.17	98.11	0.01	/workspace/coverage/default/94.chip_sw_all_escalation_resets.2394419906
95.06	0.06	94.49	0.00	92.29	0.00	94.06	0.36			94.74	0.00	96.68	0.00	98.11	0.00	/workspace/coverage/default/2.chip_sw_lc_ctrl_rand_to_scrap.3490167778
95.12	0.06	94.54	0.04	92.33	0.04	94.11	0.05			94.77	0.02	96.85	0.17	98.12	0.01	/workspace/coverage/default/11.chip_sw_all_escalation_resets.283026728
95.17	0.05	94.54	0.00	92.49	0.16	94.11	0.00			94.94	0.17	96.85	0.00	98.12	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.1841509729
95.22	0.05	94.54	0.00	92.56	0.07	94.11	0.00			94.97	0.03	96.85	0.00	98.28	0.16	/workspace/coverage/cover_reg_top/25.xbar_stress_all_with_rand_reset.1973861746
95.26	0.04	94.58	0.04	92.65	0.09	94.21	0.10			95.00	0.03	96.85	0.00	98.28	0.00	/workspace/coverage/cover_reg_top/0.chip_csr_hw_reset.4175788335
95.30	0.04	94.59	0.01	92.66	0.01	94.21	0.00			95.03	0.02	97.03	0.17	98.30	0.01	/workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.2639497085
95.34	0.04	94.59	0.01	92.68	0.01	94.22	0.01			95.03	0.01	97.20	0.17	98.31	0.01	/workspace/coverage/default/91.chip_sw_all_escalation_resets.2247204723
95.37	0.04	94.60	0.01	92.69	0.01	94.22	0.00			95.04	0.01	97.38	0.17	98.32	0.01	/workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.3218692770
95.41	0.03	94.60	0.00	92.89	0.20	94.22	0.00			95.04	0.00	97.38	0.00	98.32	0.00	/workspace/coverage/cover_reg_top/10.chip_tl_errors.1105631450
95.44	0.03	94.60	0.00	92.89	0.00	94.22	0.00			95.04	0.00	97.38	0.00	98.52	0.20	/workspace/coverage/cover_reg_top/38.xbar_stress_all_with_reset_error.3067422817
95.47	0.03	94.60	0.00	92.89	0.00	94.42	0.19			95.04	0.00	97.38	0.00	98.52	0.00	/workspace/coverage/default/1.chip_sw_flash_rma_unlocked.586418617
95.51	0.03	94.67	0.07	92.89	0.00	94.52	0.11			95.05	0.01	97.38	0.00	98.52	0.00	/workspace/coverage/default/2.chip_tap_straps_testunlock0.2181184673
95.54	0.03	94.69	0.02	92.94	0.05	94.62	0.09			95.08	0.02	97.38	0.00	98.52	0.00	/workspace/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.124465532
95.57	0.03	94.69	0.00	93.11	0.18	94.62	0.00			95.08	0.00	97.38	0.00	98.52	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_0.3734467542
95.60	0.03	94.72	0.02	93.27	0.15	94.62	0.00			95.08	0.00	97.38	0.00	98.52	0.00	/workspace/coverage/cover_reg_top/17.chip_same_csr_outstanding.1728033384
95.62	0.03	94.79	0.07	93.29	0.03	94.63	0.01			95.12	0.05	97.38	0.00	98.52	0.00	/workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.1524897739
95.64	0.02	94.80	0.01	93.36	0.07	94.63	0.00			95.19	0.06	97.38	0.00	98.52	0.00	/workspace/coverage/default/0.chip_sw_spi_device_pinmux_sleep_retention.4106325604
95.67	0.02	94.82	0.02	93.42	0.06	94.64	0.02			95.23	0.04	97.38	0.00	98.52	0.00	/workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.3846637876
95.69	0.02	94.82	0.00	93.50	0.08	94.64	0.00			95.26	0.03	97.38	0.00	98.52	0.00	/workspace/coverage/cover_reg_top/23.xbar_stress_all.1474459095
95.70	0.02	94.82	0.00	93.61	0.11	94.64	0.00			95.26	0.00	97.38	0.00	98.52	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_20.1990341563
95.72	0.02	94.82	0.00	93.61	0.00	94.75	0.11			95.26	0.00	97.38	0.00	98.52	0.00	/workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.2885605817
95.74	0.02	94.82	0.00	93.68	0.07	94.75	0.00			95.29	0.03	97.38	0.00	98.52	0.00	/workspace/coverage/cover_reg_top/38.xbar_stress_all_with_rand_reset.1079581041
95.75	0.02	94.82	0.00	93.71	0.04	94.75	0.00			95.29	0.00	97.38	0.00	98.58	0.06	/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_rand_reset.841273415
95.77	0.02	94.82	0.00	93.73	0.02	94.82	0.07			95.29	0.00	97.38	0.00	98.58	0.00	/workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.4213941918
95.78	0.01	94.82	0.00	93.82	0.09	94.82	0.00			95.29	0.00	97.38	0.00	98.58	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_0.3882387008
95.80	0.01	94.83	0.01	93.83	0.01	94.88	0.07			95.29	0.00	97.38	0.00	98.58	0.00	/workspace/coverage/default/1.chip_sw_ast_clk_rst_inputs.1990231455
95.81	0.01	94.83	0.00	93.83	0.00	94.95	0.07			95.29	0.00	97.38	0.00	98.58	0.00	/workspace/coverage/default/2.chip_sw_lc_walkthrough_dev.2313981578
95.82	0.01	94.83	0.00	93.89	0.06	94.95	0.00			95.29	0.00	97.38	0.00	98.59	0.01	/workspace/coverage/cover_reg_top/27.chip_tl_errors.1574504337
95.83	0.01	94.83	0.00	93.94	0.05	94.95	0.00			95.31	0.02	97.38	0.00	98.59	0.00	/workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.107155044
95.84	0.01	94.86	0.03	93.96	0.02	94.95	0.00			95.32	0.01	97.38	0.00	98.59	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_wake.3994584329
95.85	0.01	94.86	0.00	93.97	0.01	95.01	0.05			95.32	0.00	97.38	0.00	98.59	0.00	/workspace/coverage/default/0.rom_e2e_shutdown_output.2067233350
95.86	0.01	94.89	0.02	93.98	0.01	95.02	0.01			95.33	0.02	97.38	0.00	98.59	0.00	/workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.4026260134
95.87	0.01	94.89	0.01	93.99	0.01	95.03	0.02			95.34	0.01	97.38	0.00	98.60	0.01	/workspace/coverage/default/55.chip_sw_all_escalation_resets.3714730173
95.88	0.01	94.89	0.00	94.00	0.01	95.03	0.00			95.34	0.00	97.38	0.00	98.64	0.04	/workspace/coverage/cover_reg_top/57.xbar_stress_all_with_rand_reset.2960128078
95.89	0.01	94.89	0.00	94.05	0.05	95.03	0.00			95.34	0.00	97.38	0.00	98.64	0.00	/workspace/coverage/cover_reg_top/17.chip_tl_errors.674826544
95.89	0.01	94.89	0.01	94.06	0.02	95.05	0.02			95.34	0.00	97.38	0.00	98.64	0.00	/workspace/coverage/default/1.chip_sw_spi_host_tx_rx.2843908593
95.90	0.01	94.89	0.00	94.06	0.00	95.09	0.04			95.34	0.00	97.38	0.00	98.64	0.00	/workspace/coverage/cover_reg_top/2.chip_csr_hw_reset.64683994
95.91	0.01	94.89	0.00	94.08	0.02	95.09	0.00			95.34	0.00	97.38	0.00	98.66	0.02	/workspace/coverage/cover_reg_top/45.xbar_stress_all_with_rand_reset.3404668780
95.91	0.01	94.89	0.00	94.12	0.04	95.09	0.00			95.34	0.00	97.38	0.00	98.66	0.00	/workspace/coverage/default/2.chip_sw_gpio.3529016954
95.92	0.01	94.89	0.00	94.12	0.00	95.13	0.04			95.34	0.00	97.38	0.00	98.66	0.00	/workspace/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.1713631348
95.93	0.01	94.89	0.00	94.12	0.00	95.17	0.04			95.34	0.00	97.38	0.00	98.66	0.00	/workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.854907359
95.93	0.01	94.89	0.00	94.12	0.00	95.21	0.04			95.34	0.00	97.38	0.00	98.66	0.00	/workspace/coverage/default/2.chip_sw_flash_rma_unlocked.1403616122
95.94	0.01	94.89	0.00	94.16	0.04	95.21	0.00			95.34	0.00	97.38	0.00	98.66	0.00	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.2423519048
95.95	0.01	94.89	0.00	94.16	0.00	95.21	0.00			95.34	0.00	97.38	0.00	98.70	0.04	/workspace/coverage/cover_reg_top/37.xbar_stress_all_with_rand_reset.3573649214
95.95	0.01	94.89	0.00	94.16	0.00	95.24	0.03			95.34	0.00	97.38	0.00	98.70	0.00	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.2073379865
95.96	0.01	94.89	0.00	94.16	0.01	95.24	0.00			95.34	0.00	97.38	0.00	98.72	0.02	/workspace/coverage/cover_reg_top/34.xbar_stress_all_with_rand_reset.3724244124
95.96	0.01	94.90	0.01	94.19	0.02	95.24	0.00			95.34	0.00	97.38	0.00	98.72	0.00	/workspace/coverage/cover_reg_top/14.chip_csr_rw.3352172323
95.96	0.01	94.90	0.00	94.21	0.02	95.24	0.00			95.34	0.00	97.38	0.00	98.72	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_10.2818478712
95.97	0.01	94.90	0.00	94.21	0.00	95.24	0.00			95.34	0.00	97.38	0.00	98.74	0.02	/workspace/coverage/cover_reg_top/21.xbar_stress_all_with_reset_error.993092495
95.97	0.01	94.90	0.00	94.21	0.00	95.24	0.00			95.34	0.00	97.38	0.00	98.77	0.02	/workspace/coverage/cover_reg_top/56.xbar_stress_all_with_rand_reset.3299058829
95.98	0.01	94.90	0.01	94.22	0.01	95.25	0.01			95.34	0.00	97.38	0.00	98.77	0.00	/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx3.11695907
95.98	0.01	94.90	0.00	94.22	0.00	95.27	0.02			95.34	0.00	97.38	0.00	98.77	0.00	/workspace/coverage/default/3.chip_sw_csrng_edn_concurrency.1839162155
95.98	0.01	94.90	0.00	94.24	0.02	95.27	0.00			95.34	0.00	97.38	0.00	98.77	0.00	/workspace/coverage/cover_reg_top/61.xbar_stress_all_with_rand_reset.3652227793
95.99	0.01	94.90	0.00	94.24	0.00	95.30	0.02			95.34	0.00	97.38	0.00	98.77	0.00	/workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.1898942944
95.99	0.01	94.90	0.01	94.25	0.01	95.30	0.01			95.34	0.00	97.38	0.00	98.77	0.00	/workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.1873391562
95.99	0.01	94.90	0.00	94.25	0.00	95.32	0.02			95.34	0.00	97.38	0.00	98.77	0.00	/workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.3391467284
96.00	0.01	94.90	0.00	94.25	0.00	95.34	0.02			95.34	0.00	97.38	0.00	98.77	0.00	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_lc.3175182171
96.00	0.01	94.90	0.00	94.27	0.02	95.34	0.00			95.34	0.00	97.38	0.00	98.77	0.00	/workspace/coverage/cover_reg_top/23.chip_tl_errors.1011049449
96.00	0.01	94.90	0.00	94.29	0.02	95.34	0.00			95.34	0.00	97.38	0.00	98.77	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_20.3255584729
96.01	0.01	94.90	0.00	94.29	0.00	95.35	0.01			95.35	0.01	97.38	0.00	98.77	0.00	/workspace/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.1164275858
96.01	0.01	94.92	0.01	94.29	0.00	95.35	0.01			95.35	0.00	97.38	0.00	98.77	0.00	/workspace/coverage/default/0.chip_sw_plic_sw_irq.99558954
96.01	0.01	94.92	0.00	94.29	0.01	95.35	0.00			95.35	0.00	97.38	0.00	98.78	0.01	/workspace/coverage/cover_reg_top/47.xbar_stress_all_with_error.3384984084
96.01	0.01	94.92	0.00	94.30	0.01	95.35	0.01			95.35	0.00	97.38	0.00	98.78	0.00	/workspace/coverage/default/1.chip_sw_rstmgr_alert_info.2148883535
96.02	0.01	94.92	0.00	94.32	0.01	95.35	0.00			95.35	0.00	97.38	0.00	98.78	0.00	/workspace/coverage/cover_reg_top/1.chip_same_csr_outstanding.3704307746
96.02	0.01	94.92	0.00	94.33	0.01	95.35	0.00			95.35	0.00	97.38	0.00	98.78	0.00	/workspace/coverage/cover_reg_top/28.xbar_stress_all_with_rand_reset.319428852
96.02	0.01	94.92	0.00	94.35	0.01	95.35	0.00			95.35	0.00	97.38	0.00	98.78	0.00	/workspace/coverage/cover_reg_top/40.xbar_stress_all.1956764944
96.02	0.01	94.92	0.00	94.36	0.01	95.35	0.00			95.35	0.00	97.38	0.00	98.78	0.00	/workspace/coverage/default/1.chip_sw_gpio.659413969
96.03	0.01	94.92	0.00	94.36	0.00	95.37	0.01			95.35	0.00	97.38	0.00	98.78	0.00	/workspace/coverage/default/0.chip_sw_usbdev_config_host.1652235100
96.03	0.01	94.92	0.00	94.36	0.00	95.37	0.00			95.35	0.00	97.38	0.00	98.79	0.01	/workspace/coverage/cover_reg_top/13.chip_tl_errors.4130440526
96.03	0.01	94.92	0.00	94.36	0.00	95.37	0.00			95.35	0.00	97.38	0.00	98.80	0.01	/workspace/coverage/cover_reg_top/24.xbar_stress_all_with_rand_reset.1901086816
96.03	0.01	94.92	0.00	94.36	0.00	95.37	0.00			95.35	0.00	97.38	0.00	98.81	0.01	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.2180228308
96.03	0.01	94.92	0.00	94.36	0.00	95.37	0.00			95.35	0.00	97.38	0.00	98.83	0.01	/workspace/coverage/default/0.chip_sw_all_escalation_resets.2347994624
96.04	0.01	94.92	0.00	94.36	0.00	95.37	0.00			95.35	0.00	97.38	0.00	98.84	0.01	/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.4244073263
96.04	0.01	94.92	0.00	94.36	0.00	95.37	0.00			95.35	0.00	97.38	0.00	98.85	0.01	/workspace/coverage/default/1.chip_sw_all_escalation_resets.77782391
96.04	0.01	94.92	0.00	94.36	0.00	95.37	0.00			95.35	0.00	97.38	0.00	98.86	0.01	/workspace/coverage/default/12.chip_sw_all_escalation_resets.3387062799
96.04	0.01	94.92	0.00	94.36	0.00	95.37	0.00			95.35	0.00	97.38	0.00	98.87	0.01	/workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.2890275474
96.04	0.01	94.92	0.00	94.36	0.00	95.37	0.00			95.35	0.00	97.38	0.00	98.88	0.01	/workspace/coverage/default/14.chip_sw_all_escalation_resets.3371762600
96.04	0.01	94.92	0.00	94.36	0.00	95.37	0.00			95.35	0.00	97.38	0.00	98.90	0.01	/workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.3046929779
96.05	0.01	94.92	0.00	94.36	0.00	95.37	0.00			95.35	0.00	97.38	0.00	98.91	0.01	/workspace/coverage/default/15.chip_sw_all_escalation_resets.3403912712
96.05	0.01	94.92	0.00	94.36	0.00	95.37	0.00			95.35	0.00	97.38	0.00	98.92	0.01	/workspace/coverage/default/16.chip_sw_all_escalation_resets.2639683062
96.05	0.01	94.92	0.00	94.36	0.00	95.37	0.00			95.35	0.00	97.38	0.00	98.93	0.01	/workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.1238861730
96.05	0.01	94.92	0.00	94.36	0.00	95.37	0.00			95.35	0.00	97.38	0.00	98.94	0.01	/workspace/coverage/default/17.chip_sw_all_escalation_resets.729021213
96.05	0.01	94.92	0.00	94.36	0.00	95.37	0.00			95.35	0.00	97.38	0.00	98.95	0.01	/workspace/coverage/default/18.chip_sw_all_escalation_resets.2209776191
96.06	0.01	94.92	0.00	94.36	0.00	95.37	0.00			95.35	0.00	97.38	0.00	98.97	0.01	/workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.3176692430
96.06	0.01	94.92	0.00	94.36	0.00	95.37	0.00			95.35	0.00	97.38	0.00	98.98	0.01	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.3072350562
96.06	0.01	94.92	0.00	94.36	0.00	95.37	0.00			95.35	0.00	97.38	0.00	98.99	0.01	/workspace/coverage/default/2.chip_sw_all_escalation_resets.1525812603
96.06	0.01	94.92	0.00	94.36	0.00	95.37	0.00			95.35	0.00	97.38	0.00	99.00	0.01	/workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.1875320140
96.06	0.01	94.92	0.00	94.36	0.00	95.37	0.00			95.35	0.00	97.38	0.00	99.01	0.01	/workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.2939721404
96.07	0.01	94.92	0.00	94.36	0.00	95.37	0.00			95.35	0.00	97.38	0.00	99.02	0.01	/workspace/coverage/default/21.chip_sw_all_escalation_resets.3810526059
96.07	0.01	94.92	0.00	94.36	0.00	95.37	0.00			95.35	0.00	97.38	0.00	99.04	0.01	/workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.2465992001
96.07	0.01	94.92	0.00	94.36	0.00	95.37	0.00			95.35	0.00	97.38	0.00	99.05	0.01	/workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.2735254973
96.07	0.01	94.92	0.00	94.36	0.00	95.37	0.00			95.35	0.00	97.38	0.00	99.06	0.01	/workspace/coverage/default/23.chip_sw_all_escalation_resets.3468758954
96.07	0.01	94.92	0.00	94.36	0.00	95.37	0.00			95.35	0.00	97.38	0.00	99.07	0.01	/workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.642326803
96.08	0.01	94.92	0.00	94.36	0.00	95.37	0.00			95.35	0.00	97.38	0.00	99.08	0.01	/workspace/coverage/default/24.chip_sw_all_escalation_resets.3297700111
96.08	0.01	94.92	0.00	94.36	0.00	95.37	0.00			95.35	0.00	97.38	0.00	99.10	0.01	/workspace/coverage/default/25.chip_sw_all_escalation_resets.1689415394
96.08	0.01	94.92	0.00	94.36	0.00	95.37	0.00			95.35	0.00	97.38	0.00	99.11	0.01	/workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.206198315
96.08	0.01	94.92	0.00	94.36	0.00	95.37	0.00			95.35	0.00	97.38	0.00	99.12	0.01	/workspace/coverage/default/27.chip_sw_all_escalation_resets.2973525898
96.08	0.01	94.92	0.00	94.36	0.00	95.37	0.00			95.35	0.00	97.38	0.00	99.13	0.01	/workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.1623203386
96.09	0.01	94.92	0.00	94.36	0.00	95.37	0.00			95.35	0.00	97.38	0.00	99.14	0.01	/workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.4081332063
96.09	0.01	94.92	0.00	94.36	0.00	95.37	0.00			95.35	0.00	97.38	0.00	99.15	0.01	/workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.539738980
96.09	0.01	94.92	0.00	94.36	0.00	95.37	0.00			95.35	0.00	97.38	0.00	99.17	0.01	/workspace/coverage/default/34.chip_sw_all_escalation_resets.1448889430
96.09	0.01	94.92	0.00	94.36	0.00	95.37	0.00			95.35	0.00	97.38	0.00	99.18	0.01	/workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.3220451977
96.09	0.01	94.92	0.00	94.36	0.00	95.37	0.00			95.35	0.00	97.38	0.00	99.19	0.01	/workspace/coverage/default/37.chip_sw_all_escalation_resets.1916986600
96.10	0.01	94.92	0.00	94.36	0.00	95.37	0.00			95.35	0.00	97.38	0.00	99.20	0.01	/workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.1360562581
96.10	0.01	94.92	0.00	94.36	0.00	95.37	0.00			95.35	0.00	97.38	0.00	99.21	0.01	/workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.1851259411
96.10	0.01	94.92	0.00	94.36	0.00	95.37	0.00			95.35	0.00	97.38	0.00	99.22	0.01	/workspace/coverage/default/41.chip_sw_all_escalation_resets.2093178912
96.10	0.01	94.92	0.00	94.36	0.00	95.37	0.00			95.35	0.00	97.38	0.00	99.24	0.01	/workspace/coverage/default/42.chip_sw_all_escalation_resets.1219250571
96.10	0.01	94.92	0.00	94.36	0.00	95.37	0.00			95.35	0.00	97.38	0.00	99.25	0.01	/workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.1841332110
96.11	0.01	94.92	0.00	94.36	0.00	95.37	0.00			95.35	0.00	97.38	0.00	99.26	0.01	/workspace/coverage/default/47.chip_sw_all_escalation_resets.465482917
96.11	0.01	94.92	0.00	94.36	0.00	95.37	0.00			95.35	0.00	97.38	0.00	99.27	0.01	/workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.3721582106
96.11	0.01	94.92	0.00	94.36	0.00	95.37	0.00			95.35	0.00	97.38	0.00	99.28	0.01	/workspace/coverage/default/52.chip_sw_all_escalation_resets.3234162102
96.11	0.01	94.92	0.00	94.36	0.00	95.37	0.00			95.35	0.00	97.38	0.00	99.30	0.01	/workspace/coverage/default/53.chip_sw_all_escalation_resets.1160060458
96.11	0.01	94.92	0.00	94.36	0.00	95.37	0.00			95.35	0.00	97.38	0.00	99.31	0.01	/workspace/coverage/default/54.chip_sw_all_escalation_resets.3058847008
96.12	0.01	94.92	0.00	94.36	0.00	95.37	0.00			95.35	0.00	97.38	0.00	99.32	0.01	/workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.951733122
96.12	0.01	94.92	0.00	94.36	0.00	95.37	0.00			95.35	0.00	97.38	0.00	99.33	0.01	/workspace/coverage/default/56.chip_sw_all_escalation_resets.4176007080
96.12	0.01	94.92	0.00	94.36	0.00	95.37	0.00			95.35	0.00	97.38	0.00	99.34	0.01	/workspace/coverage/default/57.chip_sw_all_escalation_resets.1905739837
96.12	0.01	94.92	0.00	94.36	0.00	95.37	0.00			95.35	0.00	97.38	0.00	99.35	0.01	/workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.441654620
96.12	0.01	94.92	0.00	94.36	0.00	95.37	0.00			95.35	0.00	97.38	0.00	99.37	0.01	/workspace/coverage/default/60.chip_sw_all_escalation_resets.4174556798
96.13	0.01	94.92	0.00	94.36	0.00	95.37	0.00			95.35	0.00	97.38	0.00	99.38	0.01	/workspace/coverage/default/61.chip_sw_all_escalation_resets.743528815
96.13	0.01	94.92	0.00	94.36	0.00	95.37	0.00			95.35	0.00	97.38	0.00	99.39	0.01	/workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.300229453
96.13	0.01	94.92	0.00	94.36	0.00	95.37	0.00			95.35	0.00	97.38	0.00	99.40	0.01	/workspace/coverage/default/63.chip_sw_all_escalation_resets.2896354565
96.13	0.01	94.92	0.00	94.36	0.00	95.37	0.00			95.35	0.00	97.38	0.00	99.41	0.01	/workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.4182198815
96.13	0.01	94.92	0.00	94.36	0.00	95.37	0.00			95.35	0.00	97.38	0.00	99.42	0.01	/workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.3853068633
96.13	0.01	94.92	0.00	94.36	0.00	95.37	0.00			95.35	0.00	97.38	0.00	99.44	0.01	/workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.833951807
96.14	0.01	94.92	0.00	94.36	0.00	95.37	0.00			95.35	0.00	97.38	0.00	99.45	0.01	/workspace/coverage/default/73.chip_sw_all_escalation_resets.2869063144
96.14	0.01	94.92	0.00	94.36	0.00	95.37	0.00			95.35	0.00	97.38	0.00	99.46	0.01	/workspace/coverage/default/79.chip_sw_all_escalation_resets.1191403146
96.14	0.01	94.92	0.00	94.36	0.00	95.37	0.00			95.35	0.00	97.38	0.00	99.47	0.01	/workspace/coverage/default/8.chip_sw_all_escalation_resets.3895647680
96.14	0.01	94.92	0.00	94.36	0.00	95.37	0.00			95.35	0.00	97.38	0.00	99.48	0.01	/workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.1736982302
96.14	0.01	94.92	0.00	94.36	0.00	95.37	0.00			95.35	0.00	97.38	0.00	99.49	0.01	/workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.3686411964
96.15	0.01	94.92	0.00	94.36	0.00	95.37	0.00			95.35	0.00	97.38	0.00	99.51	0.01	/workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.2621034512
96.15	0.01	94.92	0.00	94.36	0.00	95.37	0.00			95.35	0.00	97.38	0.00	99.52	0.01	/workspace/coverage/default/98.chip_sw_all_escalation_resets.3115916619
96.15	0.01	94.92	0.00	94.37	0.01	95.37	0.00			95.35	0.00	97.38	0.00	99.52	0.00	/workspace/coverage/cover_reg_top/30.xbar_stress_all.2749501017
96.15	0.01	94.92	0.00	94.38	0.01	95.37	0.00			95.35	0.00	97.38	0.00	99.52	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.1368005249
96.15	0.01	94.92	0.00	94.39	0.01	95.37	0.00			95.35	0.00	97.38	0.00	99.52	0.00	/workspace/coverage/default/0.chip_sw_uart_tx_rx.2953794827
96.16	0.01	94.92	0.01	94.39	0.00	95.38	0.01			95.35	0.00	97.38	0.00	99.52	0.00	/workspace/coverage/default/10.chip_sw_all_escalation_resets.3150299888
96.16	0.01	94.92	0.00	94.40	0.01	95.38	0.01			95.35	0.00	97.38	0.00	99.52	0.00	/workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.1800347619
96.16	0.01	94.92	0.00	94.40	0.00	95.39	0.01			95.35	0.00	97.38	0.00	99.52	0.00	/workspace/coverage/default/0.chip_sw_flash_init.405204683
96.16	0.01	94.92	0.00	94.40	0.00	95.40	0.01			95.35	0.00	97.38	0.00	99.52	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.1987618149
96.16	0.01	94.92	0.00	94.40	0.00	95.41	0.01			95.35	0.00	97.38	0.00	99.52	0.00	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.4164697396
96.16	0.01	94.92	0.00	94.40	0.00	95.42	0.01			95.35	0.00	97.38	0.00	99.52	0.00	/workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.3475576793
96.16	0.01	94.92	0.00	94.40	0.01	95.42	0.01			95.35	0.00	97.38	0.00	99.52	0.00	/workspace/coverage/cover_reg_top/4.chip_csr_hw_reset.3855975859
96.17	0.01	94.92	0.00	94.40	0.00	95.42	0.00			95.36	0.01	97.38	0.00	99.52	0.00	/workspace/coverage/default/1.chip_tap_straps_dev.567001475
96.17	0.01	94.92	0.00	94.41	0.01	95.42	0.00			95.36	0.00	97.38	0.00	99.52	0.00	/workspace/coverage/cover_reg_top/14.xbar_random_large_delays.1560825460
96.17	0.01	94.92	0.00	94.42	0.01	95.42	0.00			95.36	0.00	97.38	0.00	99.52	0.00	/workspace/coverage/cover_reg_top/8.chip_tl_errors.87483581
96.17	0.01	94.92	0.00	94.42	0.01	95.42	0.00			95.36	0.00	97.38	0.00	99.52	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.3086532784
96.17	0.01	94.92	0.00	94.43	0.01	95.42	0.00			95.36	0.00	97.38	0.00	99.52	0.00	/workspace/coverage/default/1.chip_sw_flash_ctrl_ops.1922988858
96.17	0.01	94.92	0.00	94.44	0.01	95.42	0.00			95.36	0.00	97.38	0.00	99.52	0.00	/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx1.3673615190
96.17	0.01	94.92	0.00	94.44	0.00	95.43	0.01			95.36	0.00	97.38	0.00	99.52	0.00	/workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2847851792
96.17	0.01	94.92	0.00	94.44	0.00	95.43	0.01			95.36	0.00	97.38	0.00	99.52	0.00	/workspace/coverage/default/0.chip_sw_kmac_idle.4010307652
96.18	0.01	94.92	0.00	94.44	0.01	95.44	0.01			95.36	0.00	97.38	0.00	99.52	0.00	/workspace/coverage/default/1.chip_sw_aon_timer_irq.4032029703
96.18	0.01	94.92	0.00	94.44	0.00	95.44	0.01			95.36	0.00	97.38	0.00	99.52	0.00	/workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.2829361168
96.18	0.01	94.92	0.00	94.44	0.00	95.45	0.01			95.36	0.00	97.38	0.00	99.52	0.00	/workspace/coverage/default/0.chip_sw_lc_ctrl_program_error.1432894194
96.18	0.01	94.92	0.00	94.44	0.00	95.45	0.01			95.36	0.00	97.38	0.00	99.52	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2579496505
96.18	0.01	94.92	0.00	94.44	0.00	95.45	0.01			95.36	0.00	97.38	0.00	99.52	0.00	/workspace/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.2203572110
96.18	0.01	94.92	0.00	94.44	0.01	95.45	0.00			95.36	0.00	97.38	0.00	99.52	0.00	/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.1318030276
96.18	0.01	94.92	0.00	94.45	0.01	95.45	0.00			95.36	0.00	97.38	0.00	99.52	0.00	/workspace/coverage/cover_reg_top/28.xbar_error_random.1301963669
96.18	0.01	94.92	0.00	94.45	0.01	95.45	0.00			95.36	0.00	97.38	0.00	99.52	0.00	/workspace/coverage/cover_reg_top/44.xbar_stress_all_with_error.4254241195
96.18	0.01	94.92	0.00	94.46	0.01	95.45	0.00			95.36	0.00	97.38	0.00	99.52	0.00	/workspace/coverage/cover_reg_top/58.xbar_stress_all_with_error.1628948119
96.18	0.01	94.92	0.00	94.46	0.01	95.45	0.00			95.36	0.00	97.38	0.00	99.52	0.00	/workspace/coverage/cover_reg_top/8.xbar_stress_all_with_error.3728084734
96.18	0.01	94.92	0.00	94.46	0.01	95.45	0.00			95.36	0.00	97.38	0.00	99.52	0.00	/workspace/coverage/cover_reg_top/92.xbar_stress_all_with_error.4179229383
96.18	0.01	94.92	0.00	94.47	0.01	95.45	0.00			95.36	0.00	97.38	0.00	99.52	0.00	/workspace/coverage/default/0.chip_sw_gpio.2648734561
96.18	0.01	94.92	0.00	94.47	0.01	95.45	0.00			95.36	0.00	97.38	0.00	99.52	0.00	/workspace/coverage/default/0.chip_sw_rstmgr_alert_info.2881154566
96.18	0.01	94.92	0.00	94.47	0.01	95.45	0.00			95.36	0.00	97.38	0.00	99.52	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.843562597
96.18	0.01	94.92	0.00	94.47	0.00	95.46	0.01			95.36	0.00	97.38	0.00	99.52	0.00	/workspace/coverage/cover_reg_top/1.chip_csr_hw_reset.1612096706
96.18	0.01	94.92	0.00	94.47	0.00	95.46	0.01			95.36	0.00	97.38	0.00	99.52	0.00	/workspace/coverage/default/0.chip_sw_edn_boot_mode.707624057
96.18	0.01	94.92	0.00	94.47	0.00	95.46	0.01			95.36	0.00	97.38	0.00	99.52	0.00	/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.1226228276
96.19	0.01	94.92	0.00	94.47	0.00	95.46	0.01			95.36	0.00	97.38	0.00	99.52	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.552805578
96.19	0.01	94.92	0.00	94.47	0.00	95.47	0.01			95.36	0.00	97.38	0.00	99.52	0.00	/workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.637234761
96.19	0.01	94.92	0.00	94.47	0.00	95.47	0.01			95.36	0.00	97.38	0.00	99.52	0.00	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.68868669

---

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.chip_csr_aliasing.775709684
/workspace/coverage/cover_reg_top/0.chip_csr_bit_bash.104227543
/workspace/coverage/cover_reg_top/0.chip_csr_mem_rw_with_rand_reset.1934936964
/workspace/coverage/cover_reg_top/0.chip_csr_rw.2716406623
/workspace/coverage/cover_reg_top/0.chip_prim_tl_access.1185773951
/workspace/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.2508862221
/workspace/coverage/cover_reg_top/0.chip_tl_errors.1424444363
/workspace/coverage/cover_reg_top/0.xbar_access_same_device.2594419316
/workspace/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.2210140771
/workspace/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.1321017730
/workspace/coverage/cover_reg_top/0.xbar_error_random.1619864238
/workspace/coverage/cover_reg_top/0.xbar_random.3124694689
/workspace/coverage/cover_reg_top/0.xbar_random_large_delays.1130924057
/workspace/coverage/cover_reg_top/0.xbar_random_slow_rsp.1443522862
/workspace/coverage/cover_reg_top/0.xbar_random_zero_delays.2138175564
/workspace/coverage/cover_reg_top/0.xbar_same_source.3212125676
/workspace/coverage/cover_reg_top/0.xbar_smoke.224235315
/workspace/coverage/cover_reg_top/0.xbar_smoke_large_delays.2486606998
/workspace/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.669174151
/workspace/coverage/cover_reg_top/0.xbar_smoke_zero_delays.2589645103
/workspace/coverage/cover_reg_top/0.xbar_stress_all.3508419221
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_error.3599855038
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.1092801157
/workspace/coverage/cover_reg_top/0.xbar_unmapped_addr.1483367391
/workspace/coverage/cover_reg_top/1.chip_csr_aliasing.1933397105
/workspace/coverage/cover_reg_top/1.chip_csr_bit_bash.3837127818
/workspace/coverage/cover_reg_top/1.chip_csr_mem_rw_with_rand_reset.669651596
/workspace/coverage/cover_reg_top/1.chip_csr_rw.2792541843
/workspace/coverage/cover_reg_top/1.chip_prim_tl_access.4033940051
/workspace/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.3621506427
/workspace/coverage/cover_reg_top/1.chip_tl_errors.1948886364
/workspace/coverage/cover_reg_top/1.xbar_access_same_device.2697114489
/workspace/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.2489481367
/workspace/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.3773152217
/workspace/coverage/cover_reg_top/1.xbar_error_random.2684314025
/workspace/coverage/cover_reg_top/1.xbar_random.1311940516
/workspace/coverage/cover_reg_top/1.xbar_random_large_delays.3776091400
/workspace/coverage/cover_reg_top/1.xbar_random_slow_rsp.3088701449
/workspace/coverage/cover_reg_top/1.xbar_random_zero_delays.308474446
/workspace/coverage/cover_reg_top/1.xbar_same_source.3592647280
/workspace/coverage/cover_reg_top/1.xbar_smoke.2396360909
/workspace/coverage/cover_reg_top/1.xbar_smoke_large_delays.1166213496
/workspace/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.145300889
/workspace/coverage/cover_reg_top/1.xbar_smoke_zero_delays.3323404671
/workspace/coverage/cover_reg_top/1.xbar_stress_all.2470682058
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_error.521906016
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.3578398402
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.3381967531
/workspace/coverage/cover_reg_top/1.xbar_unmapped_addr.2940888233
/workspace/coverage/cover_reg_top/10.chip_csr_mem_rw_with_rand_reset.3924454151
/workspace/coverage/cover_reg_top/10.chip_csr_rw.2006844293
/workspace/coverage/cover_reg_top/10.chip_same_csr_outstanding.2149852725
/workspace/coverage/cover_reg_top/10.xbar_access_same_device.968865423
/workspace/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.3155449639
/workspace/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.806915738
/workspace/coverage/cover_reg_top/10.xbar_error_random.35154783
/workspace/coverage/cover_reg_top/10.xbar_random.1274560107
/workspace/coverage/cover_reg_top/10.xbar_random_large_delays.2347859995
/workspace/coverage/cover_reg_top/10.xbar_random_slow_rsp.520070977
/workspace/coverage/cover_reg_top/10.xbar_random_zero_delays.777486777
/workspace/coverage/cover_reg_top/10.xbar_same_source.3181631598
/workspace/coverage/cover_reg_top/10.xbar_smoke.3537565918
/workspace/coverage/cover_reg_top/10.xbar_smoke_large_delays.1781812873
/workspace/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.3529736996
/workspace/coverage/cover_reg_top/10.xbar_smoke_zero_delays.1469114940
/workspace/coverage/cover_reg_top/10.xbar_stress_all.299027096
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_error.2875615227
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.1445830487
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.2865487783
/workspace/coverage/cover_reg_top/10.xbar_unmapped_addr.365965659
/workspace/coverage/cover_reg_top/11.chip_csr_mem_rw_with_rand_reset.3715333661
/workspace/coverage/cover_reg_top/11.chip_csr_rw.2547965749
/workspace/coverage/cover_reg_top/11.chip_same_csr_outstanding.4173774889
/workspace/coverage/cover_reg_top/11.xbar_access_same_device.403876346
/workspace/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.3159181666
/workspace/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.1812649131
/workspace/coverage/cover_reg_top/11.xbar_error_random.724197414
/workspace/coverage/cover_reg_top/11.xbar_random.1857323921
/workspace/coverage/cover_reg_top/11.xbar_random_large_delays.1911609939
/workspace/coverage/cover_reg_top/11.xbar_random_slow_rsp.3642801523
/workspace/coverage/cover_reg_top/11.xbar_random_zero_delays.2102237992
/workspace/coverage/cover_reg_top/11.xbar_same_source.2487825860
/workspace/coverage/cover_reg_top/11.xbar_smoke.741470224
/workspace/coverage/cover_reg_top/11.xbar_smoke_large_delays.2347341660
/workspace/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.301913867
/workspace/coverage/cover_reg_top/11.xbar_smoke_zero_delays.320654571
/workspace/coverage/cover_reg_top/11.xbar_stress_all.3956091607
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_error.1164916355
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.4167098282
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.2718553559
/workspace/coverage/cover_reg_top/11.xbar_unmapped_addr.2902716109
/workspace/coverage/cover_reg_top/12.chip_csr_mem_rw_with_rand_reset.1932893102
/workspace/coverage/cover_reg_top/12.chip_same_csr_outstanding.629901167
/workspace/coverage/cover_reg_top/12.chip_tl_errors.2108668495
/workspace/coverage/cover_reg_top/12.xbar_access_same_device.2897202385
/workspace/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.2315998083
/workspace/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.3251824129
/workspace/coverage/cover_reg_top/12.xbar_error_random.255869200
/workspace/coverage/cover_reg_top/12.xbar_random.1392401692
/workspace/coverage/cover_reg_top/12.xbar_random_large_delays.3168803901
/workspace/coverage/cover_reg_top/12.xbar_random_slow_rsp.514170606
/workspace/coverage/cover_reg_top/12.xbar_random_zero_delays.2085761770
/workspace/coverage/cover_reg_top/12.xbar_same_source.3104184354
/workspace/coverage/cover_reg_top/12.xbar_smoke.2528704255
/workspace/coverage/cover_reg_top/12.xbar_smoke_large_delays.3193720939
/workspace/coverage/cover_reg_top/12.xbar_smoke_slow_rsp.2330480622
/workspace/coverage/cover_reg_top/12.xbar_smoke_zero_delays.922982684
/workspace/coverage/cover_reg_top/12.xbar_stress_all.2317588312
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_error.2194201312
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_rand_reset.699405408
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_reset_error.266051463
/workspace/coverage/cover_reg_top/12.xbar_unmapped_addr.2960323898
/workspace/coverage/cover_reg_top/13.chip_csr_mem_rw_with_rand_reset.3202478411
/workspace/coverage/cover_reg_top/13.chip_csr_rw.1341542940
/workspace/coverage/cover_reg_top/13.chip_same_csr_outstanding.2038960603
/workspace/coverage/cover_reg_top/13.xbar_access_same_device.2638044636
/workspace/coverage/cover_reg_top/13.xbar_access_same_device_slow_rsp.699901415
/workspace/coverage/cover_reg_top/13.xbar_error_and_unmapped_addr.514455785
/workspace/coverage/cover_reg_top/13.xbar_error_random.1769509867
/workspace/coverage/cover_reg_top/13.xbar_random.1576224964
/workspace/coverage/cover_reg_top/13.xbar_random_large_delays.3213561168
/workspace/coverage/cover_reg_top/13.xbar_random_slow_rsp.781501480
/workspace/coverage/cover_reg_top/13.xbar_random_zero_delays.3541755272
/workspace/coverage/cover_reg_top/13.xbar_same_source.3266879494
/workspace/coverage/cover_reg_top/13.xbar_smoke.2591625849
/workspace/coverage/cover_reg_top/13.xbar_smoke_large_delays.2421141230
/workspace/coverage/cover_reg_top/13.xbar_smoke_slow_rsp.3684564245
/workspace/coverage/cover_reg_top/13.xbar_smoke_zero_delays.3065067139
/workspace/coverage/cover_reg_top/13.xbar_stress_all.369422104
/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_error.1274235883
/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_reset_error.1742972621
/workspace/coverage/cover_reg_top/13.xbar_unmapped_addr.1933965262
/workspace/coverage/cover_reg_top/14.chip_csr_mem_rw_with_rand_reset.694132188
/workspace/coverage/cover_reg_top/14.chip_same_csr_outstanding.3440517195
/workspace/coverage/cover_reg_top/14.chip_tl_errors.892488858
/workspace/coverage/cover_reg_top/14.xbar_access_same_device.170065294
/workspace/coverage/cover_reg_top/14.xbar_access_same_device_slow_rsp.1475188038
/workspace/coverage/cover_reg_top/14.xbar_error_and_unmapped_addr.1108991311
/workspace/coverage/cover_reg_top/14.xbar_error_random.1048055702
/workspace/coverage/cover_reg_top/14.xbar_random.691470639
/workspace/coverage/cover_reg_top/14.xbar_random_slow_rsp.3601112764
/workspace/coverage/cover_reg_top/14.xbar_random_zero_delays.881631808
/workspace/coverage/cover_reg_top/14.xbar_same_source.3656520872
/workspace/coverage/cover_reg_top/14.xbar_smoke.1351299659
/workspace/coverage/cover_reg_top/14.xbar_smoke_large_delays.106889401
/workspace/coverage/cover_reg_top/14.xbar_smoke_slow_rsp.223781684
/workspace/coverage/cover_reg_top/14.xbar_smoke_zero_delays.755501700
/workspace/coverage/cover_reg_top/14.xbar_stress_all.1847873899
/workspace/coverage/cover_reg_top/14.xbar_stress_all_with_error.2438694261
/workspace/coverage/cover_reg_top/14.xbar_stress_all_with_rand_reset.3231097928
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/workspace/coverage/default/2.chip_sw_spi_device_pinmux_sleep_retention.1855226450
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/workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.29919823
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.2517599404
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_inputs.2000483261
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_outputs.2078430160
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.763827112
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/workspace/coverage/default/2.rom_raw_unlock.1083213454
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/workspace/coverage/default/22.chip_sw_all_escalation_resets.3935730697
/workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.2368787799
/workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.3526590425
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/workspace/coverage/default/29.chip_sw_all_escalation_resets.3090805490
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/workspace/coverage/default/3.chip_tap_straps_testunlock0.1796612768
/workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.2190416445
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/workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.2105629130
/workspace/coverage/default/31.chip_sw_all_escalation_resets.607858336
/workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.2570746397
/workspace/coverage/default/32.chip_sw_all_escalation_resets.1341919215
/workspace/coverage/default/33.chip_sw_all_escalation_resets.690322650
/workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.3909747231
/workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.1386694262
/workspace/coverage/default/35.chip_sw_all_escalation_resets.51467974
/workspace/coverage/default/36.chip_sw_all_escalation_resets.2893769353
/workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.1980559149
/workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.984181828
/workspace/coverage/default/38.chip_sw_all_escalation_resets.4232626080
/workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.3844121425
/workspace/coverage/default/39.chip_sw_all_escalation_resets.1298925667
/workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.53708607
/workspace/coverage/default/4.chip_sw_all_escalation_resets.1358962098
/workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.4119411648
/workspace/coverage/default/4.chip_sw_csrng_edn_concurrency.2511988613
/workspace/coverage/default/4.chip_sw_data_integrity_escalation.3429690980
/workspace/coverage/default/4.chip_sw_lc_ctrl_transition.3146544345
/workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.3817519866
/workspace/coverage/default/4.chip_sw_uart_rand_baudrate.3938242157
/workspace/coverage/default/4.chip_sw_uart_tx_rx.2197808739
/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.1568664234
/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3500430447
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.1587757224
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.1040452552
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.463447196
/workspace/coverage/default/4.chip_tap_straps_dev.467201168
/workspace/coverage/default/4.chip_tap_straps_prod.3414099091
/workspace/coverage/default/4.chip_tap_straps_rma.4285707391
/workspace/coverage/default/4.chip_tap_straps_testunlock0.2977075021
/workspace/coverage/default/40.chip_sw_all_escalation_resets.1504717382
/workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.3965148425
/workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.1390852149
/workspace/coverage/default/43.chip_sw_all_escalation_resets.3498438479
/workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.2296688920
/workspace/coverage/default/44.chip_sw_all_escalation_resets.858302148
/workspace/coverage/default/45.chip_sw_all_escalation_resets.3619597362
/workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.861819183
/workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.4032492823
/workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.2183852606
/workspace/coverage/default/48.chip_sw_all_escalation_resets.2963319554
/workspace/coverage/default/49.chip_sw_all_escalation_resets.975357971
/workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.3051974834
/workspace/coverage/default/5.chip_sw_all_escalation_resets.117929435
/workspace/coverage/default/5.chip_sw_csrng_edn_concurrency.2184520568
/workspace/coverage/default/5.chip_sw_data_integrity_escalation.234693746
/workspace/coverage/default/5.chip_sw_lc_ctrl_transition.1039394367
/workspace/coverage/default/5.chip_sw_uart_rand_baudrate.2198549894
/workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.3289395000
/workspace/coverage/default/50.chip_sw_all_escalation_resets.1782619592
/workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.3675972949
/workspace/coverage/default/51.chip_sw_all_escalation_resets.830733869
/workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.1465088766
/workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.3027099658
/workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.297290908
/workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.4039229074
/workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.2733018194
/workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.407928169
/workspace/coverage/default/58.chip_sw_all_escalation_resets.3670874373
/workspace/coverage/default/59.chip_sw_all_escalation_resets.3304048892
/workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.817827802
/workspace/coverage/default/6.chip_sw_all_escalation_resets.2187779017
/workspace/coverage/default/6.chip_sw_csrng_edn_concurrency.1471666413
/workspace/coverage/default/6.chip_sw_lc_ctrl_transition.317649807
/workspace/coverage/default/6.chip_sw_uart_rand_baudrate.2138305365
/workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.378539888
/workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.716382738
/workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.2406326352
/workspace/coverage/default/62.chip_sw_all_escalation_resets.752266004
/workspace/coverage/default/64.chip_sw_all_escalation_resets.2358613841
/workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.756446988
/workspace/coverage/default/65.chip_sw_all_escalation_resets.1353579185
/workspace/coverage/default/66.chip_sw_all_escalation_resets.790978623
/workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.2166527369
/workspace/coverage/default/67.chip_sw_all_escalation_resets.4002525009
/workspace/coverage/default/68.chip_sw_all_escalation_resets.3701325958
/workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.4084929547
/workspace/coverage/default/69.chip_sw_all_escalation_resets.3031922223
/workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.3497219242
/workspace/coverage/default/7.chip_sw_all_escalation_resets.449349079
/workspace/coverage/default/7.chip_sw_csrng_edn_concurrency.941391246
/workspace/coverage/default/7.chip_sw_lc_ctrl_transition.4175115789
/workspace/coverage/default/7.chip_sw_uart_rand_baudrate.4045323605
/workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.1308658701
/workspace/coverage/default/70.chip_sw_all_escalation_resets.4224085960
/workspace/coverage/default/71.chip_sw_all_escalation_resets.2107411834
/workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.1400108250
/workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.3682497061
/workspace/coverage/default/74.chip_sw_all_escalation_resets.2874064494
/workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.5444066
/workspace/coverage/default/75.chip_sw_all_escalation_resets.508918
/workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.36063770
/workspace/coverage/default/76.chip_sw_all_escalation_resets.4253539610
/workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.1906782957
/workspace/coverage/default/77.chip_sw_all_escalation_resets.623743273
/workspace/coverage/default/78.chip_sw_all_escalation_resets.3053489225
/workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.3874842978
/workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.997835923
/workspace/coverage/default/8.chip_sw_csrng_edn_concurrency.4285945130
/workspace/coverage/default/8.chip_sw_lc_ctrl_transition.4059131038
/workspace/coverage/default/8.chip_sw_uart_rand_baudrate.2841770750
/workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.844158137
/workspace/coverage/default/80.chip_sw_all_escalation_resets.2514504417
/workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.3553814356
/workspace/coverage/default/81.chip_sw_all_escalation_resets.3928425117
/workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.858656540
/workspace/coverage/default/82.chip_sw_all_escalation_resets.2502094992
/workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.4072582765
/workspace/coverage/default/84.chip_sw_all_escalation_resets.2988143920
/workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.1473170800
/workspace/coverage/default/85.chip_sw_all_escalation_resets.2024493092
/workspace/coverage/default/86.chip_sw_all_escalation_resets.329813370
/workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.3854409923
/workspace/coverage/default/87.chip_sw_all_escalation_resets.3919547089
/workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.2052196559
/workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.2290124782
/workspace/coverage/default/89.chip_sw_all_escalation_resets.3093285425
/workspace/coverage/default/9.chip_sw_all_escalation_resets.1787369104
/workspace/coverage/default/9.chip_sw_csrng_edn_concurrency.3268483442
/workspace/coverage/default/9.chip_sw_lc_ctrl_transition.522179904
/workspace/coverage/default/9.chip_sw_uart_rand_baudrate.3798116976
/workspace/coverage/default/90.chip_sw_all_escalation_resets.997637024
/workspace/coverage/default/92.chip_sw_all_escalation_resets.3115311300
/workspace/coverage/default/93.chip_sw_all_escalation_resets.2647049354
/workspace/coverage/default/95.chip_sw_all_escalation_resets.1237878098
/workspace/coverage/default/96.chip_sw_all_escalation_resets.2859837896
/workspace/coverage/default/97.chip_sw_all_escalation_resets.75673444
/workspace/coverage/default/99.chip_sw_all_escalation_resets.3578826838
/workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.1793758878
/workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.1851739404
/workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.4180290392
/workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.3408872537
/workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.4238819953
/workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.3216452664
/workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.3249991543
/workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.219820730

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Total test records in report: 2940

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TEST NO	TEST LOCATION	TEST NAME	STATUS	STARTED	FINISHED	SIMULATION TIME
T1	/workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock.3690855339			Aug 08 08:25:17 PM PDT 24	Aug 08 08:26:57 PM PDT 24	2231560111 ps
T2	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.2180228308			Aug 08 08:16:49 PM PDT 24	Aug 08 08:26:47 PM PDT 24	3343995986 ps
T3	/workspace/coverage/default/1.rom_e2e_self_hash.4042426587			Aug 08 08:37:53 PM PDT 24	Aug 08 10:10:05 PM PDT 24	26245951278 ps
T4	/workspace/coverage/default/0.chip_sw_otp_ctrl_ecc_error_vendor_test.1109570114			Aug 08 08:17:44 PM PDT 24	Aug 08 08:23:03 PM PDT 24	3489271008 ps
T5	/workspace/coverage/default/2.chip_sw_power_sleep_load.763402185			Aug 08 08:44:29 PM PDT 24	Aug 08 08:49:59 PM PDT 24	4440567790 ps
T34	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_power_glitch_reset.855839545			Aug 08 08:18:50 PM PDT 24	Aug 08 08:24:56 PM PDT 24	5078215437 ps
T6	/workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.2361046186			Aug 08 08:57:06 PM PDT 24	Aug 08 09:04:13 PM PDT 24	3991331900 ps
T95	/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.2562112402			Aug 08 08:45:01 PM PDT 24	Aug 08 09:45:30 PM PDT 24	24515579786 ps
T16	/workspace/coverage/default/1.chip_sw_gpio_smoketest.4238044080			Aug 08 08:34:06 PM PDT 24	Aug 08 08:38:41 PM PDT 24	3597219630 ps
T96	/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.3339192944			Aug 08 08:39:55 PM PDT 24	Aug 08 08:43:57 PM PDT 24	2822906460 ps
T35	/workspace/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.1164275858			Aug 08 08:44:40 PM PDT 24	Aug 08 08:52:46 PM PDT 24	4162688885 ps
T36	/workspace/coverage/default/2.chip_sw_flash_crash_alert.1877773146			Aug 08 08:44:09 PM PDT 24	Aug 08 08:55:50 PM PDT 24	4635229320 ps
T52	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.2073379865			Aug 08 08:31:51 PM PDT 24	Aug 08 08:43:17 PM PDT 24	4992237920 ps
T71	/workspace/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.2727219461			Aug 08 08:25:11 PM PDT 24	Aug 08 08:48:44 PM PDT 24	10773244144 ps
T198	/workspace/coverage/default/1.chip_sw_hmac_smoketest.1278044563			Aug 08 08:35:07 PM PDT 24	Aug 08 08:42:00 PM PDT 24	3262282440 ps
T70	/workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.246706922			Aug 08 08:24:33 PM PDT 24	Aug 08 08:26:19 PM PDT 24	2249701016 ps
T126	/workspace/coverage/default/1.chip_sw_entropy_src_csrng.728837433			Aug 08 08:28:42 PM PDT 24	Aug 08 08:52:35 PM PDT 24	6059506368 ps
T75	/workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.3391467284			Aug 08 08:17:55 PM PDT 24	Aug 08 08:21:25 PM PDT 24	2859423853 ps
T154	/workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.2730338489			Aug 08 08:18:38 PM PDT 24	Aug 08 08:28:49 PM PDT 24	5021724346 ps
T217	/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.3194755222			Aug 08 08:24:18 PM PDT 24	Aug 08 08:40:25 PM PDT 24	4868080042 ps
T195	/workspace/coverage/default/55.chip_sw_all_escalation_resets.3714730173			Aug 08 08:54:26 PM PDT 24	Aug 08 09:06:15 PM PDT 24	4845328424 ps
T169	/workspace/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.177264067			Aug 08 08:17:48 PM PDT 24	Aug 08 08:45:47 PM PDT 24	9510088732 ps
T90	/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.1075799536			Aug 08 08:29:14 PM PDT 24	Aug 08 08:54:01 PM PDT 24	12087449720 ps
T170	/workspace/coverage/default/2.chip_sw_clkmgr_off_aes_trans.876555822			Aug 08 08:42:04 PM PDT 24	Aug 08 08:48:05 PM PDT 24	3475686888 ps
T626	/workspace/coverage/default/0.chip_sw_clkmgr_reset_frequency.2573210532			Aug 08 08:19:25 PM PDT 24	Aug 08 08:25:04 PM PDT 24	3307812924 ps
T174	/workspace/coverage/default/94.chip_sw_all_escalation_resets.2394419906			Aug 08 08:57:28 PM PDT 24	Aug 08 09:10:17 PM PDT 24	5586165148 ps
T121	/workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.4213941918			Aug 08 08:16:01 PM PDT 24	Aug 08 08:26:34 PM PDT 24	4816280029 ps
T124	/workspace/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.891162341			Aug 08 08:16:48 PM PDT 24	Aug 08 08:24:23 PM PDT 24	7003244604 ps
T7	/workspace/coverage/default/2.chip_sw_rom_ctrl_integrity_check.1152244771			Aug 08 08:41:21 PM PDT 24	Aug 08 08:53:24 PM PDT 24	9689486817 ps
T220	/workspace/coverage/default/8.chip_sw_all_escalation_resets.3895647680			Aug 08 08:50:01 PM PDT 24	Aug 08 09:00:09 PM PDT 24	5413942244 ps
T119	/workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.2123448738			Aug 08 08:18:42 PM PDT 24	Aug 08 08:25:06 PM PDT 24	3579633265 ps
T8	/workspace/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.124465532			Aug 08 08:16:26 PM PDT 24	Aug 09 12:03:30 AM PDT 24	77695912331 ps
T155	/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.2665516156			Aug 08 08:24:45 PM PDT 24	Aug 08 08:43:18 PM PDT 24	7343089502 ps
T9	/workspace/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.3332540522			Aug 08 08:15:47 PM PDT 24	Aug 08 08:23:13 PM PDT 24	4078681656 ps
T244	/workspace/coverage/default/1.chip_sw_flash_ctrl_ops.1922988858			Aug 08 08:25:19 PM PDT 24	Aug 08 08:37:50 PM PDT 24	4764719248 ps
T609	/workspace/coverage/default/2.chip_sw_aes_masking_off.762364882			Aug 08 08:38:15 PM PDT 24	Aug 08 08:44:29 PM PDT 24	3749008840 ps
T643	/workspace/coverage/default/0.chip_sw_flash_crash_alert.1159843388			Aug 08 08:22:51 PM PDT 24	Aug 08 08:32:06 PM PDT 24	4616210428 ps
T128	/workspace/coverage/default/0.chip_sw_edn_sw_mode.1900447056			Aug 08 08:16:16 PM PDT 24	Aug 08 08:58:30 PM PDT 24	11247173700 ps
T13	/workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.3533788675			Aug 08 08:35:22 PM PDT 24	Aug 08 08:44:54 PM PDT 24	4851327416 ps
T367	/workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.3176692430			Aug 08 08:51:10 PM PDT 24	Aug 08 08:56:55 PM PDT 24	3655836280 ps
T125	/workspace/coverage/default/2.chip_sw_ast_clk_outputs.250626301			Aug 08 08:43:04 PM PDT 24	Aug 08 09:00:43 PM PDT 24	8443222536 ps
T310	/workspace/coverage/default/12.chip_sw_all_escalation_resets.3387062799			Aug 08 08:50:06 PM PDT 24	Aug 08 08:59:50 PM PDT 24	5193367550 ps
T222	/workspace/coverage/default/44.chip_sw_all_escalation_resets.858302148			Aug 08 08:53:24 PM PDT 24	Aug 08 09:05:33 PM PDT 24	5805886952 ps
T666	/workspace/coverage/default/93.chip_sw_all_escalation_resets.2647049354			Aug 08 08:57:41 PM PDT 24	Aug 08 09:05:56 PM PDT 24	6219931930 ps
T224	/workspace/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.2868688868			Aug 08 08:19:46 PM PDT 24	Aug 08 08:27:10 PM PDT 24	4250011698 ps
T221	/workspace/coverage/default/78.chip_sw_all_escalation_resets.3053489225			Aug 08 08:55:26 PM PDT 24	Aug 08 09:04:18 PM PDT 24	6496766520 ps
T143	/workspace/coverage/default/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.1686355635			Aug 08 08:32:22 PM PDT 24	Aug 08 08:39:59 PM PDT 24	5704342162 ps
T151	/workspace/coverage/default/0.chip_sw_uart_rand_baudrate.678700898			Aug 08 08:15:47 PM PDT 24	Aug 08 08:38:26 PM PDT 24	7812374376 ps
T321	/workspace/coverage/default/0.chip_sw_rv_plic_smoketest.3880900618			Aug 08 08:21:19 PM PDT 24	Aug 08 08:25:03 PM PDT 24	2921456180 ps
T49	/workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_invalid_meas.2109275465			Aug 08 08:38:09 PM PDT 24	Aug 08 09:39:38 PM PDT 24	14745176852 ps
T152	/workspace/coverage/default/0.chip_sw_otbn_smoketest.223380273			Aug 08 08:21:18 PM PDT 24	Aug 08 08:56:08 PM PDT 24	9079616120 ps
T214	/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx1.4183680713			Aug 08 08:36:36 PM PDT 24	Aug 08 08:46:32 PM PDT 24	4530933800 ps
T231	/workspace/coverage/default/1.chip_sw_rv_timer_irq.1154002664			Aug 08 08:27:13 PM PDT 24	Aug 08 08:31:39 PM PDT 24	3076181740 ps
T173	/workspace/coverage/default/2.chip_sw_keymgr_sideload_otbn.2701610941			Aug 08 08:40:48 PM PDT 24	Aug 08 09:37:37 PM PDT 24	15453029882 ps
T611	/workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.539738980			Aug 08 08:52:47 PM PDT 24	Aug 08 08:57:44 PM PDT 24	3690577568 ps
T289	/workspace/coverage/default/11.chip_sw_all_escalation_resets.283026728			Aug 08 08:51:14 PM PDT 24	Aug 08 09:02:41 PM PDT 24	5425756000 ps
T50	/workspace/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.68665587			Aug 08 08:15:48 PM PDT 24	Aug 08 08:18:09 PM PDT 24	3878087215 ps
T237	/workspace/coverage/default/0.chip_sw_rv_core_ibex_rnd.3624713069			Aug 08 08:16:32 PM PDT 24	Aug 08 08:32:20 PM PDT 24	5641672026 ps
T295	/workspace/coverage/default/2.chip_sw_aes_entropy.187916995			Aug 08 08:40:30 PM PDT 24	Aug 08 08:44:25 PM PDT 24	2878883800 ps
T235	/workspace/coverage/default/3.chip_sw_csrng_edn_concurrency.1839162155			Aug 08 08:48:37 PM PDT 24	Aug 08 09:40:19 PM PDT 24	13529412440 ps
T51	/workspace/coverage/default/0.chip_sw_exit_test_unlocked_bootstrap.640894662			Aug 08 08:15:55 PM PDT 24	Aug 08 11:12:03 PM PDT 24	58781352200 ps
T91	/workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.717763446			Aug 08 08:51:50 PM PDT 24	Aug 08 09:00:35 PM PDT 24	4164600658 ps
T103	/workspace/coverage/default/0.chip_sw_data_integrity_escalation.2873437502			Aug 08 08:16:00 PM PDT 24	Aug 08 08:24:31 PM PDT 24	5117521800 ps
T104	/workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.3553814356			Aug 08 08:56:53 PM PDT 24	Aug 08 09:02:10 PM PDT 24	3484373480 ps
T69	/workspace/coverage/default/2.chip_sw_exit_test_unlocked_bootstrap.2501372158			Aug 08 08:36:00 PM PDT 24	Aug 08 11:31:36 PM PDT 24	58933314760 ps
T105	/workspace/coverage/default/2.chip_sw_lc_ctrl_rand_to_scrap.3490167778			Aug 08 08:36:40 PM PDT 24	Aug 08 08:41:09 PM PDT 24	2939815717 ps
T19	/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.1623684162			Aug 08 08:31:21 PM PDT 24	Aug 08 08:49:53 PM PDT 24	22622327192 ps
T106	/workspace/coverage/default/0.chip_sw_clkmgr_jitter_frequency.2074595887			Aug 08 08:19:31 PM PDT 24	Aug 08 08:28:57 PM PDT 24	4055555380 ps
T107	/workspace/coverage/default/1.chip_sw_aes_entropy.2514915825			Aug 08 08:28:58 PM PDT 24	Aug 08 08:34:38 PM PDT 24	2966966966 ps
T53	/workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.2552145783			Aug 08 08:20:59 PM PDT 24	Aug 08 08:28:08 PM PDT 24	5086426424 ps
T108	/workspace/coverage/default/1.chip_sw_pwrmgr_wdog_reset.2042979948			Aug 08 08:26:16 PM PDT 24	Aug 08 08:40:53 PM PDT 24	5789413328 ps
T111	/workspace/coverage/default/1.chip_sw_aes_enc_jitter_en.4277625516			Aug 08 08:27:35 PM PDT 24	Aug 08 08:31:50 PM PDT 24	2618895970 ps
T112	/workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en_reduced_freq.1107596239			Aug 08 08:33:29 PM PDT 24	Aug 08 08:38:13 PM PDT 24	2731816104 ps
T113	/workspace/coverage/default/1.chip_sw_pwrmgr_main_power_glitch_reset.391045101			Aug 08 08:25:17 PM PDT 24	Aug 08 08:33:24 PM PDT 24	5490676290 ps
T114	/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.382779362			Aug 08 08:45:14 PM PDT 24	Aug 08 09:07:22 PM PDT 24	9837926388 ps
T115	/workspace/coverage/default/1.chip_sw_flash_scrambling_smoketest.1960444072			Aug 08 08:36:26 PM PDT 24	Aug 08 08:39:29 PM PDT 24	2426169358 ps
T411	/workspace/coverage/default/1.chip_sw_otp_ctrl_ecc_error_vendor_test.2003225382			Aug 08 08:24:50 PM PDT 24	Aug 08 08:29:36 PM PDT 24	2759028161 ps
T83	/workspace/coverage/default/2.rom_raw_unlock.1083213454			Aug 08 08:47:03 PM PDT 24	Aug 08 08:51:01 PM PDT 24	5984636596 ps
T165	/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_prod.3273871660			Aug 08 08:36:33 PM PDT 24	Aug 08 08:59:46 PM PDT 24	7703048936 ps
T54	/workspace/coverage/default/1.chip_rv_dm_ndm_reset_req.2287726889			Aug 08 08:38:30 PM PDT 24	Aug 08 08:48:19 PM PDT 24	3913852424 ps
T84	/workspace/coverage/default/2.chip_jtag_mem_access.3889709380			Aug 08 08:36:07 PM PDT 24	Aug 08 09:02:29 PM PDT 24	13805195320 ps
T72	/workspace/coverage/default/0.chip_tap_straps_testunlock0.399033761			Aug 08 08:19:19 PM PDT 24	Aug 08 08:21:33 PM PDT 24	1809391545 ps
T651	/workspace/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.3906431146			Aug 08 08:35:32 PM PDT 24	Aug 08 08:45:31 PM PDT 24	4487037058 ps
T853	/workspace/coverage/default/2.chip_sw_flash_ctrl_write_clear.3017491389			Aug 08 08:44:56 PM PDT 24	Aug 08 08:51:26 PM PDT 24	3427380792 ps
T300	/workspace/coverage/default/1.chip_sw_all_escalation_resets.77782391			Aug 08 08:24:48 PM PDT 24	Aug 08 08:37:58 PM PDT 24	4641072280 ps
T299	/workspace/coverage/default/89.chip_sw_all_escalation_resets.3093285425			Aug 08 08:57:57 PM PDT 24	Aug 08 09:05:49 PM PDT 24	4643998580 ps
T179	/workspace/coverage/default/0.chip_sw_rv_core_ibex_icache_invalidate.2015329542			Aug 08 08:23:03 PM PDT 24	Aug 08 08:27:03 PM PDT 24	2889866947 ps
T265	/workspace/coverage/default/0.chip_sw_kmac_mode_cshake.2900076915			Aug 08 08:17:15 PM PDT 24	Aug 08 08:21:19 PM PDT 24	2718694328 ps
T171	/workspace/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.3037371160			Aug 08 08:36:23 PM PDT 24	Aug 08 08:46:50 PM PDT 24	4892284674 ps
T20	/workspace/coverage/default/1.chip_sw_pwrmgr_usbdev_smoketest.575820394			Aug 08 08:34:20 PM PDT 24	Aug 08 08:40:03 PM PDT 24	5519070996 ps
T213	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_reset_toggle.1936993817			Aug 08 08:40:07 PM PDT 24	Aug 08 09:10:44 PM PDT 24	8223997032 ps
T266	/workspace/coverage/default/2.chip_sw_clkmgr_reset_frequency.1480913453			Aug 08 08:43:02 PM PDT 24	Aug 08 08:52:31 PM PDT 24	3648834080 ps
T232	/workspace/coverage/default/0.rom_e2e_jtag_inject_test_unlocked0.268087255			Aug 08 08:21:09 PM PDT 24	Aug 08 09:06:40 PM PDT 24	31050298831 ps
T267	/workspace/coverage/default/82.chip_sw_all_escalation_resets.2502094992			Aug 08 08:56:51 PM PDT 24	Aug 08 09:07:12 PM PDT 24	4358426692 ps
T120	/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.125627846			Aug 08 08:44:44 PM PDT 24	Aug 08 08:53:50 PM PDT 24	3780587488 ps
T17	/workspace/coverage/default/2.chip_sw_sleep_pin_retention.2237220488			Aug 08 08:35:15 PM PDT 24	Aug 08 08:41:23 PM PDT 24	3775116730 ps
T389	/workspace/coverage/default/0.chip_sw_coremark.3994803217			Aug 08 08:20:18 PM PDT 24	Aug 09 12:26:03 AM PDT 24	71573437328 ps
T164	/workspace/coverage/default/2.chip_sw_lc_walkthrough_prodend.1692735963			Aug 08 08:36:47 PM PDT 24	Aug 08 08:51:50 PM PDT 24	11190688940 ps
T390	/workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.502337046			Aug 08 08:17:04 PM PDT 24	Aug 08 08:23:02 PM PDT 24	4006704159 ps
T140	/workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.3817519866			Aug 08 08:48:07 PM PDT 24	Aug 08 08:58:30 PM PDT 24	5780723000 ps
T391	/workspace/coverage/default/2.chip_sw_edn_sw_mode.3337391227			Aug 08 08:40:12 PM PDT 24	Aug 08 09:04:28 PM PDT 24	7216490272 ps
T116	/workspace/coverage/default/1.chip_sw_ast_clk_rst_inputs.1990231455			Aug 08 08:32:29 PM PDT 24	Aug 08 09:16:35 PM PDT 24	18157964906 ps
T320	/workspace/coverage/default/1.chip_sw_otbn_randomness.1427656899			Aug 08 08:27:26 PM PDT 24	Aug 08 08:45:35 PM PDT 24	5999544120 ps
T392	/workspace/coverage/default/1.chip_sw_kmac_entropy.2328173274			Aug 08 08:23:18 PM PDT 24	Aug 08 08:28:02 PM PDT 24	2882425576 ps
T393	/workspace/coverage/default/1.chip_sw_clkmgr_off_aes_trans.2521895127			Aug 08 08:30:23 PM PDT 24	Aug 08 08:38:47 PM PDT 24	4560179956 ps
T327	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.2423519048			Aug 08 08:19:52 PM PDT 24	Aug 08 08:30:12 PM PDT 24	4220045495 ps
T268	/workspace/coverage/default/1.chip_sw_keymgr_sideload_aes.2934047279			Aug 08 08:29:57 PM PDT 24	Aug 08 09:10:21 PM PDT 24	9204028918 ps
T18	/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx3.11695907			Aug 08 08:16:34 PM PDT 24	Aug 08 08:26:08 PM PDT 24	3968669890 ps
T661	/workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.4084929547			Aug 08 08:56:15 PM PDT 24	Aug 08 09:03:19 PM PDT 24	3814913940 ps
T46	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.499767218			Aug 08 08:24:49 PM PDT 24	Aug 08 09:22:00 PM PDT 24	14677995049 ps
T127	/workspace/coverage/default/0.chip_sw_entropy_src_csrng.3838978242			Aug 08 08:20:35 PM PDT 24	Aug 08 08:57:44 PM PDT 24	8124530668 ps
T290	/workspace/coverage/default/41.chip_sw_all_escalation_resets.2093178912			Aug 08 08:52:52 PM PDT 24	Aug 08 09:00:36 PM PDT 24	4487695768 ps
T336	/workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en.857071571			Aug 08 08:21:36 PM PDT 24	Aug 08 08:25:29 PM PDT 24	2206326654 ps
T672	/workspace/coverage/default/0.chip_sw_alert_handler_ping_ok.2327117014			Aug 08 08:20:48 PM PDT 24	Aug 08 08:43:27 PM PDT 24	8327784324 ps
T854	/workspace/coverage/default/1.chip_sw_clkmgr_sleep_frequency.1713247310			Aug 08 08:31:00 PM PDT 24	Aug 08 08:41:19 PM PDT 24	4565427766 ps
T153	/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.4065360456			Aug 08 08:18:28 PM PDT 24	Aug 08 09:24:03 PM PDT 24	18443596664 ps
T27	/workspace/coverage/default/1.chip_sw_sleep_pin_retention.4187419202			Aug 08 08:23:45 PM PDT 24	Aug 08 08:29:31 PM PDT 24	3251164502 ps
T218	/workspace/coverage/default/2.chip_sw_pattgen_ios.3110651934			Aug 08 08:33:53 PM PDT 24	Aug 08 08:37:12 PM PDT 24	3245178304 ps
T47	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod.421661517			Aug 08 08:29:17 PM PDT 24	Aug 08 10:14:38 PM PDT 24	23458025880 ps
T122	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.1457103705			Aug 08 08:42:33 PM PDT 24	Aug 08 08:52:49 PM PDT 24	5354892902 ps
T269	/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_prod.4164721185			Aug 08 08:30:03 PM PDT 24	Aug 08 08:56:22 PM PDT 24	8358335144 ps
T270	/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_dev.100340995			Aug 08 08:36:29 PM PDT 24	Aug 08 09:01:37 PM PDT 24	6912199404 ps
T206	/workspace/coverage/default/1.chip_sw_inject_scramble_seed.164689669			Aug 08 08:23:23 PM PDT 24	Aug 08 11:31:19 PM PDT 24	65763099559 ps
T373	/workspace/coverage/default/2.rom_e2e_asm_init_rma.380334252			Aug 08 08:49:29 PM PDT 24	Aug 08 09:53:02 PM PDT 24	14662508393 ps
T92	/workspace/coverage/default/1.chip_sw_alert_handler_entropy.2330391635			Aug 08 08:27:43 PM PDT 24	Aug 08 08:32:37 PM PDT 24	3060012397 ps
T28	/workspace/coverage/default/0.chip_sw_gpio.2648734561			Aug 08 08:15:29 PM PDT 24	Aug 08 08:21:41 PM PDT 24	3646740239 ps
T94	/workspace/coverage/default/0.chip_sw_gpio_smoketest.166268983			Aug 08 08:22:20 PM PDT 24	Aug 08 08:26:46 PM PDT 24	2779840137 ps
T667	/workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.716382738			Aug 08 08:55:42 PM PDT 24	Aug 08 09:00:56 PM PDT 24	4514706360 ps
T123	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.2215917621			Aug 08 08:19:08 PM PDT 24	Aug 08 08:28:35 PM PDT 24	4826780904 ps
T271	/workspace/coverage/default/2.chip_sw_keymgr_sideload_aes.4051611723			Aug 08 08:41:08 PM PDT 24	Aug 08 09:13:47 PM PDT 24	9483834130 ps
T418	/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.1226228276			Aug 08 08:18:26 PM PDT 24	Aug 08 09:20:29 PM PDT 24	17259935944 ps
T175	/workspace/coverage/default/2.chip_sw_lc_walkthrough_testunlocks.1951460905			Aug 08 08:36:30 PM PDT 24	Aug 08 09:09:16 PM PDT 24	24583245812 ps
T180	/workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.2885605817			Aug 08 08:19:42 PM PDT 24	Aug 08 08:37:15 PM PDT 24	10484054477 ps
T176	/workspace/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.1450418201			Aug 08 08:15:49 PM PDT 24	Aug 08 08:19:55 PM PDT 24	2754589753 ps
T22	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_outputs.1237601300			Aug 08 08:15:49 PM PDT 24	Aug 08 08:22:16 PM PDT 24	3611079518 ps
T745	/workspace/coverage/default/68.chip_sw_all_escalation_resets.3701325958			Aug 08 08:56:02 PM PDT 24	Aug 08 09:05:23 PM PDT 24	4854873360 ps
T663	/workspace/coverage/default/24.chip_sw_all_escalation_resets.3297700111			Aug 08 08:52:41 PM PDT 24	Aug 08 09:03:46 PM PDT 24	6116872488 ps
T177	/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.1453197546			Aug 08 08:20:35 PM PDT 24	Aug 08 08:28:36 PM PDT 24	4940079525 ps
T77	/workspace/coverage/default/0.chip_sw_usb_ast_clk_calib.1100283481			Aug 08 08:22:02 PM PDT 24	Aug 08 08:26:29 PM PDT 24	3004548178 ps
T144	/workspace/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.3390058132			Aug 08 08:36:22 PM PDT 24	Aug 08 08:43:51 PM PDT 24	8302489224 ps
T236	/workspace/coverage/default/0.chip_sw_edn_boot_mode.707624057			Aug 08 08:18:23 PM PDT 24	Aug 08 08:27:27 PM PDT 24	3510919750 ps
T331	/workspace/coverage/default/1.chip_sw_pattgen_ios.735854810			Aug 08 08:22:30 PM PDT 24	Aug 08 08:26:48 PM PDT 24	3032230792 ps
T625	/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_por_reset.3934540568			Aug 08 08:27:56 PM PDT 24	Aug 08 08:37:00 PM PDT 24	6276819626 ps
T245	/workspace/coverage/default/1.chip_sw_lc_ctrl_rand_to_scrap.3230077558			Aug 08 08:25:20 PM PDT 24	Aug 08 08:28:12 PM PDT 24	3568414663 ps
T76	/workspace/coverage/default/1.chip_tap_straps_testunlock0.261131103			Aug 08 08:31:44 PM PDT 24	Aug 08 08:47:31 PM PDT 24	7375804497 ps
T48	/workspace/coverage/default/0.rom_e2e_shutdown_output.2067233350			Aug 08 08:24:46 PM PDT 24	Aug 08 09:33:51 PM PDT 24	25748168660 ps
T340	/workspace/coverage/default/2.chip_sw_flash_ctrl_idle_low_power.1111144927			Aug 08 08:36:38 PM PDT 24	Aug 08 08:42:37 PM PDT 24	2975335624 ps
T855	/workspace/coverage/default/0.chip_sw_csrng_smoketest.1073222791			Aug 08 08:19:14 PM PDT 24	Aug 08 08:22:24 PM PDT 24	2948693868 ps
T631	/workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock.3106499802			Aug 08 08:39:50 PM PDT 24	Aug 08 08:41:35 PM PDT 24	2022822392 ps
T856	/workspace/coverage/default/1.chip_sw_hmac_enc.3673391328			Aug 08 08:28:48 PM PDT 24	Aug 08 08:32:11 PM PDT 24	2669260322 ps
T324	/workspace/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.3086532784			Aug 08 08:20:12 PM PDT 24	Aug 08 08:26:33 PM PDT 24	3836662816 ps
T272	/workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.2829361168			Aug 08 08:18:55 PM PDT 24	Aug 08 08:37:17 PM PDT 24	8134064720 ps
T857	/workspace/coverage/default/2.chip_sw_pwrmgr_wdog_reset.1026984032			Aug 08 08:37:49 PM PDT 24	Aug 08 08:47:30 PM PDT 24	5230904534 ps
T415	/workspace/coverage/default/1.chip_sw_edn_entropy_reqs.753668309			Aug 08 08:28:58 PM PDT 24	Aug 08 08:45:12 PM PDT 24	6624559896 ps
T715	/workspace/coverage/default/49.chip_sw_all_escalation_resets.975357971			Aug 08 08:54:34 PM PDT 24	Aug 08 09:04:42 PM PDT 24	4961410156 ps
T858	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.510243002			Aug 08 08:41:57 PM PDT 24	Aug 08 08:52:22 PM PDT 24	3660827512 ps
T859	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.4020191736			Aug 08 08:42:13 PM PDT 24	Aug 08 08:50:49 PM PDT 24	4096514898 ps
T129	/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_wake_5_bug.1251657759			Aug 08 08:43:15 PM PDT 24	Aug 08 08:51:01 PM PDT 24	6175268952 ps
T673	/workspace/coverage/default/85.chip_sw_all_escalation_resets.2024493092			Aug 08 08:57:32 PM PDT 24	Aug 08 09:06:45 PM PDT 24	4381923700 ps
T860	/workspace/coverage/default/8.chip_sw_lc_ctrl_transition.4059131038			Aug 08 08:49:27 PM PDT 24	Aug 08 09:04:20 PM PDT 24	11088106221 ps
T861	/workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.1641693793			Aug 08 08:44:07 PM PDT 24	Aug 08 09:02:18 PM PDT 24	7652358265 ps
T721	/workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.2939721404			Aug 08 08:52:02 PM PDT 24	Aug 08 08:59:30 PM PDT 24	4013185692 ps
T862	/workspace/coverage/default/2.chip_sw_entropy_src_ast_rng_req.1627246901			Aug 08 08:40:54 PM PDT 24	Aug 08 08:44:15 PM PDT 24	3004958528 ps
T308	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.2695922951			Aug 08 08:16:47 PM PDT 24	Aug 08 08:31:57 PM PDT 24	5244742410 ps
T674	/workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.2735254973			Aug 08 08:51:38 PM PDT 24	Aug 08 08:58:32 PM PDT 24	3836298840 ps
T246	/workspace/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.339470459			Aug 08 08:17:58 PM PDT 24	Aug 08 08:20:36 PM PDT 24	3011013044 ps
T329	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.2077048818			Aug 08 08:18:33 PM PDT 24	Aug 08 08:27:43 PM PDT 24	4207951458 ps
T382	/workspace/coverage/default/2.chip_sw_kmac_app_rom.3870469106			Aug 08 08:40:07 PM PDT 24	Aug 08 08:43:40 PM PDT 24	2835796720 ps
T650	/workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.1841332110			Aug 08 08:54:11 PM PDT 24	Aug 08 09:01:33 PM PDT 24	3667565278 ps
T145	/workspace/coverage/default/0.chip_sw_sensor_ctrl_status.1546750333			Aug 08 08:17:44 PM PDT 24	Aug 08 08:23:32 PM PDT 24	2689241954 ps
T21	/workspace/coverage/default/0.chip_sw_usbdev_pincfg.1472080371			Aug 08 08:16:08 PM PDT 24	Aug 08 10:22:42 PM PDT 24	31361590900 ps
T185	/workspace/coverage/default/1.chip_sw_csrng_fuse_en_sw_app_read_test.2108971447			Aug 08 08:28:58 PM PDT 24	Aug 08 08:36:06 PM PDT 24	4118758984 ps
T301	/workspace/coverage/default/1.chip_plic_all_irqs_0.2769122595			Aug 08 08:29:55 PM PDT 24	Aug 08 08:52:02 PM PDT 24	6561315526 ps
T62	/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_wake_ups.1468127713			Aug 08 08:43:05 PM PDT 24	Aug 08 09:02:50 PM PDT 24	23333424600 ps
T863	/workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.4119411648			Aug 08 08:49:05 PM PDT 24	Aug 08 08:55:21 PM PDT 24	7507334836 ps
T726	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.3072350562			Aug 08 08:38:39 PM PDT 24	Aug 08 08:46:00 PM PDT 24	3418410840 ps
T419	/workspace/coverage/default/1.chip_sw_edn_auto_mode.2325550260			Aug 08 08:28:46 PM PDT 24	Aug 08 08:43:41 PM PDT 24	4990701040 ps
T315	/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.1040452552			Aug 08 08:47:25 PM PDT 24	Aug 08 08:58:01 PM PDT 24	3856613950 ps
T864	/workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en.3056743618			Aug 08 08:41:01 PM PDT 24	Aug 08 08:46:45 PM PDT 24	2718354160 ps
T247	/workspace/coverage/default/4.chip_sw_data_integrity_escalation.3429690980			Aug 08 08:50:37 PM PDT 24	Aug 08 08:58:29 PM PDT 24	4895317778 ps
T514	/workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.1659002845			Aug 08 08:19:03 PM PDT 24	Aug 08 08:34:22 PM PDT 24	8398478700 ps
T229	/workspace/coverage/default/1.chip_sw_plic_sw_irq.1732457577			Aug 08 08:30:26 PM PDT 24	Aug 08 08:34:22 PM PDT 24	2841491378 ps
T215	/workspace/coverage/default/1.chip_sw_uart_rand_baudrate.603459859			Aug 08 08:21:59 PM PDT 24	Aug 08 09:04:24 PM PDT 24	13057900894 ps
T865	/workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.250756636			Aug 08 08:39:56 PM PDT 24	Aug 08 08:44:27 PM PDT 24	2789785461 ps
T332	/workspace/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.896765788			Aug 08 08:24:05 PM PDT 24	Aug 08 08:38:37 PM PDT 24	6634360948 ps
T333	/workspace/coverage/default/57.chip_sw_all_escalation_resets.1905739837			Aug 08 08:55:24 PM PDT 24	Aug 08 09:08:10 PM PDT 24	6325756960 ps
T156	/workspace/coverage/default/0.chip_plic_all_irqs_10.2818478712			Aug 08 08:19:52 PM PDT 24	Aug 08 08:28:39 PM PDT 24	3781778920 ps
T334	/workspace/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3247603381			Aug 08 08:38:10 PM PDT 24	Aug 08 08:44:31 PM PDT 24	19216667952 ps
T688	/workspace/coverage/default/18.chip_sw_all_escalation_resets.2209776191			Aug 08 08:51:27 PM PDT 24	Aug 08 09:01:52 PM PDT 24	5219948132 ps
T718	/workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.2621034512			Aug 08 08:49:15 PM PDT 24	Aug 08 08:58:37 PM PDT 24	4322743218 ps
T717	/workspace/coverage/default/0.chip_sw_aes_masking_off.341504034			Aug 08 08:17:46 PM PDT 24	Aug 08 08:23:21 PM PDT 24	3077414807 ps
T117	/workspace/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.3186942963			Aug 08 08:44:50 PM PDT 24	Aug 08 09:46:47 PM PDT 24	21400592559 ps
T209	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_inputs.2000483261			Aug 08 08:39:50 PM PDT 24	Aug 08 08:45:14 PM PDT 24	3102109063 ps
T226	/workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.2733018194			Aug 08 08:55:47 PM PDT 24	Aug 08 09:03:35 PM PDT 24	4077000750 ps
T257	/workspace/coverage/default/2.chip_sw_gpio_smoketest.2104290327			Aug 08 08:45:34 PM PDT 24	Aug 08 08:49:44 PM PDT 24	2868968673 ps
T85	/workspace/coverage/default/0.chip_jtag_csr_rw.499411181			Aug 08 08:10:33 PM PDT 24	Aug 08 08:28:44 PM PDT 24	11069225250 ps
T216	/workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.1873391562			Aug 08 08:17:03 PM PDT 24	Aug 08 08:28:20 PM PDT 24	4683913380 ps
T258	/workspace/coverage/default/2.chip_sw_alert_handler_ping_timeout.1776782730			Aug 08 08:39:32 PM PDT 24	Aug 08 08:49:21 PM PDT 24	5213252500 ps
T259	/workspace/coverage/default/1.chip_sw_lc_ctrl_transition.4174354990			Aug 08 08:26:19 PM PDT 24	Aug 08 08:33:59 PM PDT 24	5346256469 ps
T260	/workspace/coverage/default/1.chip_sw_entropy_src_ast_rng_req.4272047602			Aug 08 08:28:21 PM PDT 24	Aug 08 08:34:04 PM PDT 24	3194178520 ps
T63	/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.4006644140			Aug 08 08:43:30 PM PDT 24	Aug 08 09:10:14 PM PDT 24	24212306148 ps
T261	/workspace/coverage/default/3.chip_tap_straps_prod.1108767658			Aug 08 08:47:01 PM PDT 24	Aug 08 08:49:34 PM PDT 24	2563875307 ps
T29	/workspace/coverage/default/1.chip_sw_gpio.659413969			Aug 08 08:22:41 PM PDT 24	Aug 08 08:32:24 PM PDT 24	4696403704 ps
T866	/workspace/coverage/default/2.chip_sw_rv_dm_access_after_wakeup.848768848			Aug 08 08:43:40 PM PDT 24	Aug 08 08:51:59 PM PDT 24	6924130804 ps
T339	/workspace/coverage/default/34.chip_sw_all_escalation_resets.1448889430			Aug 08 08:51:54 PM PDT 24	Aug 08 09:07:21 PM PDT 24	5207218904 ps
T161	/workspace/coverage/default/0.chip_sw_rstmgr_alert_info.2881154566			Aug 08 08:16:58 PM PDT 24	Aug 08 08:43:15 PM PDT 24	10711256996 ps
T39	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.620719352			Aug 08 08:37:01 PM PDT 24	Aug 08 08:44:14 PM PDT 24	5440543732 ps
T867	/workspace/coverage/default/2.chip_tap_straps_prod.1590909041			Aug 08 08:43:28 PM PDT 24	Aug 08 08:46:38 PM PDT 24	3210090753 ps
T868	/workspace/coverage/default/0.chip_sw_otp_ctrl_smoketest.3806131405			Aug 08 08:22:47 PM PDT 24	Aug 08 08:25:46 PM PDT 24	2074494060 ps
T287	/workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3594930149			Aug 08 08:46:55 PM PDT 24	Aug 08 09:05:55 PM PDT 24	8578647069 ps
T652	/workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.2406326352			Aug 08 08:56:13 PM PDT 24	Aug 08 09:02:24 PM PDT 24	4097624568 ps
T869	/workspace/coverage/default/1.chip_sw_aon_timer_smoketest.1651868552			Aug 08 08:33:37 PM PDT 24	Aug 08 08:39:12 PM PDT 24	2929895512 ps
T870	/workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.3462752583			Aug 08 08:29:23 PM PDT 24	Aug 08 08:39:43 PM PDT 24	6842201366 ps
T698	/workspace/coverage/default/58.chip_sw_all_escalation_resets.3670874373			Aug 08 08:55:09 PM PDT 24	Aug 08 09:02:54 PM PDT 24	4295586500 ps
T288	/workspace/coverage/default/2.chip_sw_clkmgr_off_peri.1560111369			Aug 08 08:42:20 PM PDT 24	Aug 08 09:00:25 PM PDT 24	12268220420 ps
T871	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.4233697813			Aug 08 08:24:57 PM PDT 24	Aug 08 09:50:48 PM PDT 24	17946054757 ps
T662	/workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.3686411964			Aug 08 08:58:09 PM PDT 24	Aug 08 09:03:45 PM PDT 24	3692044536 ps
T732	/workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.2190416445			Aug 08 08:52:03 PM PDT 24	Aug 08 08:58:49 PM PDT 24	4688159956 ps
T872	/workspace/coverage/default/0.chip_sw_aes_idle.3492238127			Aug 08 08:16:19 PM PDT 24	Aug 08 08:20:39 PM PDT 24	3153376044 ps
T303	/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx3.2073275718			Aug 08 08:23:33 PM PDT 24	Aug 08 08:35:44 PM PDT 24	4990823832 ps
T60	/workspace/coverage/default/1.chip_sw_sleep_pin_wake.1818509527			Aug 08 08:25:55 PM PDT 24	Aug 08 08:29:32 PM PDT 24	3254928754 ps
T402	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.534401884			Aug 08 08:31:19 PM PDT 24	Aug 08 08:42:04 PM PDT 24	4363774886 ps
T403	/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.1624450982			Aug 08 08:37:46 PM PDT 24	Aug 08 09:02:33 PM PDT 24	17598858984 ps
T404	/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_prod.1931360791			Aug 08 08:40:45 PM PDT 24	Aug 08 09:08:54 PM PDT 24	7709760452 ps
T405	/workspace/coverage/default/2.chip_sw_otp_ctrl_ecc_error_vendor_test.1036659119			Aug 08 08:38:08 PM PDT 24	Aug 08 08:43:27 PM PDT 24	3307142574 ps
T406	/workspace/coverage/default/39.chip_sw_all_escalation_resets.1298925667			Aug 08 08:53:34 PM PDT 24	Aug 08 09:05:07 PM PDT 24	5824376344 ps
T407	/workspace/coverage/default/2.chip_sw_sram_ctrl_smoketest.1240370848			Aug 08 08:46:19 PM PDT 24	Aug 08 08:50:15 PM PDT 24	3146510584 ps
T248	/workspace/coverage/default/1.chip_sw_otbn_mem_scramble.2868513011			Aug 08 08:26:08 PM PDT 24	Aug 08 08:32:46 PM PDT 24	3835098048 ps
T408	/workspace/coverage/default/1.chip_sw_keymgr_sideload_kmac.3384913426			Aug 08 08:30:07 PM PDT 24	Aug 08 09:02:54 PM PDT 24	9274496760 ps
T409	/workspace/coverage/default/1.chip_sw_clkmgr_jitter_frequency.1073490214			Aug 08 08:36:39 PM PDT 24	Aug 08 08:46:04 PM PDT 24	4205136398 ps
T696	/workspace/coverage/default/90.chip_sw_all_escalation_resets.997637024			Aug 08 08:58:03 PM PDT 24	Aug 08 09:09:44 PM PDT 24	5204090564 ps
T97	/workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.1238861730			Aug 08 08:52:05 PM PDT 24	Aug 08 08:59:01 PM PDT 24	4011946162 ps
T873	/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx1.2599985961			Aug 08 08:22:54 PM PDT 24	Aug 08 08:32:54 PM PDT 24	4142901240 ps
T343	/workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.3335729080			Aug 08 08:32:17 PM PDT 24	Aug 08 08:42:34 PM PDT 24	4825305345 ps
T306	/workspace/coverage/default/2.chip_plic_all_irqs_0.3734467542			Aug 08 08:41:44 PM PDT 24	Aug 08 09:03:12 PM PDT 24	5902999134 ps
T73	/workspace/coverage/default/3.chip_tap_straps_testunlock0.1796612768			Aug 08 08:46:50 PM PDT 24	Aug 08 08:59:31 PM PDT 24	7115453682 ps
T286	/workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.3909747231			Aug 08 08:52:40 PM PDT 24	Aug 08 09:00:25 PM PDT 24	3830918600 ps
T874	/workspace/coverage/default/4.chip_tap_straps_prod.3414099091			Aug 08 08:48:00 PM PDT 24	Aug 08 09:10:02 PM PDT 24	14452100677 ps
T314	/workspace/coverage/default/3.chip_sw_uart_tx_rx.1451690935			Aug 08 08:49:14 PM PDT 24	Aug 08 08:57:10 PM PDT 24	4184444200 ps
T130	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3684335951			Aug 08 08:17:49 PM PDT 24	Aug 08 08:24:46 PM PDT 24	5303785788 ps
T131	/workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.625122889			Aug 08 08:50:26 PM PDT 24	Aug 08 08:59:20 PM PDT 24	4983044418 ps
T172	/workspace/coverage/default/0.chip_sw_flash_rma_unlocked.3261497798			Aug 08 08:14:45 PM PDT 24	Aug 08 09:41:19 PM PDT 24	42795643172 ps
T655	/workspace/coverage/default/51.chip_sw_all_escalation_resets.830733869			Aug 08 08:54:42 PM PDT 24	Aug 08 09:04:30 PM PDT 24	4315297800 ps
T875	/workspace/coverage/default/0.chip_sw_edn_auto_mode.857261789			Aug 08 08:18:45 PM PDT 24	Aug 08 08:42:20 PM PDT 24	5786326564 ps
T93	/workspace/coverage/default/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.1769686533			Aug 08 08:39:52 PM PDT 24	Aug 09 12:17:35 AM PDT 24	256249925256 ps
T764	/workspace/coverage/default/3.chip_sw_all_escalation_resets.3332681449			Aug 08 08:46:41 PM PDT 24	Aug 08 08:56:54 PM PDT 24	4862548200 ps
T701	/workspace/coverage/default/19.chip_sw_all_escalation_resets.1531678895			Aug 08 08:51:37 PM PDT 24	Aug 08 08:59:43 PM PDT 24	5929568760 ps
T708	/workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.3682497061			Aug 08 08:55:56 PM PDT 24	Aug 08 09:02:45 PM PDT 24	3967083980 ps
T210	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.4164697396			Aug 08 08:15:18 PM PDT 24	Aug 08 08:22:19 PM PDT 24	4443982467 ps
T876	/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_por_reset.3765540987			Aug 08 08:37:02 PM PDT 24	Aug 08 08:48:52 PM PDT 24	5879600693 ps