Unified Coverage Report :: Group Instance : rv_timer

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T80	1		T420	1		T519	1
small_delay	681	1			T81	1		T89	1		T87	1
zero	619	1			T82	1		T88	1		T516	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T80	1		T420	1		T519	1
small_delay	981	1			T81	1		T89	1		T87	1
zero	619	1			T82	1		T88	1		T516	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T80	1		T420	1		T519	1
small_delay	681	1			T81	1		T89	1		T87	1
zero	619	1			T82	1		T88	1		T516	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T80	1		T420	1		T519	1
small_delay	981	1			T81	1		T89	1		T87	1
zero	619	1			T82	1		T88	1		T516	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T80	1		T420	1		T519	1
small_delay	681	1			T81	1		T89	1		T87	1
zero	619	1			T82	1		T88	1		T516	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T80	1		T420	1		T519	1
small_delay	981	1			T81	1		T89	1		T87	1
zero	619	1			T82	1		T88	1		T516	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T80	1		T420	1		T519	1
small_delay	681	1			T81	1		T89	1		T87	1
zero	619	1			T82	1		T88	1		T516	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T80	1		T420	1		T519	1
small_delay	981	1			T81	1		T89	1		T87	1
zero	619	1			T82	1		T88	1		T516	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T80	1		T420	1		T519	1
small_delay	681	1			T81	1		T89	1		T87	1
zero	619	1			T82	1		T88	1		T516	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T80	1		T420	1		T519	1
small_delay	981	1			T81	1		T89	1		T87	1
zero	619	1			T82	1		T88	1		T516	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T80	1		T420	1		T519	1
small_delay	681	1			T81	1		T89	1		T87	1
zero	619	1			T82	1		T88	1		T516	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T80	1		T420	1		T519	1
small_delay	981	1			T81	1		T89	1		T87	1
zero	619	1			T82	1		T88	1		T516	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T80	1		T420	1		T519	1
small_delay	681	1			T81	1		T89	1		T87	1
zero	619	1			T82	1		T88	1		T516	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T80	1		T420	1		T519	1
small_delay	981	1			T81	1		T89	1		T87	1
zero	619	1			T82	1		T88	1		T516	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T80	1		T420	1		T519	1
small_delay	681	1			T81	1		T89	1		T87	1
zero	619	1			T82	1		T88	1		T516	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T80	1		T420	1		T519	1
small_delay	981	1			T81	1		T89	1		T87	1
zero	619	1			T82	1		T88	1		T516	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T80	1		T420	1		T519	1
small_delay	681	1			T81	1		T89	1		T87	1
zero	619	1			T82	1		T88	1		T516	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T80	1		T420	1		T519	1
small_delay	981	1			T81	1		T89	1		T87	1
zero	619	1			T82	1		T88	1		T516	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T80	1		T420	1		T519	1
small_delay	681	1			T81	1		T89	1		T87	1
zero	619	1			T82	1		T88	1		T516	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T80	1		T420	1		T519	1
small_delay	981	1			T81	1		T89	1		T87	1
zero	619	1			T82	1		T88	1		T516	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T80	1		T420	1		T519	1
small_delay	681	1			T81	1		T89	1		T87	1
zero	619	1			T82	1		T88	1		T516	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T80	1		T420	1		T519	1
small_delay	981	1			T81	1		T89	1		T87	1
zero	619	1			T82	1		T88	1		T516	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T80	1		T420	1		T519	1
small_delay	681	1			T81	1		T89	1		T87	1
zero	619	1			T82	1		T88	1		T516	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T80	1		T420	1		T519	1
small_delay	981	1			T81	1		T89	1		T87	1
zero	619	1			T82	1		T88	1		T516	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T80	1		T420	1		T519	1
small_delay	681	1			T81	1		T89	1		T87	1
zero	619	1			T82	1		T88	1		T516	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T80	1		T420	1		T519	1
small_delay	981	1			T81	1		T89	1		T87	1
zero	619	1			T82	1		T88	1		T516	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T80	1		T420	1		T519	1
small_delay	681	1			T81	1		T89	1		T87	1
zero	619	1			T82	1		T88	1		T516	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T80	1		T420	1		T519	1
small_delay	981	1			T81	1		T89	1		T87	1
zero	619	1			T82	1		T88	1		T516	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T80	1		T420	1		T519	1
small_delay	681	1			T81	1		T89	1		T87	1
zero	619	1			T82	1		T88	1		T516	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T80	1		T420	1		T519	1
small_delay	981	1			T81	1		T89	1		T87	1
zero	619	1			T82	1		T88	1		T516	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T80	1		T420	1		T519	1
small_delay	681	1			T81	1		T89	1		T87	1
zero	619	1			T82	1		T88	1		T516	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T80	1		T420	1		T519	1
small_delay	981	1			T81	1		T89	1		T87	1
zero	619	1			T82	1		T88	1		T516	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T80	1		T420	1		T519	1
small_delay	681	1			T81	1		T89	1		T87	1
zero	619	1			T82	1		T88	1		T516	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T80	1		T420	1		T519	1
small_delay	981	1			T81	1		T89	1		T87	1
zero	619	1			T82	1		T88	1		T516	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T80	1		T420	1		T519	1
small_delay	681	1			T81	1		T89	1		T87	1
zero	619	1			T82	1		T88	1		T516	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T80	1		T420	1		T519	1
small_delay	981	1			T81	1		T89	1		T87	1
zero	619	1			T82	1		T88	1		T516	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T80	1		T420	1		T519	1
small_delay	681	1			T81	1		T89	1		T87	1
zero	619	1			T82	1		T88	1		T516	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T80	1		T420	1		T519	1
small_delay	981	1			T81	1		T89	1		T87	1
zero	619	1			T82	1		T88	1		T516	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T80	1		T420	1		T519	1
small_delay	681	1			T81	1		T89	1		T87	1
zero	619	1			T82	1		T88	1		T516	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T80	1		T420	1		T519	1
small_delay	981	1			T81	1		T89	1		T87	1
zero	619	1			T82	1		T88	1		T516	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T80	1		T420	1		T519	1
small_delay	681	1			T81	1		T89	1		T87	1
zero	619	1			T82	1		T88	1		T516	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T80	1		T420	1		T519	1
small_delay	981	1			T81	1		T89	1		T87	1
zero	619	1			T82	1		T88	1		T516	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T80	1		T420	1		T519	1
small_delay	681	1			T81	1		T89	1		T87	1
zero	619	1			T82	1		T88	1		T516	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T80	1		T420	1		T519	1
small_delay	981	1			T81	1		T89	1		T87	1
zero	619	1			T82	1		T88	1		T516	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T80	1		T420	1		T519	1
small_delay	681	1			T81	1		T89	1		T87	1
zero	619	1			T82	1		T88	1		T516	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T80	1		T420	1		T519	1
small_delay	981	1			T81	1		T89	1		T87	1
zero	619	1			T82	1		T88	1		T516	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T80	1		T420	1		T519	1
small_delay	681	1			T81	1		T89	1		T87	1
zero	619	1			T82	1		T88	1		T516	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T80	1		T420	1		T519	1
small_delay	981	1			T81	1		T89	1		T87	1
zero	619	1			T82	1		T88	1		T516	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T80	1		T420	1		T519	1
small_delay	681	1			T81	1		T89	1		T87	1
zero	619	1			T82	1		T88	1		T516	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T80	1		T420	1		T519	1
small_delay	981	1			T81	1		T89	1		T87	1
zero	619	1			T82	1		T88	1		T516	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T80	1		T420	1		T519	1
small_delay	681	1			T81	1		T89	1		T87	1
zero	619	1			T82	1		T88	1		T516	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T80	1		T420	1		T519	1
small_delay	981	1			T81	1		T89	1		T87	1
zero	619	1			T82	1		T88	1		T516	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T80	1		T420	1		T519	1
small_delay	681	1			T81	1		T89	1		T87	1
zero	619	1			T82	1		T88	1		T516	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T80	1		T420	1		T519	1
small_delay	981	1			T81	1		T89	1		T87	1
zero	619	1			T82	1		T88	1		T516	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T80	1		T420	1		T519	1
small_delay	681	1			T81	1		T89	1		T87	1
zero	619	1			T82	1		T88	1		T516	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T80	1		T420	1		T519	1
small_delay	981	1			T81	1		T89	1		T87	1
zero	619	1			T82	1		T88	1		T516	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T80	1		T420	1		T519	1
small_delay	681	1			T81	1		T89	1		T87	1
zero	619	1			T82	1		T88	1		T516	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T80	1		T420	1		T519	1
small_delay	981	1			T81	1		T89	1		T87	1
zero	619	1			T82	1		T88	1		T516	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T80	1		T420	1		T519	1
small_delay	681	1			T81	1		T89	1		T87	1
zero	619	1			T82	1		T88	1		T516	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T80	1		T420	1		T519	1
small_delay	981	1			T81	1		T89	1		T87	1
zero	619	1			T82	1		T88	1		T516	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T80	1		T420	1		T519	1
small_delay	681	1			T81	1		T89	1		T87	1
zero	619	1			T82	1		T88	1		T516	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T80	1		T420	1		T519	1
small_delay	981	1			T81	1		T89	1		T87	1
zero	619	1			T82	1		T88	1		T516	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T80	1		T420	1		T519	1
small_delay	681	1			T81	1		T89	1		T87	1
zero	619	1			T82	1		T88	1		T516	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T80	1		T420	1		T519	1
small_delay	981	1			T81	1		T89	1		T87	1
zero	619	1			T82	1		T88	1		T516	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T80	1		T420	1		T519	1
small_delay	981	1			T81	1		T89	1		T87	1
zero	619	1			T82	1		T88	1		T516	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T80	1		T420	1		T519	1
small_delay	681	1			T81	1		T89	1		T87	1
zero	619	1			T82	1		T88	1		T516	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T80	1		T420	1		T519	1
small_delay	981	1			T81	1		T89	1		T87	1
zero	619	1			T82	1		T88	1		T516	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T80	1		T420	1		T519	1
small_delay	681	1			T81	1		T89	1		T87	1
zero	619	1			T82	1		T88	1		T516	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T80	1		T420	1		T519	1
small_delay	681	1			T81	1		T89	1		T87	1
zero	619	1			T82	1		T88	1		T516	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T80	1		T420	1		T519	1
small_delay	981	1			T81	1		T89	1		T87	1
zero	619	1			T82	1		T88	1		T516	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T80	1		T420	1		T519	1
small_delay	681	1			T81	1		T89	1		T87	1
zero	619	1			T82	1		T88	1		T516	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T80	1		T420	1		T519	1
small_delay	981	1			T81	1		T89	1		T87	1
zero	619	1			T82	1		T88	1		T516	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T80	1		T420	1		T519	1
small_delay	981	1			T81	1		T89	1		T87	1
zero	619	1			T82	1		T88	1		T516	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T80	1		T420	1		T519	1
small_delay	681	1			T81	1		T89	1		T87	1
zero	619	1			T82	1		T88	1		T516	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T80	1		T420	1		T519	1
small_delay	681	1			T81	1		T89	1		T87	1
zero	619	1			T82	1		T88	1		T516	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T80	1		T420	1		T519	1
small_delay	981	1			T81	1		T89	1		T87	1
zero	619	1			T82	1		T88	1		T516	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T80	1		T420	1		T519	1
small_delay	681	1			T81	1		T89	1		T87	1
zero	619	1			T82	1		T88	1		T516	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T80	1		T420	1		T519	1
small_delay	981	1			T81	1		T89	1		T87	1
zero	619	1			T82	1		T88	1		T516	1