Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	50	0	50	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	50	0	50	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	50	0	50	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	478	1			T88	3		T515	4		T517	1
all_values[1]	470	1			T88	1		T520	2		T511	3
all_values[2]	468	1			T88	3		T520	1		T516	1
all_values[3]	459	1			T81	1		T511	1		T515	3
all_values[4]	507	1			T81	1		T88	3		T511	3
all_values[5]	463	1			T81	1		T88	2		T511	3
all_values[6]	432	1			T88	4		T511	2		T515	3
all_values[7]	471	1			T81	1		T88	1		T511	1
all_values[8]	471	1			T88	2		T511	2		T515	6
all_values[9]	429	1			T88	4		T511	3		T515	3
all_values[10]	406	1			T81	1		T88	2		T511	1
all_values[11]	427	1			T88	1		T511	2		T515	1
all_values[12]	453	1			T81	1		T88	1		T511	1
all_values[13]	453	1			T88	1		T520	1		T516	2
all_values[14]	426	1			T88	1		T516	1		T511	3
all_values[15]	463	1			T81	2		T88	3		T515	2
all_values[16]	467	1			T88	1		T511	1		T515	3
all_values[17]	486	1			T81	2		T88	3		T511	2
all_values[18]	468	1			T88	1		T520	1		T511	5
all_values[19]	462	1			T88	2		T516	1		T511	1
all_values[20]	455	1			T81	1		T88	2		T511	3
all_values[21]	486	1			T81	1		T88	1		T520	1
all_values[22]	455	1			T88	4		T516	2		T511	2
all_values[23]	451	1			T81	2		T88	4		T520	2
all_values[24]	505	1			T81	1		T88	1		T511	4
all_values[25]	472	1			T81	2		T88	1		T511	5
all_values[26]	440	1			T81	1		T88	4		T511	2
all_values[27]	437	1			T88	1		T511	1		T515	3
all_values[28]	447	1			T88	1		T511	1		T515	4
all_values[29]	442	1			T511	1		T515	3		T517	1
all_values[30]	472	1			T81	1		T88	3		T511	1
all_values[31]	439	1			T88	2		T511	1		T515	2
all_values[32]	455	1			T81	2		T88	1		T516	1
all_values[33]	428	1			T88	1		T511	3		T515	2
all_values[34]	457	1			T81	1		T88	1		T520	1
all_values[35]	443	1			T81	1		T88	2		T516	1
all_values[36]	492	1			T88	1		T511	3		T515	5
all_values[37]	464	1			T81	2		T520	1		T511	5
all_values[38]	426	1			T511	3		T515	2		T517	3
all_values[39]	457	1			T88	3		T511	1		T515	4
all_values[40]	479	1			T88	1		T511	2		T515	5
all_values[41]	474	1			T88	4		T516	1		T511	1
all_values[42]	426	1			T515	3		T517	1		T518	4
all_values[43]	441	1			T81	1		T88	1		T511	3
all_values[44]	449	1			T81	1		T511	2		T515	2
all_values[45]	451	1			T81	1		T88	1		T511	2
all_values[46]	485	1			T88	2		T511	2		T515	1
all_values[47]	433	1			T81	1		T88	2		T516	1
all_values[48]	501	1			T88	6		T511	2		T515	3
all_values[49]	475	1			T81	1		T88	2		T511	5