Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	3443	1			T81	5		T88	10		T511	6
all_values[1]	3444	1			T81	9		T88	15		T511	8
all_values[2]	3438	1			T81	5		T88	13		T511	9
all_values[3]	3437	1			T81	5		T88	16		T511	9
all_values[4]	3342	1			T81	4		T88	12		T511	4
all_values[5]	3413	1			T81	8		T88	10		T511	10
all_values[6]	3453	1			T81	1		T88	13		T511	3
all_values[7]	3352	1			T81	2		T88	9		T511	7
all_values[8]	3348	1			T81	5		T88	10		T511	11
all_values[9]	3457	1			T81	5		T87	1		T88	11
all_values[10]	3396	1			T81	7		T88	17		T511	11
all_values[11]	3487	1			T81	3		T87	1		T88	12
all_values[12]	3518	1			T81	2		T88	16		T511	10
all_values[13]	3483	1			T81	3		T87	1		T88	11
all_values[14]	3478	1			T81	6		T87	1		T88	12
all_values[15]	3389	1			T81	4		T88	9		T511	7
all_values[16]	3516	1			T81	6		T87	2		T88	6
all_values[17]	3423	1			T81	9		T88	13		T511	8
all_values[18]	3438	1			T81	5		T87	1		T88	10
all_values[19]	3538	1			T81	5		T88	14		T511	16
all_values[20]	3453	1			T81	3		T87	1		T88	10
all_values[21]	3429	1			T81	4		T88	13		T511	8
all_values[22]	3462	1			T88	9		T511	10		T515	6
all_values[23]	3443	1			T81	3		T87	1		T88	9
all_values[24]	3354	1			T81	4		T87	2		T88	13
all_values[25]	3455	1			T81	7		T88	19		T511	8
all_values[26]	3451	1			T81	3		T88	14		T511	7
all_values[27]	3472	1			T81	4		T88	5		T511	8
all_values[28]	3423	1			T81	7		T87	1		T88	10
all_values[29]	3413	1			T81	5		T87	1		T88	20
all_values[30]	3450	1			T81	6		T88	14		T511	10
all_values[31]	3404	1			T81	3		T88	9		T511	10
all_values[32]	3392	1			T81	3		T88	14		T511	10
all_values[33]	3376	1			T81	3		T88	10		T511	7
all_values[34]	3376	1			T81	6		T88	6		T511	12
all_values[35]	3355	1			T81	4		T88	7		T511	5
all_values[36]	3337	1			T81	4		T88	12		T511	12
all_values[37]	3421	1			T81	5		T87	1		T88	14
all_values[38]	3435	1			T81	4		T87	2		T88	9
all_values[39]	3532	1			T81	5		T88	8		T511	11
all_values[40]	3327	1			T81	4		T88	10		T511	6
all_values[41]	3374	1			T81	6		T87	1		T88	11
all_values[42]	3470	1			T81	3		T88	8		T511	14
all_values[43]	3539	1			T81	2		T88	16		T511	3
all_values[44]	3411	1			T81	2		T87	2		T88	10
all_values[45]	3407	1			T81	3		T87	1		T88	11
all_values[46]	3471	1			T81	5		T88	12		T511	3
all_values[47]	3403	1			T81	3		T88	12		T511	5
all_values[48]	3450	1			T81	2		T88	11		T511	4
all_values[49]	3548	1			T81	4		T87	1		T88	9
all_values[50]	3513	1			T81	4		T88	10		T511	9
all_values[51]	3338	1			T81	3		T88	6		T511	11
all_values[52]	3441	1			T81	9		T87	1		T88	19
all_values[53]	3367	1			T81	6		T88	7		T511	9
all_values[54]	3458	1			T81	5		T88	15		T511	6
all_values[55]	3429	1			T81	4		T87	1		T88	6
all_values[56]	3402	1			T81	6		T88	4		T511	9
all_values[57]	3430	1			T81	3		T88	17		T511	8
all_values[58]	3441	1			T81	4		T87	1		T88	10
all_values[59]	3460	1			T81	7		T88	14		T511	7
all_values[60]	3517	1			T81	5		T88	16		T511	10
all_values[61]	3406	1			T81	5		T87	1		T88	12
all_values[62]	3418	1			T81	2		T88	14		T511	7
all_values[63]	3450	1			T81	9		T88	11		T511	14