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LINE 18002
EXPRESSION (addr_hit[199] & reg_we & ((!reg_error)))
------1------ ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T2,T5,T6 |
| 1 | 0 | 1 | Covered | T2,T6,T95 |
| 1 | 1 | 0 | Covered | T521,T370,T524 |
| 1 | 1 | 1 | Covered | T2,T6,T95 |
LINE 18005
EXPRESSION (addr_hit[200] & reg_we & ((!reg_error)))
------1------ ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T2,T6,T95 |
| 1 | 0 | 1 | Covered | T5,T421,T147 |
| 1 | 1 | 0 | Covered | T521,T370,T530 |
| 1 | 1 | 1 | Covered | T5,T229,T230 |
LINE 18008
EXPRESSION (addr_hit[201] & reg_we & ((!reg_error)))
------1------ ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T2,T5,T6 |
| 1 | 0 | 1 | Covered | T421,T147,T148 |
| 1 | 1 | 0 | Covered | T521,T370,T522 |
| 1 | 1 | 1 | Covered | T66,T67,T68 |