Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.flash_ctrl__prim_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	155266	1			T77	221		T82	11		T84	6
values[2]	4371	1			T561	6		T830	11		T593	2
values[3]	2065	1			T830	3		T841	1		T517	25
values[4]	1382	1			T517	38		T643	5		T665	26
values[5]	1192	1			T517	54		T643	8		T665	46
values[6]	972	1			T517	64		T643	14		T665	53
values[7]	829	1			T517	81		T643	4		T665	69
values[8]	716	1			T517	84		T643	16		T665	44
values[9]	700	1			T517	55		T643	22		T665	44
values[10]	584	1			T517	16		T643	34		T665	29
values[11]	447	1			T517	19		T643	25		T665	32
values[12]	377	1			T517	12		T643	17		T665	17
values[13]	317	1			T517	2		T643	11		T665	10
values[14]	312	1			T643	18		T665	3		T518	6
values[15]	338	1			T643	12		T518	10		T842	1
values[16]	332	1			T643	8		T518	9		T842	1
values[17]	320	1			T643	8		T518	5		T842	1
values[18]	280	1			T643	1		T518	2		T842	1
values[19]	278	1			T518	1		T842	1		T843	1
values[20]	238	1			T518	2		T842	1		T843	1
values[21]	254	1			T518	5		T842	1		T843	1
values[22]	221	1			T518	10		T842	1		T843	1
values[23]	210	1			T518	23		T842	1		T843	1
values[24]	242	1			T518	34		T842	1		T843	1
values[25]	231	1			T518	17		T842	1		T843	1
values[26]	254	1			T518	7		T842	1		T843	1
values[27]	209	1			T518	4		T842	1		T843	1
values[28]	175	1			T518	4		T842	1		T843	1
values[29]	189	1			T518	15		T842	1		T843	1
values[30]	191	1			T518	10		T842	1		T843	1
values[31]	193	1			T518	15		T842	1		T843	1
values[32]	208	1			T518	29		T842	1		T843	1
values[33]	173	1			T518	41		T842	1		T843	1
values[34]	171	1			T518	46		T842	1		T843	1
values[35]	164	1			T518	17		T842	1		T843	1
values[36]	129	1			T518	2		T842	1		T843	1
values[37]	112	1			T842	1		T843	1		T650	1
values[38]	96	1			T842	1		T843	1		T650	1
values[39]	71	1			T842	1		T843	1		T650	1
values[40]	118	1			T842	1		T843	1		T650	1
values[41]	115	1			T842	1		T843	1		T650	1
values[42]	113	1			T842	1		T843	1		T650	1
values[43]	101	1			T842	1		T843	1		T650	1
values[44]	81	1			T842	1		T843	1		T650	1
values[45]	82	1			T842	1		T843	1		T650	1
values[46]	83	1			T842	1		T843	1		T650	1
values[47]	82	1			T842	1		T843	1		T650	1
values[48]	74	1			T842	1		T843	1		T650	1
values[49]	71	1			T842	1		T843	1		T650	1
values[50]	95	1			T842	1		T843	1		T650	1
values[51]	104	1			T842	1		T843	1		T650	1
values[52]	119	1			T842	1		T843	1		T650	1
values[53]	94	1			T842	1		T843	1		T650	1
values[54]	75	1			T842	1		T843	1		T650	1
values[55]	73	1			T842	1		T843	1		T650	2
values[56]	81	1			T842	1		T843	1		T650	1
values[57]	72	1			T842	1		T843	1		T650	1
values[58]	47	1			T842	1		T843	1		T650	1
values[59]	43	1			T842	1		T843	1		T650	1
values[60]	51	1			T842	1		T843	1		T650	1
values[61]	49	1			T842	1		T843	1		T650	1
values[62]	45	1			T842	1		T843	1		T650	1
values[63]	53	1			T842	1		T843	1		T650	1
values[64]	43	1			T842	1		T843	1		T650	2
values[65]	57	1			T842	1		T843	1		T650	1
values[66]	65	1			T842	1		T843	1		T650	1
values[67]	52	1			T842	1		T843	2		T650	1
values[68]	56	1			T842	1		T843	1		T650	1
values[69]	62	1			T842	1		T843	1		T650	1
values[70]	53	1			T842	1		T843	1		T650	1
values[71]	48	1			T842	1		T843	1		T650	1
values[72]	62	1			T842	1		T843	1		T650	1
values[73]	52	1			T842	1		T843	1		T650	1
values[74]	51	1			T842	1		T843	1		T650	1
values[75]	61	1			T842	1		T843	1		T650	1
values[76]	61	1			T842	1		T843	1		T650	1
values[77]	54	1			T842	1		T843	1		T650	1
values[78]	65	1			T842	1		T843	1		T650	1
values[79]	54	1			T842	1		T843	1		T650	1
values[80]	51	1			T842	1		T843	1		T650	1
values[81]	62	1			T842	1		T843	1		T650	1
values[82]	51	1			T842	1		T843	1		T650	1
values[83]	58	1			T842	1		T843	1		T650	1
values[84]	49	1			T842	1		T843	1		T650	1
values[85]	44	1			T842	1		T843	1		T650	1
values[86]	48	1			T842	1		T843	1		T650	1
values[87]	65	1			T842	1		T843	1		T650	1
values[88]	62	1			T842	1		T843	1		T650	1
values[89]	60	1			T842	1		T843	1		T650	4
values[90]	65	1			T842	1		T843	1		T650	12
values[91]	55	1			T842	1		T843	1		T650	2
values[92]	75	1			T842	1		T843	1		T650	2
values[93]	77	1			T842	1		T843	1		T650	3
values[94]	76	1			T842	1		T843	1		T650	4
values[95]	64	1			T842	1		T843	1		T650	5
values[96]	71	1			T842	1		T843	1		T650	1
values[97]	73	1			T842	1		T843	1		T650	1
values[98]	87	1			T842	1		T843	7		T650	1
values[99]	72	1			T842	1		T843	2		T650	1
values[100]	61	1			T842	1		T843	1		T650	2
values[101]	75	1			T842	2		T843	2		T650	4
values[102]	81	1			T842	1		T843	4		T650	3
values[103]	78	1			T842	1		T843	7		T650	1
values[104]	71	1			T842	1		T843	1		T650	1
values[105]	68	1			T842	3		T843	1		T650	3
values[106]	90	1			T842	2		T843	2		T650	3
values[107]	85	1			T842	7		T843	2		T650	1
values[108]	86	1			T842	5		T843	2		T650	3
values[109]	101	1			T842	6		T843	2		T650	1
values[110]	83	1			T842	2		T843	5		T650	1
values[111]	83	1			T842	1		T843	4		T650	1
values[112]	75	1			T842	1		T843	2		T650	1
values[113]	72	1			T842	2		T843	1		T650	1
values[114]	76	1			T842	4		T843	1		T650	1
values[115]	88	1			T842	1		T843	2		T650	1
values[116]	98	1			T842	5		T843	1		T650	1
values[117]	91	1			T842	3		T843	3		T650	2
values[118]	85	1			T842	2		T843	2		T650	1
values[119]	90	1			T842	1		T843	3		T650	1
values[120]	82	1			T842	1		T843	1		T650	3
values[121]	87	1			T842	1		T843	1		T650	1
values[122]	99	1			T842	1		T843	1		T650	2
values[123]	121	1			T842	1		T843	2		T650	4
values[124]	175	1			T842	3		T843	1		T650	4
values[125]	345	1			T842	1		T843	2		T650	1
values[126]	709	1			T842	14		T843	11		T650	19
values[127]	2415	1			T842	105		T843	94		T650	139
values[128]	4185	1			T842	255		T843	201		T650	234