Total Coverage Summary 

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.09	95.46	93.86	95.44		94.60	97.53	99.61

Total tests in report: 2935

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Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
40.64	40.64	45.70	45.70	44.88	44.88	33.27	33.27			58.76	58.76	59.09	59.09	2.11	2.11	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.3479084001
51.70	11.06	57.99	12.29	58.13	13.25	38.07	4.79			68.69	9.93	84.27	25.17	3.03	0.92	/workspace/coverage/cover_reg_top/19.chip_same_csr_outstanding.707397891
58.13	6.43	71.38	13.39	67.20	9.07	41.70	3.64			81.19	12.50	84.27	0.00	3.03	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_0.3586267302
63.51	5.38	71.38	0.00	70.17	2.97	42.05	0.34			81.48	0.28	84.27	0.00	31.70	28.67	/workspace/coverage/cover_reg_top/63.xbar_access_same_device_slow_rsp.2175210043
66.94	3.44	71.38	0.00	70.17	0.00	42.05	0.00			81.48	0.00	84.27	0.00	52.32	20.62	/workspace/coverage/cover_reg_top/53.xbar_access_same_device_slow_rsp.1080734244
70.16	3.22	76.69	5.31	74.22	4.04	45.66	3.61			83.28	1.80	88.81	4.55	52.32	0.00	/workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.210577794
72.84	2.67	76.69	0.00	74.22	0.00	45.66	0.00			83.28	0.00	88.81	0.00	68.37	16.05	/workspace/coverage/cover_reg_top/71.xbar_access_same_device_slow_rsp.234914223
75.46	2.63	81.71	5.01	75.67	1.46	48.32	2.66			83.50	0.22	88.81	0.00	74.79	6.42	/workspace/coverage/cover_reg_top/67.xbar_stress_all.2444336659
77.87	2.41	85.05	3.35	77.39	1.72	55.58	7.26			84.58	1.09	89.86	1.05	74.79	0.00	/workspace/coverage/default/1.chip_sw_power_virus.920903027
79.69	1.82	85.05	0.00	77.39	0.00	66.48	10.91			84.58	0.00	89.86	0.00	74.79	0.00	/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.3443806527
81.48	1.79	87.26	2.21	81.13	3.75	67.24	0.76			88.42	3.84	90.03	0.17	74.79	0.00	/workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.1303466581
83.11	1.63	87.26	0.00	81.28	0.14	67.24	0.00			88.45	0.02	90.03	0.00	84.41	9.62	/workspace/coverage/cover_reg_top/31.xbar_access_same_device_slow_rsp.2796982861
84.60	1.49	87.37	0.11	81.36	0.08	75.48	8.24			88.62	0.17	90.38	0.35	84.41	0.00	/workspace/coverage/default/2.chip_sw_lc_walkthrough_prodend.2684673292
85.66	1.05	88.66	1.29	82.42	1.06	76.53	1.05			89.78	1.16	92.13	1.75	84.43	0.02	/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.2620075579
86.50	0.84	89.42	0.76	82.59	0.17	76.55	0.01			90.02	0.24	95.98	3.85	84.43	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.3402733181
87.31	0.81	90.00	0.58	82.86	0.28	80.00	3.45			90.14	0.12	96.33	0.35	84.50	0.07	/workspace/coverage/default/50.chip_sw_all_escalation_resets.2857229793
87.99	0.68	90.00	0.00	82.86	0.00	80.00	0.00			90.14	0.00	96.33	0.00	88.59	4.09	/workspace/coverage/cover_reg_top/8.xbar_access_same_device_slow_rsp.3338165857
88.67	0.68	90.46	0.45	85.32	2.46	80.17	0.17			90.72	0.58	96.33	0.00	89.01	0.42	/workspace/coverage/cover_reg_top/5.chip_csr_mem_rw_with_rand_reset.1190652912
89.30	0.64	91.69	1.23	86.37	1.05	80.48	0.31			91.94	1.22	96.33	0.00	89.01	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_20.101501220
89.91	0.61	91.69	0.01	86.48	0.11	81.04	0.56			91.97	0.03	96.33	0.00	91.95	2.94	/workspace/coverage/cover_reg_top/82.xbar_stress_all_with_reset_error.2869413981
90.43	0.52	92.35	0.66	86.77	0.29	82.89	1.84			92.28	0.32	96.33	0.00	91.95	0.00	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.1839984396
90.93	0.50	92.35	0.00	86.77	0.00	85.89	3.00			92.28	0.00	96.33	0.00	91.95	0.00	/workspace/coverage/default/2.chip_sw_keymgr_sideload_aes.2916857462
91.38	0.45	92.35	0.00	86.77	0.00	85.89	0.00			92.28	0.00	96.33	0.00	94.68	2.73	/workspace/coverage/cover_reg_top/70.xbar_access_same_device_slow_rsp.2114507391
91.72	0.34	92.35	0.00	86.77	0.00	87.91	2.02			92.28	0.00	96.33	0.00	94.68	0.00	/workspace/coverage/default/2.chip_sw_flash_init.1968980155
92.05	0.33	92.86	0.51	87.21	0.44	88.47	0.57			92.75	0.46	96.33	0.00	94.68	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_10.3021835665
92.34	0.29	92.87	0.01	88.91	1.70	88.47	0.00			92.75	0.00	96.33	0.00	94.71	0.04	/workspace/coverage/cover_reg_top/2.chip_tl_errors.1215986847
92.60	0.26	93.45	0.58	89.31	0.41	88.75	0.28			93.05	0.31	96.33	0.00	94.71	0.00	/workspace/coverage/default/2.chip_sw_gpio.1889302964
92.86	0.26	93.45	0.00	89.35	0.03	88.75	0.00			93.05	0.00	96.33	0.00	96.24	1.53	/workspace/coverage/cover_reg_top/42.xbar_access_same_device.146134904
93.05	0.19	93.62	0.17	89.36	0.02	89.66	0.90			93.07	0.02	96.33	0.00	96.28	0.04	/workspace/coverage/default/1.chip_jtag_csr_rw.2152176491
93.23	0.18	93.62	0.00	89.39	0.03	90.70	1.05			93.07	0.00	96.33	0.00	96.28	0.00	/workspace/coverage/default/1.chip_sw_entropy_src_csrng.2265927495
93.39	0.16	93.62	0.00	89.39	0.00	91.67	0.96			93.07	0.00	96.33	0.00	96.28	0.00	/workspace/coverage/default/1.chip_sw_lc_walkthrough_dev.743180332
93.54	0.15	93.82	0.21	89.71	0.32	92.02	0.35			93.07	0.00	96.33	0.00	96.28	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3492165550
93.68	0.14	93.84	0.02	90.08	0.37	92.03	0.01			93.49	0.42	96.33	0.00	96.28	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.2123558002
93.79	0.12	93.89	0.05	90.14	0.06	92.24	0.21			93.49	0.00	96.33	0.00	96.66	0.39	/workspace/coverage/default/0.chip_sw_alert_test.1900915217
93.90	0.11	93.89	0.00	90.14	0.00	92.24	0.00			93.49	0.00	96.33	0.00	97.33	0.67	/workspace/coverage/cover_reg_top/60.xbar_smoke_large_delays.782771365
94.01	0.10	93.89	0.00	90.76	0.61	92.24	0.00			93.49	0.00	96.33	0.00	97.33	0.00	/workspace/coverage/cover_reg_top/19.chip_tl_errors.2912372213
94.10	0.09	94.06	0.17	90.89	0.13	92.35	0.11			93.62	0.13	96.33	0.00	97.33	0.00	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.2419853137
94.18	0.09	94.08	0.01	90.95	0.06	92.60	0.25			93.65	0.02	96.50	0.17	97.33	0.00	/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.3606653996
94.27	0.09	94.08	0.01	91.19	0.24	92.60	0.01			93.92	0.28	96.50	0.00	97.33	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.3869773043
94.36	0.08	94.08	0.00	91.19	0.00	93.11	0.51			93.92	0.00	96.50	0.00	97.33	0.00	/workspace/coverage/default/1.chip_sw_flash_rma_unlocked.157770217
94.44	0.08	94.08	0.00	91.24	0.05	93.11	0.00			93.92	0.00	96.50	0.00	97.77	0.43	/workspace/coverage/cover_reg_top/74.xbar_stress_all.2026639130
94.51	0.07	94.20	0.12	91.24	0.00	93.42	0.32			93.92	0.00	96.50	0.00	97.77	0.00	/workspace/coverage/cover_reg_top/85.xbar_access_same_device.3252414729
94.58	0.07	94.23	0.02	91.27	0.03	93.58	0.16			93.94	0.02	96.68	0.17	97.77	0.00	/workspace/coverage/default/3.chip_sw_data_integrity_escalation.71512892
94.63	0.06	94.30	0.07	91.42	0.16	93.58	0.00			94.06	0.12	96.68	0.00	97.77	0.00	/workspace/coverage/default/0.chip_sw_spi_device_pinmux_sleep_retention.674936821
94.69	0.05	94.31	0.02	91.71	0.29	93.59	0.01			94.06	0.00	96.68	0.00	97.77	0.00	/workspace/coverage/cover_reg_top/4.chip_same_csr_outstanding.1755841693
94.74	0.05	94.35	0.04	91.78	0.07	93.73	0.14			94.11	0.05	96.68	0.00	97.77	0.00	/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.883656162
94.78	0.05	94.38	0.03	91.83	0.05	93.73	0.01			94.13	0.02	96.85	0.17	97.78	0.01	/workspace/coverage/default/88.chip_sw_all_escalation_resets.3997580795
94.83	0.04	94.38	0.00	91.93	0.10	93.73	0.00			94.17	0.03	96.85	0.00	97.91	0.13	/workspace/coverage/cover_reg_top/31.xbar_stress_all_with_rand_reset.188747557
94.87	0.04	94.38	0.00	91.93	0.00	93.98	0.25			94.17	0.00	96.85	0.00	97.91	0.00	/workspace/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.2593967938
94.91	0.04	94.38	0.00	92.17	0.25	93.98	0.00			94.17	0.00	96.85	0.00	97.91	0.00	/workspace/coverage/cover_reg_top/11.chip_tl_errors.1864346936
94.95	0.04	94.39	0.01	92.19	0.01	93.98	0.00			94.19	0.02	97.03	0.17	97.92	0.01	/workspace/coverage/default/1.chip_sw_all_escalation_resets.2060511703
94.99	0.04	94.40	0.01	92.21	0.02	93.99	0.01			94.20	0.01	97.20	0.17	97.93	0.01	/workspace/coverage/default/86.chip_sw_all_escalation_resets.4243920124
95.02	0.04	94.40	0.01	92.22	0.01	94.00	0.01			94.21	0.01	97.38	0.17	97.94	0.01	/workspace/coverage/default/20.chip_sw_all_escalation_resets.663714871
95.06	0.04	94.40	0.01	92.23	0.01	94.01	0.01			94.22	0.01	97.55	0.17	97.96	0.01	/workspace/coverage/default/47.chip_sw_all_escalation_resets.2302711844
95.09	0.03	94.40	0.00	92.23	0.00	94.20	0.19			94.22	0.00	97.55	0.00	97.96	0.00	/workspace/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.67559417
95.12	0.03	94.47	0.07	92.23	0.00	94.31	0.11			94.22	0.01	97.55	0.00	97.96	0.00	/workspace/coverage/default/0.chip_tap_straps_rma.54095477
95.15	0.03	94.47	0.00	92.32	0.10	94.31	0.00			94.31	0.09	97.55	0.00	97.96	0.00	/workspace/coverage/default/2.chip_sw_sleep_pin_retention.964876469
95.19	0.03	94.47	0.00	92.51	0.18	94.31	0.00			94.31	0.00	97.55	0.00	97.96	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_0.641920635
95.22	0.03	94.47	0.00	92.53	0.02	94.31	0.00			94.31	0.00	97.55	0.00	98.11	0.15	/workspace/coverage/cover_reg_top/77.xbar_stress_all.2456931153
95.24	0.03	94.48	0.01	92.54	0.01	94.45	0.14			94.32	0.01	97.55	0.00	98.11	0.00	/workspace/coverage/cover_reg_top/1.chip_csr_hw_reset.2912216585
95.27	0.03	94.48	0.00	92.54	0.00	94.61	0.16			94.32	0.00	97.55	0.00	98.11	0.00	/workspace/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.720405775
95.29	0.03	94.56	0.07	92.57	0.03	94.62	0.01			94.37	0.05	97.55	0.00	98.11	0.00	/workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.1043009570
95.32	0.02	94.56	0.00	92.63	0.07	94.62	0.00			94.37	0.00	97.55	0.00	98.19	0.08	/workspace/coverage/cover_reg_top/73.xbar_access_same_device.1956490630
95.34	0.02	94.62	0.07	92.68	0.05	94.62	0.00			94.40	0.03	97.55	0.00	98.19	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_wake.1221370899
95.37	0.02	94.69	0.07	92.73	0.05	94.62	0.01			94.42	0.02	97.55	0.00	98.19	0.00	/workspace/coverage/default/2.chip_sw_sleep_pin_wake.3116394568
95.39	0.02	94.75	0.07	92.78	0.05	94.63	0.01			94.43	0.02	97.55	0.00	98.19	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_wake.3734272177
95.41	0.02	94.77	0.01	92.81	0.03	94.71	0.08			94.43	0.00	97.55	0.00	98.19	0.00	/workspace/coverage/default/2.chip_sw_uart_tx_rx_bootstrap.449700493
95.43	0.02	94.77	0.00	92.83	0.02	94.71	0.00			94.43	0.00	97.55	0.00	98.30	0.11	/workspace/coverage/cover_reg_top/85.xbar_stress_all_with_rand_reset.3412161804
95.45	0.02	94.79	0.02	92.88	0.05	94.72	0.01			94.47	0.04	97.55	0.00	98.30	0.00	/workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.3127782077
95.47	0.02	94.79	0.00	92.88	0.00	94.84	0.12			94.47	0.00	97.55	0.00	98.30	0.00	/workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.462596027
95.49	0.02	94.79	0.00	92.99	0.11	94.84	0.00			94.47	0.00	97.55	0.00	98.30	0.00	/workspace/coverage/cover_reg_top/9.chip_tl_errors.2637379684
95.51	0.02	94.79	0.00	92.99	0.00	94.94	0.10			94.47	0.00	97.55	0.00	98.30	0.00	/workspace/coverage/default/2.chip_sw_flash_rma_unlocked.2595058024
95.52	0.02	94.79	0.00	92.99	0.01	94.94	0.00			94.47	0.00	97.55	0.00	98.39	0.09	/workspace/coverage/cover_reg_top/84.xbar_stress_all_with_rand_reset.726548065
95.54	0.02	94.79	0.00	93.09	0.10	94.94	0.00			94.47	0.00	97.55	0.00	98.39	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_20.392502563
95.55	0.02	94.79	0.00	93.09	0.00	94.94	0.00			94.47	0.00	97.55	0.00	98.48	0.09	/workspace/coverage/cover_reg_top/75.xbar_stress_all_with_reset_error.3734902907
95.57	0.01	94.79	0.00	93.14	0.06	94.94	0.00			94.51	0.03	97.55	0.00	98.48	0.00	/workspace/coverage/cover_reg_top/88.xbar_access_same_device_slow_rsp.2936025652
95.58	0.01	94.79	0.00	93.20	0.06	94.94	0.00			94.51	0.00	97.55	0.00	98.51	0.02	/workspace/coverage/cover_reg_top/5.xbar_stress_all_with_rand_reset.3165822853
95.59	0.01	94.79	0.00	93.25	0.05	94.94	0.00			94.52	0.02	97.55	0.00	98.51	0.00	/workspace/coverage/cover_reg_top/15.xbar_stress_all.1930964876
95.60	0.01	94.79	0.00	93.26	0.01	94.94	0.00			94.52	0.00	97.55	0.00	98.57	0.06	/workspace/coverage/cover_reg_top/18.xbar_stress_all_with_reset_error.1228640500
95.62	0.01	94.79	0.01	93.28	0.02	94.98	0.04			94.52	0.00	97.55	0.00	98.57	0.00	/workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.3148726878
95.63	0.01	94.79	0.00	93.28	0.00	95.00	0.02			94.52	0.00	97.55	0.00	98.60	0.04	/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_power_glitch_reset.1985388191
95.63	0.01	94.81	0.02	93.29	0.01	95.01	0.01			94.54	0.02	97.55	0.00	98.60	0.00	/workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.3395723628
95.64	0.01	94.81	0.00	93.33	0.04	95.02	0.01			94.55	0.01	97.55	0.00	98.60	0.00	/workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.3904754670
95.65	0.01	94.81	0.00	93.38	0.05	95.02	0.00			94.55	0.00	97.55	0.00	98.60	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_10.4155299496
95.66	0.01	94.84	0.02	93.39	0.01	95.02	0.01			94.56	0.02	97.55	0.00	98.60	0.00	/workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.198646831
95.67	0.01	94.84	0.00	93.39	0.00	95.02	0.00			94.56	0.00	97.55	0.00	98.65	0.05	/workspace/coverage/cover_reg_top/24.xbar_stress_all_with_reset_error.487932506
95.68	0.01	94.84	0.00	93.39	0.01	95.05	0.03			94.56	0.00	97.55	0.00	98.66	0.01	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod.2876339614
95.68	0.01	94.85	0.01	93.40	0.01	95.08	0.03			94.56	0.00	97.55	0.00	98.66	0.00	/workspace/coverage/default/9.chip_sw_csrng_edn_concurrency.584950160
95.69	0.01	94.85	0.00	93.44	0.05	95.08	0.00			94.56	0.00	97.55	0.00	98.66	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_0.3724280764
95.70	0.01	94.85	0.00	93.47	0.03	95.09	0.01			94.56	0.00	97.55	0.00	98.66	0.00	/workspace/coverage/cover_reg_top/1.chip_tl_errors.3835973357
95.71	0.01	94.85	0.01	93.48	0.01	95.10	0.01			94.58	0.02	97.55	0.00	98.66	0.00	/workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.3680465992
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95.93	0.01	94.88	0.00	93.75	0.00	95.38	0.00			94.58	0.00	97.55	0.00	99.45	0.01	/workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.3003197443
95.93	0.01	94.88	0.00	93.75	0.00	95.38	0.00			94.58	0.00	97.55	0.00	99.46	0.01	/workspace/coverage/default/58.chip_sw_all_escalation_resets.1048754436
95.93	0.01	94.88	0.00	93.75	0.00	95.38	0.00			94.58	0.00	97.55	0.00	99.47	0.01	/workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.4272111816
95.94	0.01	94.88	0.00	93.75	0.00	95.38	0.00			94.58	0.00	97.55	0.00	99.48	0.01	/workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.4159615451
95.94	0.01	94.88	0.00	93.75	0.00	95.38	0.00			94.58	0.00	97.55	0.00	99.49	0.01	/workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.1944304706
95.94	0.01	94.88	0.00	93.75	0.00	95.38	0.00			94.58	0.00	97.55	0.00	99.51	0.01	/workspace/coverage/default/63.chip_sw_all_escalation_resets.925164181
95.94	0.01	94.88	0.00	93.75	0.00	95.38	0.00			94.58	0.00	97.55	0.00	99.52	0.01	/workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.1364825097
95.94	0.01	94.88	0.00	93.75	0.00	95.38	0.00			94.58	0.00	97.55	0.00	99.53	0.01	/workspace/coverage/default/65.chip_sw_all_escalation_resets.2875687228
95.95	0.01	94.88	0.00	93.75	0.00	95.38	0.00			94.58	0.00	97.55	0.00	99.54	0.01	/workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.3586826208
95.95	0.01	94.88	0.00	93.75	0.00	95.38	0.00			94.58	0.00	97.55	0.00	99.55	0.01	/workspace/coverage/default/67.chip_sw_all_escalation_resets.302307295
95.95	0.01	94.88	0.00	93.75	0.00	95.38	0.00			94.58	0.00	97.55	0.00	99.57	0.01	/workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.1249037813
95.95	0.01	94.88	0.00	93.75	0.00	95.38	0.00			94.58	0.00	97.55	0.00	99.58	0.01	/workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.2010406198
95.95	0.01	94.88	0.00	93.75	0.00	95.38	0.00			94.58	0.00	97.55	0.00	99.59	0.01	/workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.571691882
95.96	0.01	94.88	0.00	93.75	0.00	95.38	0.00			94.58	0.00	97.55	0.00	99.60	0.01	/workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.2705468248
95.96	0.01	94.88	0.00	93.75	0.00	95.38	0.00			94.58	0.00	97.55	0.00	99.61	0.01	/workspace/coverage/default/97.chip_sw_all_escalation_resets.1046451451
95.96	0.01	94.88	0.00	93.76	0.01	95.38	0.00			94.58	0.00	97.55	0.00	99.61	0.00	/workspace/coverage/cover_reg_top/1.chip_same_csr_outstanding.3602761406
95.96	0.01	94.88	0.00	93.77	0.01	95.38	0.00			94.58	0.00	97.55	0.00	99.61	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.1696522153
95.96	0.01	94.88	0.00	93.78	0.01	95.38	0.00			94.58	0.00	97.55	0.00	99.61	0.00	/workspace/coverage/default/2.chip_sw_pwrmgr_lowpower_cancel.1584156223
95.97	0.01	94.88	0.01	93.78	0.00	95.39	0.01			94.58	0.00	97.55	0.00	99.61	0.00	/workspace/coverage/default/0.chip_tap_straps_testunlock0.2703696357
95.97	0.01	94.89	0.01	93.78	0.00	95.40	0.01			94.58	0.00	97.55	0.00	99.61	0.00	/workspace/coverage/default/52.chip_sw_all_escalation_resets.938891582
95.97	0.01	94.89	0.00	93.78	0.00	95.40	0.01			94.58	0.00	97.55	0.00	99.61	0.00	/workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.1446045949
95.97	0.01	94.89	0.00	93.78	0.00	95.41	0.01			94.58	0.00	97.55	0.00	99.61	0.00	/workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.2459298516
95.97	0.01	94.89	0.00	93.78	0.00	95.41	0.00			94.59	0.01	97.55	0.00	99.61	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.3804112699
95.97	0.01	94.89	0.00	93.78	0.00	95.41	0.00			94.60	0.01	97.55	0.00	99.61	0.00	/workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.58864293
95.97	0.01	94.89	0.00	93.78	0.00	95.41	0.00			94.60	0.01	97.55	0.00	99.61	0.00	/workspace/coverage/default/0.chip_tap_straps_dev.4233956898
95.98	0.01	94.89	0.00	93.78	0.01	95.41	0.00			94.60	0.00	97.55	0.00	99.61	0.00	/workspace/coverage/cover_reg_top/16.xbar_access_same_device_slow_rsp.1302410202
95.98	0.01	94.89	0.00	93.79	0.01	95.41	0.00			94.60	0.00	97.55	0.00	99.61	0.00	/workspace/coverage/cover_reg_top/17.xbar_stress_all_with_rand_reset.2157239900
95.98	0.01	94.89	0.00	93.80	0.01	95.41	0.00			94.60	0.00	97.55	0.00	99.61	0.00	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.416448358
95.98	0.01	94.89	0.00	93.81	0.01	95.41	0.00			94.60	0.00	97.55	0.00	99.61	0.00	/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx2.714265855
95.98	0.01	94.89	0.00	93.81	0.00	95.42	0.01			94.60	0.00	97.55	0.00	99.61	0.00	/workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3320424940
95.98	0.01	94.89	0.00	93.81	0.00	95.43	0.01			94.60	0.00	97.55	0.00	99.61	0.00	/workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.3303829592
95.98	0.01	94.89	0.00	93.81	0.00	95.43	0.01			94.60	0.00	97.55	0.00	99.61	0.00	/workspace/coverage/default/0.chip_sw_lc_ctrl_program_error.1781987095
95.98	0.01	94.89	0.00	93.81	0.01	95.43	0.00			94.60	0.00	97.55	0.00	99.61	0.00	/workspace/coverage/cover_reg_top/0.chip_tl_errors.2924188657
95.98	0.01	94.89	0.00	93.81	0.01	95.43	0.00			94.60	0.00	97.55	0.00	99.61	0.00	/workspace/coverage/cover_reg_top/22.chip_tl_errors.2007012921
95.98	0.01	94.89	0.00	93.82	0.01	95.43	0.00			94.60	0.00	97.55	0.00	99.61	0.00	/workspace/coverage/cover_reg_top/23.xbar_stress_all_with_reset_error.3102540064
95.98	0.01	94.89	0.00	93.82	0.01	95.43	0.00			94.60	0.00	97.55	0.00	99.61	0.00	/workspace/coverage/cover_reg_top/41.xbar_stress_all_with_reset_error.970368259
95.98	0.01	94.89	0.00	93.82	0.01	95.43	0.00			94.60	0.00	97.55	0.00	99.61	0.00	/workspace/coverage/cover_reg_top/51.xbar_stress_all_with_reset_error.119324720
95.99	0.01	94.89	0.00	93.83	0.01	95.43	0.00			94.60	0.00	97.55	0.00	99.61	0.00	/workspace/coverage/cover_reg_top/71.xbar_stress_all_with_reset_error.1555452070
95.99	0.01	94.89	0.00	93.83	0.01	95.43	0.00			94.60	0.00	97.55	0.00	99.61	0.00	/workspace/coverage/cover_reg_top/8.xbar_stress_all_with_error.884120457
95.99	0.01	94.89	0.00	93.83	0.01	95.43	0.00			94.60	0.00	97.55	0.00	99.61	0.00	/workspace/coverage/cover_reg_top/82.xbar_stress_all_with_error.196604423
95.99	0.01	94.89	0.00	93.84	0.01	95.43	0.00			94.60	0.00	97.55	0.00	99.61	0.00	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops.3304493242
95.99	0.01	94.89	0.00	93.84	0.01	95.43	0.00			94.60	0.00	97.55	0.00	99.61	0.00	/workspace/coverage/default/0.chip_sw_hmac_enc.1293372623
95.99	0.01	94.89	0.00	93.84	0.01	95.43	0.00			94.60	0.00	97.55	0.00	99.61	0.00	/workspace/coverage/default/0.chip_sw_pattgen_ios.330717555
95.99	0.01	94.89	0.00	93.85	0.01	95.43	0.00			94.60	0.00	97.55	0.00	99.61	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.3027353257
95.99	0.01	94.89	0.00	93.85	0.01	95.43	0.00			94.60	0.00	97.55	0.00	99.61	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.730730984
95.99	0.01	94.89	0.00	93.86	0.01	95.43	0.00			94.60	0.00	97.55	0.00	99.61	0.00	/workspace/coverage/default/2.chip_sw_rstmgr_alert_info.3377127880
95.99	0.01	94.89	0.00	93.86	0.00	95.43	0.01			94.60	0.00	97.55	0.00	99.61	0.00	/workspace/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.1222592144
95.99	0.01	94.89	0.00	93.86	0.00	95.43	0.01			94.60	0.00	97.55	0.00	99.61	0.00	/workspace/coverage/default/0.chip_sw_aon_timer_irq.1874849686
95.99	0.01	94.89	0.00	93.86	0.00	95.44	0.01			94.60	0.00	97.55	0.00	99.61	0.00	/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.3925174810
95.99	0.01	94.89	0.00	93.86	0.00	95.44	0.01			94.60	0.00	97.55	0.00	99.61	0.00	/workspace/coverage/default/0.chip_sw_edn_boot_mode.786999133
95.99	0.01	94.89	0.00	93.86	0.00	95.44	0.01			94.60	0.00	97.55	0.00	99.61	0.00	/workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.2443598046
95.99	0.01	94.89	0.00	93.86	0.00	95.44	0.01			94.60	0.00	97.55	0.00	99.61	0.00	/workspace/coverage/default/2.chip_sw_rv_core_ibex_lockstep_glitch.3541704252

---

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.chip_csr_aliasing.3723542410
/workspace/coverage/cover_reg_top/0.chip_csr_bit_bash.2803148929
/workspace/coverage/cover_reg_top/0.chip_csr_hw_reset.779767766
/workspace/coverage/cover_reg_top/0.chip_csr_mem_rw_with_rand_reset.3558456786
/workspace/coverage/cover_reg_top/0.chip_csr_rw.2354748208
/workspace/coverage/cover_reg_top/0.chip_prim_tl_access.811151027
/workspace/coverage/cover_reg_top/0.chip_same_csr_outstanding.3641917274
/workspace/coverage/cover_reg_top/0.xbar_access_same_device.2263162968
/workspace/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.996756936
/workspace/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.1886114927
/workspace/coverage/cover_reg_top/0.xbar_error_random.2215971000
/workspace/coverage/cover_reg_top/0.xbar_random.2746251320
/workspace/coverage/cover_reg_top/0.xbar_random_large_delays.1374380537
/workspace/coverage/cover_reg_top/0.xbar_random_slow_rsp.2171688759
/workspace/coverage/cover_reg_top/0.xbar_random_zero_delays.2211545083
/workspace/coverage/cover_reg_top/0.xbar_same_source.1899322790
/workspace/coverage/cover_reg_top/0.xbar_smoke.3109354366
/workspace/coverage/cover_reg_top/0.xbar_smoke_large_delays.1582877391
/workspace/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.1692491509
/workspace/coverage/cover_reg_top/0.xbar_smoke_zero_delays.1353124229
/workspace/coverage/cover_reg_top/0.xbar_stress_all.3238831136
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_error.1653229150
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.2856534955
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.3180507891
/workspace/coverage/cover_reg_top/0.xbar_unmapped_addr.1491447673
/workspace/coverage/cover_reg_top/1.chip_csr_aliasing.63044220
/workspace/coverage/cover_reg_top/1.chip_csr_bit_bash.470478431
/workspace/coverage/cover_reg_top/1.chip_csr_mem_rw_with_rand_reset.3951591717
/workspace/coverage/cover_reg_top/1.chip_csr_rw.1527345844
/workspace/coverage/cover_reg_top/1.chip_prim_tl_access.3700505821
/workspace/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.2450672628
/workspace/coverage/cover_reg_top/1.xbar_access_same_device.1286190700
/workspace/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.1645915429
/workspace/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.354061934
/workspace/coverage/cover_reg_top/1.xbar_error_random.3377686511
/workspace/coverage/cover_reg_top/1.xbar_random.975346909
/workspace/coverage/cover_reg_top/1.xbar_random_large_delays.2653755132
/workspace/coverage/cover_reg_top/1.xbar_random_slow_rsp.1351492984
/workspace/coverage/cover_reg_top/1.xbar_random_zero_delays.800147914
/workspace/coverage/cover_reg_top/1.xbar_same_source.3746028235
/workspace/coverage/cover_reg_top/1.xbar_smoke.4005538418
/workspace/coverage/cover_reg_top/1.xbar_smoke_large_delays.2020528687
/workspace/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.2606102217
/workspace/coverage/cover_reg_top/1.xbar_smoke_zero_delays.1313483323
/workspace/coverage/cover_reg_top/1.xbar_stress_all.1602929175
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_error.4204572978
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.3670220105
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.413214736
/workspace/coverage/cover_reg_top/1.xbar_unmapped_addr.393268290
/workspace/coverage/cover_reg_top/10.chip_csr_mem_rw_with_rand_reset.3645468003
/workspace/coverage/cover_reg_top/10.chip_csr_rw.3706901405
/workspace/coverage/cover_reg_top/10.chip_same_csr_outstanding.1876730930
/workspace/coverage/cover_reg_top/10.xbar_access_same_device.2777632670
/workspace/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.3185232595
/workspace/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.1366483704
/workspace/coverage/cover_reg_top/10.xbar_error_random.360727200
/workspace/coverage/cover_reg_top/10.xbar_random.2970881541
/workspace/coverage/cover_reg_top/10.xbar_random_large_delays.884517554
/workspace/coverage/cover_reg_top/10.xbar_random_slow_rsp.704133301
/workspace/coverage/cover_reg_top/10.xbar_random_zero_delays.290079193
/workspace/coverage/cover_reg_top/10.xbar_same_source.3255779792
/workspace/coverage/cover_reg_top/10.xbar_smoke.349813647
/workspace/coverage/cover_reg_top/10.xbar_smoke_large_delays.1923084038
/workspace/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.1713147544
/workspace/coverage/cover_reg_top/10.xbar_smoke_zero_delays.1400941614
/workspace/coverage/cover_reg_top/10.xbar_stress_all.3482865097
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_error.285675455
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.1303713586
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.2984198049
/workspace/coverage/cover_reg_top/10.xbar_unmapped_addr.868408775
/workspace/coverage/cover_reg_top/11.chip_csr_mem_rw_with_rand_reset.110143087
/workspace/coverage/cover_reg_top/11.chip_csr_rw.831911739
/workspace/coverage/cover_reg_top/11.chip_same_csr_outstanding.1884852282
/workspace/coverage/cover_reg_top/11.xbar_access_same_device.2556133073
/workspace/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.2809717200
/workspace/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.3747140848
/workspace/coverage/cover_reg_top/11.xbar_error_random.3652808387
/workspace/coverage/cover_reg_top/11.xbar_random.3524996248
/workspace/coverage/cover_reg_top/11.xbar_random_large_delays.1392190304
/workspace/coverage/cover_reg_top/11.xbar_random_slow_rsp.2102953956
/workspace/coverage/cover_reg_top/11.xbar_random_zero_delays.3052380395
/workspace/coverage/cover_reg_top/11.xbar_same_source.4238700879
/workspace/coverage/cover_reg_top/11.xbar_smoke.2864470149
/workspace/coverage/cover_reg_top/11.xbar_smoke_large_delays.1035130575
/workspace/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.1551935961
/workspace/coverage/cover_reg_top/11.xbar_smoke_zero_delays.2369059151
/workspace/coverage/cover_reg_top/11.xbar_stress_all.680237671
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_error.3185398103
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.3509590157
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.2150972063
/workspace/coverage/cover_reg_top/11.xbar_unmapped_addr.1095966783
/workspace/coverage/cover_reg_top/12.chip_csr_mem_rw_with_rand_reset.3783625412
/workspace/coverage/cover_reg_top/12.chip_csr_rw.1880537179
/workspace/coverage/cover_reg_top/12.chip_same_csr_outstanding.2451606687
/workspace/coverage/cover_reg_top/12.chip_tl_errors.1445935622
/workspace/coverage/cover_reg_top/12.xbar_access_same_device.2709173677
/workspace/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.1763850738
/workspace/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.4178274935
/workspace/coverage/cover_reg_top/12.xbar_error_random.2420344066
/workspace/coverage/cover_reg_top/12.xbar_random.1884402456
/workspace/coverage/cover_reg_top/12.xbar_random_large_delays.1569774705
/workspace/coverage/cover_reg_top/12.xbar_random_slow_rsp.2488766440
/workspace/coverage/cover_reg_top/12.xbar_random_zero_delays.588595451
/workspace/coverage/cover_reg_top/12.xbar_same_source.3897400343
/workspace/coverage/cover_reg_top/12.xbar_smoke.3162185758
/workspace/coverage/cover_reg_top/12.xbar_smoke_large_delays.999207021
/workspace/coverage/cover_reg_top/12.xbar_smoke_slow_rsp.3772503889
/workspace/coverage/cover_reg_top/12.xbar_smoke_zero_delays.691110983
/workspace/coverage/cover_reg_top/12.xbar_stress_all.1702693972
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_error.33007366
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_rand_reset.1602702806
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_reset_error.1000919873
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/workspace/coverage/default/51.chip_sw_all_escalation_resets.3125742600
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/workspace/coverage/default/70.chip_sw_all_escalation_resets.3577018454
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/workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.1505506959
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/workspace/coverage/default/9.chip_sw_all_escalation_resets.2873609929
/workspace/coverage/default/9.chip_sw_lc_ctrl_transition.1342521077
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/workspace/coverage/default/90.chip_sw_all_escalation_resets.3990816979
/workspace/coverage/default/91.chip_sw_all_escalation_resets.1055834507
/workspace/coverage/default/92.chip_sw_all_escalation_resets.1256017343
/workspace/coverage/default/93.chip_sw_all_escalation_resets.3564436666
/workspace/coverage/default/94.chip_sw_all_escalation_resets.3471962444
/workspace/coverage/default/95.chip_sw_all_escalation_resets.58396329
/workspace/coverage/default/96.chip_sw_all_escalation_resets.2217711352
/workspace/coverage/default/98.chip_sw_all_escalation_resets.1570229294
/workspace/coverage/default/99.chip_sw_all_escalation_resets.2367951363
/workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.2552194750
/workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.3652435712
/workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.3141855507
/workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.756915525
/workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.2595356250
/workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.1914711186
/workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.1960929871
/workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.2678158112

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Total test records in report: 2935

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TEST NO	TEST LOCATION	TEST NAME	STATUS	STARTED	FINISHED	SIMULATION TIME
T1	/workspace/coverage/default/0.chip_sw_example_flash.465147464			Aug 09 08:19:58 PM PDT 24	Aug 09 08:22:51 PM PDT 24	2651209156 ps
T2	/workspace/coverage/default/1.chip_sw_rv_timer_irq.557949853			Aug 09 08:26:51 PM PDT 24	Aug 09 08:31:30 PM PDT 24	3006468232 ps
T3	/workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.2224150877			Aug 09 08:52:10 PM PDT 24	Aug 09 08:58:27 PM PDT 24	3904449454 ps
T4	/workspace/coverage/default/50.chip_sw_all_escalation_resets.2857229793			Aug 09 08:52:51 PM PDT 24	Aug 09 09:03:13 PM PDT 24	5009944760 ps
T90	/workspace/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.550219476			Aug 09 08:42:23 PM PDT 24	Aug 09 08:46:53 PM PDT 24	2609090858 ps
T91	/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.883656162			Aug 09 08:46:16 PM PDT 24	Aug 09 08:56:01 PM PDT 24	3897724672 ps
T59	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.3479084001			Aug 09 08:40:06 PM PDT 24	Aug 09 09:02:09 PM PDT 24	11928900520 ps
T30	/workspace/coverage/default/1.chip_sw_clkmgr_off_hmac_trans.463137443			Aug 09 08:31:58 PM PDT 24	Aug 09 08:41:47 PM PDT 24	5127740720 ps
T5	/workspace/coverage/default/2.chip_sw_flash_init.1968980155			Aug 09 08:37:38 PM PDT 24	Aug 09 09:19:34 PM PDT 24	19406966250 ps
T63	/workspace/coverage/default/5.chip_sw_all_escalation_resets.1314782399			Aug 09 08:47:04 PM PDT 24	Aug 09 08:58:09 PM PDT 24	6575474358 ps
T203	/workspace/coverage/default/1.chip_sw_csrng_smoketest.2246515504			Aug 09 08:36:43 PM PDT 24	Aug 09 08:40:24 PM PDT 24	3137144432 ps
T204	/workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.3681213801			Aug 09 08:54:26 PM PDT 24	Aug 09 09:02:53 PM PDT 24	4326715740 ps
T130	/workspace/coverage/default/1.chip_sw_entropy_src_csrng.2265927495			Aug 09 08:31:50 PM PDT 24	Aug 09 08:53:41 PM PDT 24	5566884576 ps
T85	/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.886159437			Aug 09 08:27:31 PM PDT 24	Aug 09 08:48:35 PM PDT 24	11630855576 ps
T184	/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_power_glitch_reset.1985388191			Aug 09 08:37:55 PM PDT 24	Aug 09 08:47:03 PM PDT 24	5469521086 ps
T221	/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.1221604210			Aug 09 08:26:39 PM PDT 24	Aug 09 08:42:48 PM PDT 24	4876713304 ps
T129	/workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.462596027			Aug 09 08:22:10 PM PDT 24	Aug 09 08:33:06 PM PDT 24	7190241506 ps
T14	/workspace/coverage/default/5.chip_sw_uart_rand_baudrate.945198309			Aug 09 08:46:41 PM PDT 24	Aug 09 08:57:11 PM PDT 24	3995256670 ps
T44	/workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_meas.1950620892			Aug 09 08:49:42 PM PDT 24	Aug 09 09:45:01 PM PDT 24	14499720768 ps
T149	/workspace/coverage/default/2.chip_sw_sensor_ctrl_status.412695433			Aug 09 08:47:38 PM PDT 24	Aug 09 08:53:19 PM PDT 24	2851619707 ps
T47	/workspace/coverage/default/0.chip_tap_straps_rma.54095477			Aug 09 08:21:01 PM PDT 24	Aug 09 08:29:43 PM PDT 24	4647485802 ps
T325	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_clkoff.148326864			Aug 09 08:42:52 PM PDT 24	Aug 09 09:01:44 PM PDT 24	5822812878 ps
T374	/workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.318778472			Aug 09 08:54:06 PM PDT 24	Aug 09 09:01:12 PM PDT 24	4077164400 ps
T132	/workspace/coverage/default/9.chip_sw_csrng_edn_concurrency.584950160			Aug 09 08:48:12 PM PDT 24	Aug 09 10:38:47 PM PDT 24	32614619096 ps
T200	/workspace/coverage/default/0.chip_sw_clkmgr_off_aes_trans.1920799123			Aug 09 08:21:28 PM PDT 24	Aug 09 08:30:18 PM PDT 24	5465049350 ps
T375	/workspace/coverage/default/0.chip_sw_hmac_smoketest.3813114862			Aug 09 08:25:25 PM PDT 24	Aug 09 08:30:17 PM PDT 24	3853563534 ps
T376	/workspace/coverage/default/2.chip_sw_aes_enc.3645989002			Aug 09 08:39:06 PM PDT 24	Aug 09 08:44:05 PM PDT 24	3258190104 ps
T64	/workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.4096238914			Aug 09 08:23:41 PM PDT 24	Aug 09 08:35:25 PM PDT 24	5718120728 ps
T377	/workspace/coverage/default/1.chip_sw_example_concurrency.546609077			Aug 09 08:27:34 PM PDT 24	Aug 09 08:32:29 PM PDT 24	3479633150 ps
T17	/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.3804112699			Aug 09 08:25:06 PM PDT 24	Aug 09 08:43:12 PM PDT 24	22422848396 ps
T107	/workspace/coverage/default/3.chip_sw_csrng_edn_concurrency.292340301			Aug 09 08:46:35 PM PDT 24	Aug 09 10:00:31 PM PDT 24	22286553500 ps
T86	/workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.3761249464			Aug 09 08:57:21 PM PDT 24	Aug 09 09:04:58 PM PDT 24	3641869310 ps
T94	/workspace/coverage/default/69.chip_sw_all_escalation_resets.3471118045			Aug 09 08:54:52 PM PDT 24	Aug 09 09:08:01 PM PDT 24	5223549760 ps
T95	/workspace/coverage/default/16.chip_sw_uart_rand_baudrate.1967244169			Aug 09 08:50:35 PM PDT 24	Aug 09 08:58:29 PM PDT 24	3162846832 ps
T96	/workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.4008133501			Aug 09 08:52:19 PM PDT 24	Aug 09 08:57:52 PM PDT 24	3837129148 ps
T97	/workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.83747589			Aug 09 08:51:38 PM PDT 24	Aug 09 08:59:00 PM PDT 24	3315456382 ps
T98	/workspace/coverage/default/3.chip_sw_data_integrity_escalation.71512892			Aug 09 08:44:31 PM PDT 24	Aug 09 09:02:07 PM PDT 24	5552874824 ps
T48	/workspace/coverage/default/0.chip_sw_rv_dm_access_after_wakeup.1417665017			Aug 09 08:23:49 PM PDT 24	Aug 09 08:35:28 PM PDT 24	6088779198 ps
T99	/workspace/coverage/default/2.chip_sw_entropy_src_csrng.3209339601			Aug 09 08:41:08 PM PDT 24	Aug 09 09:08:52 PM PDT 24	8295564998 ps
T100	/workspace/coverage/default/57.chip_sw_all_escalation_resets.1115485953			Aug 09 08:53:10 PM PDT 24	Aug 09 09:03:24 PM PDT 24	5628961056 ps
T101	/workspace/coverage/default/13.chip_sw_all_escalation_resets.747225791			Aug 09 08:48:30 PM PDT 24	Aug 09 08:58:14 PM PDT 24	5328440718 ps
T45	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.1839984396			Aug 09 08:29:09 PM PDT 24	Aug 09 10:15:42 PM PDT 24	24447022926 ps
T6	/workspace/coverage/default/2.chip_sw_lc_walkthrough_prodend.2684673292			Aug 09 08:37:18 PM PDT 24	Aug 09 08:54:51 PM PDT 24	9262470706 ps
T11	/workspace/coverage/default/0.chip_sw_spi_host_tx_rx.1433207634			Aug 09 08:24:20 PM PDT 24	Aug 09 08:28:58 PM PDT 24	2798941308 ps
T281	/workspace/coverage/default/0.chip_sw_entropy_src_smoketest.3856678817			Aug 09 08:26:08 PM PDT 24	Aug 09 08:35:56 PM PDT 24	3426726020 ps
T282	/workspace/coverage/default/77.chip_sw_all_escalation_resets.3730267262			Aug 09 08:54:27 PM PDT 24	Aug 09 09:03:08 PM PDT 24	4230609872 ps
T261	/workspace/coverage/default/1.chip_sw_aon_timer_smoketest.2747480894			Aug 09 08:35:11 PM PDT 24	Aug 09 08:41:26 PM PDT 24	3510127228 ps
T120	/workspace/coverage/default/0.chip_sw_aes_enc_jitter_en.2495848178			Aug 09 08:25:03 PM PDT 24	Aug 09 08:29:18 PM PDT 24	2975449148 ps
T46	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.3082995169			Aug 09 08:28:53 PM PDT 24	Aug 09 09:37:33 PM PDT 24	15254877590 ps
T707	/workspace/coverage/default/0.chip_sw_aes_idle.3256589685			Aug 09 08:22:51 PM PDT 24	Aug 09 08:28:53 PM PDT 24	3069076550 ps
T8	/workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.1303466581			Aug 09 08:35:57 PM PDT 24	Aug 09 08:41:55 PM PDT 24	3560171940 ps
T347	/workspace/coverage/default/2.chip_sw_pwrmgr_lowpower_cancel.1584156223			Aug 09 08:43:08 PM PDT 24	Aug 09 08:49:55 PM PDT 24	4109954104 ps
T266	/workspace/coverage/default/8.chip_sw_csrng_edn_concurrency.3091895592			Aug 09 08:48:57 PM PDT 24	Aug 09 09:40:51 PM PDT 24	14412745746 ps
T60	/workspace/coverage/default/1.chip_sw_lc_ctrl_program_error.1546031090			Aug 09 08:32:27 PM PDT 24	Aug 09 08:39:30 PM PDT 24	5013199456 ps
T7	/workspace/coverage/default/1.chip_jtag_csr_rw.2152176491			Aug 09 08:24:27 PM PDT 24	Aug 09 08:41:34 PM PDT 24	11038787240 ps
T678	/workspace/coverage/default/1.chip_sw_aes_masking_off.3911631428			Aug 09 08:27:22 PM PDT 24	Aug 09 08:32:58 PM PDT 24	3152407701 ps
T68	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.291980249			Aug 09 08:21:01 PM PDT 24	Aug 09 08:30:31 PM PDT 24	5007031134 ps
T187	/workspace/coverage/default/1.chip_sw_rv_core_ibex_icache_invalidate.1117323711			Aug 09 08:33:15 PM PDT 24	Aug 09 08:37:33 PM PDT 24	2613873240 ps
T887	/workspace/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.50799149			Aug 09 08:20:28 PM PDT 24	Aug 09 08:27:09 PM PDT 24	6477836552 ps
T250	/workspace/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.3479433300			Aug 09 08:30:55 PM PDT 24	Aug 09 08:41:21 PM PDT 24	4901633982 ps
T62	/workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock.145293251			Aug 09 08:38:01 PM PDT 24	Aug 09 08:39:57 PM PDT 24	2534544902 ps
T251	/workspace/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.1617088841			Aug 09 08:20:26 PM PDT 24	Aug 09 08:27:40 PM PDT 24	5183024616 ps
T888	/workspace/coverage/default/0.chip_sw_csrng_smoketest.666129507			Aug 09 08:24:00 PM PDT 24	Aug 09 08:28:12 PM PDT 24	3079634380 ps
T198	/workspace/coverage/default/2.chip_tap_straps_dev.837823780			Aug 09 08:40:52 PM PDT 24	Aug 09 08:45:04 PM PDT 24	4518672991 ps
T12	/workspace/coverage/default/1.chip_sw_power_virus.920903027			Aug 09 08:38:08 PM PDT 24	Aug 09 09:01:26 PM PDT 24	5940250968 ps
T889	/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1084774447			Aug 09 08:39:17 PM PDT 24	Aug 09 08:47:08 PM PDT 24	5709747450 ps
T262	/workspace/coverage/default/0.chip_plic_all_irqs_0.3586267302			Aug 09 08:23:03 PM PDT 24	Aug 09 08:42:28 PM PDT 24	5934551100 ps
T890	/workspace/coverage/default/1.chip_sw_aon_timer_wdog_lc_escalate.2936856612			Aug 09 08:26:43 PM PDT 24	Aug 09 08:36:16 PM PDT 24	6541308816 ps
T160	/workspace/coverage/default/1.chip_sw_sram_ctrl_execution_main.3958679995			Aug 09 08:30:41 PM PDT 24	Aug 09 08:39:11 PM PDT 24	5979773403 ps
T121	/workspace/coverage/default/1.chip_sw_flash_ctrl_clock_freqs.899463090			Aug 09 08:27:53 PM PDT 24	Aug 09 08:43:27 PM PDT 24	5592777422 ps
T307	/workspace/coverage/default/15.chip_sw_uart_rand_baudrate.1404246487			Aug 09 08:48:35 PM PDT 24	Aug 09 09:16:36 PM PDT 24	8159488644 ps
T122	/workspace/coverage/default/0.chip_sw_clkmgr_jitter.3864218059			Aug 09 08:22:57 PM PDT 24	Aug 09 08:26:30 PM PDT 24	2848696143 ps
T406	/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency.1209555227			Aug 09 08:22:09 PM PDT 24	Aug 09 10:11:55 PM PDT 24	27433772584 ps
T891	/workspace/coverage/default/1.chip_sw_csrng_kat_test.3215958229			Aug 09 08:28:38 PM PDT 24	Aug 09 08:32:39 PM PDT 24	2885439452 ps
T113	/workspace/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.4180653133			Aug 09 08:27:15 PM PDT 24	Aug 09 08:33:13 PM PDT 24	18078007374 ps
T170	/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2878017296			Aug 09 08:27:24 PM PDT 24	Aug 09 08:39:54 PM PDT 24	4402566242 ps
T263	/workspace/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.1824219693			Aug 09 08:26:43 PM PDT 24	Aug 09 08:43:27 PM PDT 24	5558820684 ps
T155	/workspace/coverage/default/0.chip_sw_power_idle_load.3075563835			Aug 09 08:23:20 PM PDT 24	Aug 09 08:34:22 PM PDT 24	4077772172 ps
T252	/workspace/coverage/default/86.chip_sw_all_escalation_resets.4243920124			Aug 09 08:55:12 PM PDT 24	Aug 09 09:06:20 PM PDT 24	5984363644 ps
T298	/workspace/coverage/default/45.chip_sw_all_escalation_resets.2695912272			Aug 09 08:52:45 PM PDT 24	Aug 09 09:04:06 PM PDT 24	6116116016 ps
T299	/workspace/coverage/default/2.chip_sw_flash_ctrl_ops.1694355610			Aug 09 08:39:33 PM PDT 24	Aug 09 08:49:36 PM PDT 24	3318953394 ps
T300	/workspace/coverage/default/8.chip_sw_all_escalation_resets.1107274705			Aug 09 08:48:24 PM PDT 24	Aug 09 09:02:50 PM PDT 24	5874721768 ps
T226	/workspace/coverage/default/15.chip_sw_all_escalation_resets.2483495459			Aug 09 08:49:32 PM PDT 24	Aug 09 08:59:57 PM PDT 24	5130643792 ps
T301	/workspace/coverage/default/53.chip_sw_all_escalation_resets.1984501864			Aug 09 08:52:59 PM PDT 24	Aug 09 09:05:44 PM PDT 24	6085646900 ps
T154	/workspace/coverage/default/11.chip_sw_uart_rand_baudrate.1197703268			Aug 09 08:48:08 PM PDT 24	Aug 09 08:57:17 PM PDT 24	4598843322 ps
T247	/workspace/coverage/default/88.chip_sw_all_escalation_resets.3997580795			Aug 09 08:56:42 PM PDT 24	Aug 09 09:08:12 PM PDT 24	4964844566 ps
T199	/workspace/coverage/default/1.chip_tap_straps_dev.1752590112			Aug 09 08:31:14 PM PDT 24	Aug 09 08:36:05 PM PDT 24	4016843725 ps
T270	/workspace/coverage/default/2.chip_sw_example_manufacturer.1042820248			Aug 09 08:37:55 PM PDT 24	Aug 09 08:41:38 PM PDT 24	2593492304 ps
T176	/workspace/coverage/default/1.rom_e2e_static_critical.580046750			Aug 09 08:41:11 PM PDT 24	Aug 09 09:44:26 PM PDT 24	17708938600 ps
T15	/workspace/coverage/default/2.chip_sw_sleep_pin_retention.964876469			Aug 09 08:36:33 PM PDT 24	Aug 09 08:41:33 PM PDT 24	3794690880 ps
T271	/workspace/coverage/default/0.chip_sw_aes_masking_off.3146088534			Aug 09 08:21:37 PM PDT 24	Aug 09 08:26:11 PM PDT 24	2781305149 ps
T65	/workspace/coverage/default/4.chip_tap_straps_rma.1364690547			Aug 09 08:47:02 PM PDT 24	Aug 09 08:49:08 PM PDT 24	2393012706 ps
T272	/workspace/coverage/default/1.chip_sw_alert_handler_lpg_clkoff.291870574			Aug 09 08:32:40 PM PDT 24	Aug 09 09:09:28 PM PDT 24	8802757434 ps
T273	/workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.4272111816			Aug 09 08:53:11 PM PDT 24	Aug 09 08:59:11 PM PDT 24	3904364326 ps
T274	/workspace/coverage/default/1.chip_sw_entropy_src_kat_test.2406472624			Aug 09 08:28:41 PM PDT 24	Aug 09 08:32:08 PM PDT 24	2707165808 ps
T134	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_wake_5_bug.1104414599			Aug 09 08:23:03 PM PDT 24	Aug 09 08:28:41 PM PDT 24	5235679300 ps
T411	/workspace/coverage/default/2.chip_sw_hmac_smoketest.2742649884			Aug 09 08:47:57 PM PDT 24	Aug 09 08:52:39 PM PDT 24	3516819722 ps
T309	/workspace/coverage/default/20.chip_sw_all_escalation_resets.663714871			Aug 09 08:49:56 PM PDT 24	Aug 09 08:59:46 PM PDT 24	5887361304 ps
T315	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops.3304493242			Aug 09 08:19:14 PM PDT 24	Aug 09 08:27:46 PM PDT 24	4063449560 ps
T316	/workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.3415199370			Aug 09 08:55:24 PM PDT 24	Aug 09 09:01:26 PM PDT 24	3972893020 ps
T135	/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3335375545			Aug 09 08:41:15 PM PDT 24	Aug 09 08:50:52 PM PDT 24	5913269360 ps
T317	/workspace/coverage/default/1.chip_sw_flash_ctrl_write_clear.1971299032			Aug 09 08:34:37 PM PDT 24	Aug 09 08:41:09 PM PDT 24	3094832364 ps
T318	/workspace/coverage/default/66.chip_sw_all_escalation_resets.1531954466			Aug 09 08:53:42 PM PDT 24	Aug 09 09:02:20 PM PDT 24	5391283694 ps
T319	/workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.4021479349			Aug 09 08:43:36 PM PDT 24	Aug 09 08:56:35 PM PDT 24	4570659645 ps
T320	/workspace/coverage/default/0.chip_sw_otp_ctrl_ecc_error_vendor_test.2015752184			Aug 09 08:19:57 PM PDT 24	Aug 09 08:24:44 PM PDT 24	2505409869 ps
T321	/workspace/coverage/default/1.chip_plic_all_irqs_0.641920635			Aug 09 08:30:24 PM PDT 24	Aug 09 08:50:07 PM PDT 24	5494590040 ps
T172	/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_dev.582232113			Aug 09 08:21:34 PM PDT 24	Aug 09 08:46:28 PM PDT 24	6730455120 ps
T61	/workspace/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.2593967938			Aug 09 08:21:38 PM PDT 24	Aug 09 08:24:02 PM PDT 24	3407064362 ps
T365	/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.2203650800			Aug 09 08:25:34 PM PDT 24	Aug 09 09:12:34 PM PDT 24	35587171271 ps
T713	/workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.2626270406			Aug 09 08:51:40 PM PDT 24	Aug 09 08:59:08 PM PDT 24	3669618190 ps
T223	/workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_meas.2417183164			Aug 09 08:31:45 PM PDT 24	Aug 09 09:34:27 PM PDT 24	15325827448 ps
T892	/workspace/coverage/default/0.chip_sw_example_manufacturer.2119787711			Aug 09 08:19:22 PM PDT 24	Aug 09 08:23:09 PM PDT 24	2657251456 ps
T372	/workspace/coverage/default/2.rom_e2e_asm_init_prod.373789407			Aug 09 08:48:28 PM PDT 24	Aug 09 09:59:58 PM PDT 24	16214239905 ps
T16	/workspace/coverage/default/1.chip_sw_gpio.2098704510			Aug 09 08:25:59 PM PDT 24	Aug 09 08:35:48 PM PDT 24	4671411156 ps
T118	/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.3443806527			Aug 09 08:33:10 PM PDT 24	Aug 09 08:50:36 PM PDT 24	7188820829 ps
T893	/workspace/coverage/default/2.chip_sw_flash_ctrl_access.1724234927			Aug 09 08:37:49 PM PDT 24	Aug 09 08:56:07 PM PDT 24	5424362750 ps
T732	/workspace/coverage/default/2.chip_sw_alert_handler_ping_timeout.2376095758			Aug 09 08:41:24 PM PDT 24	Aug 09 08:46:50 PM PDT 24	3778424912 ps
T308	/workspace/coverage/default/4.chip_sw_uart_rand_baudrate.3024265481			Aug 09 08:47:11 PM PDT 24	Aug 09 09:14:35 PM PDT 24	9340780124 ps
T894	/workspace/coverage/default/0.chip_sw_entropy_src_kat_test.1726132206			Aug 09 08:28:22 PM PDT 24	Aug 09 08:33:07 PM PDT 24	2437539136 ps
T125	/workspace/coverage/default/7.chip_sw_lc_ctrl_transition.3002600784			Aug 09 08:47:56 PM PDT 24	Aug 09 08:57:07 PM PDT 24	6657347585 ps
T161	/workspace/coverage/default/1.chip_plic_all_irqs_10.926635546			Aug 09 08:31:23 PM PDT 24	Aug 09 08:41:26 PM PDT 24	4257561118 ps
T89	/workspace/coverage/default/2.chip_sw_uart_tx_rx_bootstrap.449700493			Aug 09 08:35:54 PM PDT 24	Aug 10 12:14:32 AM PDT 24	79023938988 ps
T550	/workspace/coverage/default/2.chip_sw_otp_ctrl_smoketest.2254139333			Aug 09 08:44:50 PM PDT 24	Aug 09 08:49:54 PM PDT 24	3297772480 ps
T119	/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.765484853			Aug 09 08:35:18 PM PDT 24	Aug 09 09:38:08 PM PDT 24	24911110873 ps
T895	/workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.2246937630			Aug 09 08:45:19 PM PDT 24	Aug 09 08:52:59 PM PDT 24	7867186688 ps
T896	/workspace/coverage/default/2.chip_sw_flash_ctrl_mem_protection.3958039868			Aug 09 08:43:47 PM PDT 24	Aug 09 09:07:05 PM PDT 24	5983233358 ps
T692	/workspace/coverage/default/4.chip_tap_straps_prod.32452210			Aug 09 08:47:12 PM PDT 24	Aug 09 08:50:24 PM PDT 24	2321177074 ps
T227	/workspace/coverage/default/2.chip_sw_keymgr_key_derivation.2954166993			Aug 09 08:40:30 PM PDT 24	Aug 09 09:15:46 PM PDT 24	9592478540 ps
T451	/workspace/coverage/default/2.chip_sw_kmac_idle.2122207942			Aug 09 08:41:22 PM PDT 24	Aug 09 08:45:05 PM PDT 24	2781319276 ps
T165	/workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.106547650			Aug 09 08:49:14 PM PDT 24	Aug 09 08:54:36 PM PDT 24	3905184584 ps
T369	/workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.2799126563			Aug 09 08:56:47 PM PDT 24	Aug 09 09:02:22 PM PDT 24	3887123328 ps
T70	/workspace/coverage/default/2.chip_tap_straps_prod.2522940616			Aug 09 08:41:57 PM PDT 24	Aug 09 09:05:58 PM PDT 24	13523278971 ps
T359	/workspace/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.2735013818			Aug 09 08:21:36 PM PDT 24	Aug 09 08:32:27 PM PDT 24	5267456936 ps
T385	/workspace/coverage/default/0.chip_sw_kmac_app_rom.1157086112			Aug 09 08:22:32 PM PDT 24	Aug 09 08:27:07 PM PDT 24	2862825400 ps
T386	/workspace/coverage/default/2.chip_sw_csrng_edn_concurrency.3464909923			Aug 09 08:40:03 PM PDT 24	Aug 09 10:05:50 PM PDT 24	22490107148 ps
T164	/workspace/coverage/default/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.2693102861			Aug 09 08:24:39 PM PDT 24	Aug 09 11:58:15 PM PDT 24	254819351052 ps
T387	/workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.2256399385			Aug 09 08:23:46 PM PDT 24	Aug 09 08:27:58 PM PDT 24	2789760060 ps
T388	/workspace/coverage/default/44.chip_sw_all_escalation_resets.4196794407			Aug 09 08:52:39 PM PDT 24	Aug 09 09:04:59 PM PDT 24	5235273492 ps
T389	/workspace/coverage/default/2.chip_sw_aon_timer_smoketest.3813651599			Aug 09 08:47:35 PM PDT 24	Aug 09 08:51:35 PM PDT 24	2441525636 ps
T390	/workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.2448729272			Aug 09 08:48:41 PM PDT 24	Aug 09 08:56:39 PM PDT 24	4046111582 ps
T126	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.2051045250			Aug 09 08:32:14 PM PDT 24	Aug 09 08:41:39 PM PDT 24	5036697100 ps
T69	/workspace/coverage/default/2.chip_tap_straps_testunlock0.1551747146			Aug 09 08:42:15 PM PDT 24	Aug 09 08:46:17 PM PDT 24	3304941132 ps
T188	/workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.3402733181			Aug 09 08:21:37 PM PDT 24	Aug 09 08:26:43 PM PDT 24	3017315048 ps
T401	/workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.2458448313			Aug 09 08:50:44 PM PDT 24	Aug 09 08:57:14 PM PDT 24	3537190760 ps
T127	/workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.3148726878			Aug 09 08:22:32 PM PDT 24	Aug 09 08:56:06 PM PDT 24	8435330057 ps
T178	/workspace/coverage/default/14.chip_sw_lc_ctrl_transition.379805089			Aug 09 08:50:55 PM PDT 24	Aug 09 09:13:51 PM PDT 24	10505730036 ps
T402	/workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.3494287354			Aug 09 08:49:43 PM PDT 24	Aug 09 08:55:09 PM PDT 24	4504240000 ps
T175	/workspace/coverage/default/1.chip_sw_flash_rma_unlocked.157770217			Aug 09 08:24:11 PM PDT 24	Aug 09 09:46:45 PM PDT 24	43800812448 ps
T260	/workspace/coverage/default/0.chip_sw_rv_timer_irq.2900407774			Aug 09 08:21:10 PM PDT 24	Aug 09 08:27:35 PM PDT 24	2804518550 ps
T403	/workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1818528932			Aug 09 08:19:36 PM PDT 24	Aug 09 08:49:32 PM PDT 24	13851425039 ps
T404	/workspace/coverage/default/2.chip_sw_pwrmgr_main_power_glitch_reset.957941916			Aug 09 08:38:12 PM PDT 24	Aug 09 08:45:48 PM PDT 24	5252272252 ps
T405	/workspace/coverage/default/2.chip_sw_flash_ctrl_clock_freqs.1463824503			Aug 09 08:37:35 PM PDT 24	Aug 09 08:59:05 PM PDT 24	6420597064 ps
T114	/workspace/coverage/default/1.chip_sw_power_sleep_load.3060622069			Aug 09 08:34:08 PM PDT 24	Aug 09 08:45:26 PM PDT 24	9822196456 ps
T302	/workspace/coverage/default/0.chip_sw_rv_core_ibex_icache_invalidate.1834991829			Aug 09 08:23:13 PM PDT 24	Aug 09 08:28:16 PM PDT 24	3268207505 ps
T41	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod.2876339614			Aug 09 08:31:42 PM PDT 24	Aug 09 10:00:06 PM PDT 24	23766568892 ps
T897	/workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_no_meas.4238956066			Aug 09 08:41:12 PM PDT 24	Aug 09 09:44:28 PM PDT 24	15679198776 ps
T366	/workspace/coverage/default/2.chip_sw_flash_ctrl_idle_low_power.3726676501			Aug 09 08:38:17 PM PDT 24	Aug 09 08:45:18 PM PDT 24	3181640266 ps
T42	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.1844074122			Aug 09 08:29:53 PM PDT 24	Aug 09 09:50:38 PM PDT 24	18002882814 ps
T18	/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.2620075579			Aug 09 08:41:21 PM PDT 24	Aug 09 09:09:20 PM PDT 24	20974559024 ps
T898	/workspace/coverage/default/6.chip_sw_csrng_edn_concurrency.3941080814			Aug 09 08:48:42 PM PDT 24	Aug 09 09:55:36 PM PDT 24	17666187664 ps
T253	/workspace/coverage/default/73.chip_sw_all_escalation_resets.2305353124			Aug 09 08:55:15 PM PDT 24	Aug 09 09:06:50 PM PDT 24	5541136216 ps
T899	/workspace/coverage/default/2.chip_sw_uart_smoketest.1602908806			Aug 09 08:47:45 PM PDT 24	Aug 09 08:52:26 PM PDT 24	2729792120 ps
T900	/workspace/coverage/default/1.chip_sw_flash_ctrl_mem_protection.777888757			Aug 09 08:34:34 PM PDT 24	Aug 09 08:53:33 PM PDT 24	5364145480 ps
T373	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_dev.2791689984			Aug 09 08:28:20 PM PDT 24	Aug 09 09:33:54 PM PDT 24	16282425524 ps
T115	/workspace/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.3970062735			Aug 09 08:34:42 PM PDT 24	Aug 09 09:38:09 PM PDT 24	22497091919 ps
T394	/workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.1133713633			Aug 09 08:49:48 PM PDT 24	Aug 09 08:56:38 PM PDT 24	4530841258 ps
T733	/workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.2081085688			Aug 09 08:50:39 PM PDT 24	Aug 09 08:58:32 PM PDT 24	4051540376 ps
T901	/workspace/coverage/default/1.chip_sw_kmac_mode_kmac.228996231			Aug 09 08:28:47 PM PDT 24	Aug 09 08:34:23 PM PDT 24	2521994160 ps
T902	/workspace/coverage/default/1.rom_e2e_asm_init_rma.343472508			Aug 09 08:37:33 PM PDT 24	Aug 09 09:35:01 PM PDT 24	14822063712 ps
T102	/workspace/coverage/default/0.chip_sw_sleep_pin_wake.3734272177			Aug 09 08:19:34 PM PDT 24	Aug 09 08:26:36 PM PDT 24	5762543896 ps
T398	/workspace/coverage/default/0.chip_sw_clkmgr_off_peri.1229017894			Aug 09 08:26:27 PM PDT 24	Aug 09 08:47:16 PM PDT 24	10191118570 ps
T166	/workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.2459298516			Aug 09 08:37:39 PM PDT 24	Aug 09 08:43:48 PM PDT 24	3254393984 ps
T415	/workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.3755519808			Aug 09 08:22:03 PM PDT 24	Aug 09 08:34:21 PM PDT 24	7594480030 ps
T123	/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.2460272814			Aug 09 08:22:47 PM PDT 24	Aug 09 08:52:35 PM PDT 24	11200687320 ps
T416	/workspace/coverage/default/89.chip_sw_all_escalation_resets.2620809846			Aug 09 08:56:24 PM PDT 24	Aug 09 09:04:51 PM PDT 24	5192958800 ps
T417	/workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.1944304706			Aug 09 08:53:41 PM PDT 24	Aug 09 08:59:37 PM PDT 24	3722838196 ps
T418	/workspace/coverage/default/0.chip_sw_kmac_idle.3665154284			Aug 09 08:22:34 PM PDT 24	Aug 09 08:26:34 PM PDT 24	2797952580 ps
T419	/workspace/coverage/default/1.chip_sw_flash_ctrl_idle_low_power.2117567462			Aug 09 08:27:53 PM PDT 24	Aug 09 08:32:47 PM PDT 24	3004688478 ps
T420	/workspace/coverage/default/0.chip_sw_kmac_entropy.430665484			Aug 09 08:26:40 PM PDT 24	Aug 09 08:31:12 PM PDT 24	3136413272 ps
T310	/workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.3100266518			Aug 09 08:48:08 PM PDT 24	Aug 09 08:54:38 PM PDT 24	4053722726 ps
T128	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.2605620490			Aug 09 08:32:01 PM PDT 24	Aug 09 08:41:54 PM PDT 24	3347241762 ps
T364	/workspace/coverage/default/0.chip_sw_alert_handler_ping_timeout.945255578			Aug 09 08:21:39 PM PDT 24	Aug 09 08:28:18 PM PDT 24	3162040040 ps
T903	/workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en.675205319			Aug 09 08:46:16 PM PDT 24	Aug 09 08:51:59 PM PDT 24	3348395447 ps
T257	/workspace/coverage/default/1.chip_sw_plic_sw_irq.2958098542			Aug 09 08:30:30 PM PDT 24	Aug 09 08:33:28 PM PDT 24	2989668714 ps
T13	/workspace/coverage/default/2.chip_sw_power_virus.3900345245			Aug 09 08:48:24 PM PDT 24	Aug 09 09:13:46 PM PDT 24	5625513990 ps
T331	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.2102644399			Aug 09 08:20:02 PM PDT 24	Aug 09 08:32:06 PM PDT 24	4620593530 ps
T801	/workspace/coverage/default/18.chip_sw_all_escalation_resets.2809049403			Aug 09 08:49:19 PM PDT 24	Aug 09 09:01:02 PM PDT 24	5440726520 ps
T39	/workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.165238553			Aug 09 08:19:09 PM PDT 24	Aug 09 08:27:20 PM PDT 24	3838389470 ps
T904	/workspace/coverage/default/2.chip_sw_rstmgr_sw_req.426550950			Aug 09 08:37:03 PM PDT 24	Aug 09 08:45:57 PM PDT 24	3750742462 ps
T727	/workspace/coverage/default/94.chip_sw_all_escalation_resets.3471962444			Aug 09 08:54:41 PM PDT 24	Aug 09 09:05:16 PM PDT 24	5958492920 ps
T905	/workspace/coverage/default/0.chip_sival_flash_info_access.2265070066			Aug 09 08:21:22 PM PDT 24	Aug 09 08:26:33 PM PDT 24	3120044112 ps
T549	/workspace/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.4034024199			Aug 09 08:39:38 PM PDT 24	Aug 09 08:52:10 PM PDT 24	4714611918 ps
T728	/workspace/coverage/default/1.chip_sw_clkmgr_reset_frequency.3975331646			Aug 09 08:31:16 PM PDT 24	Aug 09 08:38:04 PM PDT 24	3425061060 ps
T906	/workspace/coverage/default/2.chip_sw_entropy_src_kat_test.2669872863			Aug 09 08:39:02 PM PDT 24	Aug 09 08:41:54 PM PDT 24	3216328600 ps
T19	/workspace/coverage/default/0.chip_sw_usbdev_stream.2077159024			Aug 09 08:21:53 PM PDT 24	Aug 09 09:32:05 PM PDT 24	19172796320 ps
T907	/workspace/coverage/default/3.chip_sw_uart_tx_rx.896441267			Aug 09 08:44:53 PM PDT 24	Aug 09 08:54:12 PM PDT 24	4197027832 ps
T908	/workspace/coverage/default/2.chip_sw_clkmgr_off_peri.3778195996			Aug 09 08:41:52 PM PDT 24	Aug 09 09:01:58 PM PDT 24	9511458200 ps
T784	/workspace/coverage/default/72.chip_sw_all_escalation_resets.2662034211			Aug 09 08:56:06 PM PDT 24	Aug 09 09:07:04 PM PDT 24	5465483000 ps
T729	/workspace/coverage/default/2.chip_sw_ast_clk_outputs.2133301479			Aug 09 08:41:36 PM PDT 24	Aug 09 08:56:41 PM PDT 24	8788120976 ps
T909	/workspace/coverage/default/0.chip_sw_rv_plic_smoketest.801004037			Aug 09 08:27:01 PM PDT 24	Aug 09 08:31:11 PM PDT 24	2639250968 ps
T169	/workspace/coverage/default/1.chip_sw_lc_walkthrough_dev.743180332			Aug 09 08:26:37 PM PDT 24	Aug 09 09:54:47 PM PDT 24	48889369240 ps
T910	/workspace/coverage/default/2.rom_e2e_smoke.741068787			Aug 09 08:50:41 PM PDT 24	Aug 09 09:41:55 PM PDT 24	14502121698 ps
T911	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.4117717317			Aug 09 08:21:37 PM PDT 24	Aug 09 08:31:27 PM PDT 24	4118017714 ps
T267	/workspace/coverage/default/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.3760525498			Aug 09 08:27:08 PM PDT 24	Aug 09 11:56:05 PM PDT 24	255938029528 ps
T912	/workspace/coverage/default/1.rom_e2e_asm_init_dev.1810940071			Aug 09 08:37:54 PM PDT 24	Aug 09 09:30:35 PM PDT 24	15369179695 ps
T239	/workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.3590863228			Aug 09 08:44:19 PM PDT 24	Aug 09 09:24:06 PM PDT 24	20556541651 ps
T913	/workspace/coverage/default/1.chip_sw_flash_scrambling_smoketest.1254823655			Aug 09 08:38:26 PM PDT 24	Aug 09 08:42:13 PM PDT 24	2950026188 ps
T914	/workspace/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.3395771468			Aug 09 08:26:20 PM PDT 24	Aug 09 08:32:08 PM PDT 24	6481628916 ps
T725	/workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.2058494147			Aug 09 08:49:48 PM PDT 24	Aug 09 08:55:29 PM PDT 24	3907924568 ps
T915	/workspace/coverage/default/1.chip_sw_alert_handler_ping_timeout.311809815			Aug 09 08:29:55 PM PDT 24	Aug 09 08:35:15 PM PDT 24	3907579624 ps
T229	/workspace/coverage/default/2.chip_sw_alert_handler_escalation.2204078922			Aug 09 08:39:58 PM PDT 24	Aug 09 08:50:23 PM PDT 24	5620710650 ps
T43	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_dev.3542657239			Aug 09 08:30:55 PM PDT 24	Aug 09 10:07:15 PM PDT 24	22561477901 ps
T58	/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_wake_ups.2098820288			Aug 09 08:43:25 PM PDT 24	Aug 09 09:04:43 PM PDT 24	21690229992 ps
T916	/workspace/coverage/default/0.chip_sw_clkmgr_reset_frequency.2010063270			Aug 09 08:22:24 PM PDT 24	Aug 09 08:30:39 PM PDT 24	3616580178 ps
T332	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.416448358			Aug 09 08:23:32 PM PDT 24	Aug 09 08:38:03 PM PDT 24	5453742410 ps
T734	/workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.3586826208			Aug 09 08:56:09 PM PDT 24	Aug 09 09:03:19 PM PDT 24	4573791094 ps
T215	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_inputs.697298521			Aug 09 08:27:44 PM PDT 24	Aug 09 08:32:33 PM PDT 24	3613782122 ps
T917	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.3931564998			Aug 09 08:22:11 PM PDT 24	Aug 09 08:32:27 PM PDT 24	4803604444 ps
T793	/workspace/coverage/default/68.chip_sw_all_escalation_resets.1593427098			Aug 09 08:53:05 PM PDT 24	Aug 09 09:01:12 PM PDT 24	5017601884 ps
T275	/workspace/coverage/default/0.rom_volatile_raw_unlock.4220745389			Aug 09 08:23:53 PM PDT 24	Aug 09 08:25:53 PM PDT 24	2432240913 ps
T124	/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.123710683			Aug 09 08:46:01 PM PDT 24	Aug 09 09:09:06 PM PDT 24	12448171625 ps
T396	/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.4177434270			Aug 09 08:29:11 PM PDT 24	Aug 09 08:34:40 PM PDT 24	4204321260 ps
T743	/workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.1791949946			Aug 09 08:46:12 PM PDT 24	Aug 09 08:52:06 PM PDT 24	3912371904 ps
T445	/workspace/coverage/default/0.chip_sw_sram_ctrl_smoketest.1912114604			Aug 09 08:28:08 PM PDT 24	Aug 09 08:32:01 PM PDT 24	2757149350 ps
T108	/workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.3680465992			Aug 09 08:22:59 PM PDT 24	Aug 09 08:31:51 PM PDT 24	4361365400 ps
T437	/workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.2252804455			Aug 09 08:52:30 PM PDT 24	Aug 09 08:59:31 PM PDT 24	3940919630 ps
T438	/workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.409782547			Aug 09 08:55:12 PM PDT 24	Aug 09 09:02:00 PM PDT 24	3621543792 ps
T439	/workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.3962232750			Aug 09 08:48:02 PM PDT 24	Aug 09 08:54:25 PM PDT 24	3847373280 ps
T20	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_outputs.3934368578			Aug 09 08:38:25 PM PDT 24	Aug 09 08:43:53 PM PDT 24	3896545640 ps
T326	/workspace/coverage/default/2.chip_plic_all_irqs_0.3724280764			Aug 09 08:40:36 PM PDT 24	Aug 09 08:58:33 PM PDT 24	6312139144 ps
T440	/workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.2334097652			Aug 09 08:52:24 PM PDT 24	Aug 09 08:58:44 PM PDT 24	3231945172 ps
T327	/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx3.2485481615			Aug 09 08:24:35 PM PDT 24	Aug 09 08:35:46 PM PDT 24	4336259456 ps
T441	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2633485838			Aug 09 08:27:54 PM PDT 24	Aug 09 08:37:57 PM PDT 24	6199701140 ps
T442	/workspace/coverage/default/0.rom_e2e_asm_init_dev.2994290810			Aug 09 08:26:41 PM PDT 24	Aug 09 09:24:20 PM PDT 24	15907714216 ps
T918	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.2589552193			Aug 09 08:42:51 PM PDT 24	Aug 09 08:54:05 PM PDT 24	4830615758 ps
T228	/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_prod.2949339181			Aug 09 08:25:51 PM PDT 24	Aug 09 08:41:58 PM PDT 24	7754656696 ps
T919	/workspace/coverage/default/1.chip_sw_otp_ctrl_smoketest.1428484011			Aug 09 08:36:10 PM PDT 24	Aug 09 08:40:34 PM PDT 24	2530313948 ps
T920	/workspace/coverage/default/0.rom_e2e_self_hash.4062497179			Aug 09 08:28:36 PM PDT 24	Aug 09 09:59:31 PM PDT 24	26408731810 ps
T245	/workspace/coverage/default/5.chip_sw_data_integrity_escalation.950606127			Aug 09 08:46:54 PM PDT 24	Aug 09 08:59:57 PM PDT 24	5131666900 ps
T150	/workspace/coverage/default/0.chip_sw_sensor_ctrl_status.673332530			Aug 09 08:23:42 PM PDT 24	Aug 09 08:27:34 PM PDT 24	2600436728 ps
T290	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.3993676535			Aug 09 08:28:13 PM PDT 24	Aug 09 10:03:05 PM PDT 24	18271702644 ps
T291	/workspace/coverage/default/2.chip_sw_hmac_oneshot.1512285157			Aug 09 08:42:22 PM PDT 24	Aug 09 08:49:46 PM PDT 24	3301683080 ps
T292	/workspace/coverage/default/1.chip_sw_rv_timer_smoketest.2887836434			Aug 09 08:38:44 PM PDT 24	Aug 09 08:43:43 PM PDT 24	2762383704 ps
T293	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.1516005861			Aug 09 08:31:01 PM PDT 24	Aug 09 10:01:37 PM PDT 24	24113197000 ps
T294	/workspace/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.1875052575			Aug 09 08:42:29 PM PDT 24	Aug 09 08:59:15 PM PDT 24	5564769932 ps
T131	/workspace/coverage/default/0.chip_sw_edn_auto_mode.2365706825			Aug 09 08:21:05 PM PDT 24	Aug 09 08:40:58 PM PDT 24	5249514624 ps
T173	/workspace/coverage/default/0.chip_sw_lc_ctrl_program_error.1781987095			Aug 09 08:24:10 PM PDT 24	Aug 09 08:31:02 PM PDT 24	4271254582 ps
T295	/workspace/coverage/default/3.chip_tap_straps_dev.3998832330			Aug 09 08:45:21 PM PDT 24	Aug 09 08:48:18 PM PDT 24	3059721877 ps
T189	/workspace/coverage/default/1.chip_sw_csrng_fuse_en_sw_app_read_test.158807050			Aug 09 08:28:06 PM PDT 24	Aug 09 08:34:20 PM PDT 24	4282918110 ps
T731	/workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.1820863074			Aug 09 08:53:44 PM PDT 24	Aug 09 09:00:45 PM PDT 24	3943439832 ps