Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.i2c1_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	138513	1			T77	230		T82	11		T84	5
values[2]	7868	1			T77	1		T83	3		T564	1
values[3]	2751	1			T83	6		T551	63		T832	1
values[4]	1731	1			T83	3		T551	22		T832	1
values[5]	1161	1			T551	14		T832	1		T716	5
values[6]	780	1			T551	9		T832	1		T716	13
values[7]	641	1			T551	16		T832	1		T716	9
values[8]	485	1			T551	7		T832	1		T716	5
values[9]	368	1			T832	1		T716	7		T502	1
values[10]	291	1			T832	1		T716	5		T502	1
values[11]	275	1			T832	1		T716	6		T502	1
values[12]	315	1			T832	1		T716	19		T502	1
values[13]	300	1			T832	1		T716	6		T502	1
values[14]	252	1			T832	1		T716	6		T502	1
values[15]	271	1			T832	1		T716	6		T502	1
values[16]	271	1			T832	1		T716	5		T502	1
values[17]	295	1			T832	1		T716	11		T502	1
values[18]	230	1			T832	1		T716	6		T502	1
values[19]	246	1			T832	1		T716	11		T502	1
values[20]	198	1			T832	1		T716	5		T502	1
values[21]	200	1			T832	1		T716	6		T502	1
values[22]	223	1			T832	1		T716	6		T502	1
values[23]	263	1			T832	1		T716	6		T502	1
values[24]	252	1			T832	1		T716	9		T502	1
values[25]	235	1			T832	1		T716	2		T502	1
values[26]	248	1			T832	1		T716	15		T502	1
values[27]	246	1			T832	1		T716	8		T502	1
values[28]	223	1			T832	1		T716	6		T502	1
values[29]	199	1			T832	1		T716	9		T502	1
values[30]	218	1			T832	1		T716	7		T502	1
values[31]	212	1			T832	1		T716	6		T502	1
values[32]	218	1			T832	1		T716	5		T502	1
values[33]	258	1			T832	1		T716	3		T502	1
values[34]	199	1			T832	1		T716	7		T502	1
values[35]	206	1			T832	1		T716	6		T502	1
values[36]	201	1			T832	1		T716	10		T502	1
values[37]	231	1			T832	1		T716	8		T502	1
values[38]	223	1			T832	1		T716	7		T502	1
values[39]	190	1			T832	1		T716	12		T502	1
values[40]	199	1			T832	1		T716	7		T502	1
values[41]	221	1			T832	1		T716	6		T502	1
values[42]	181	1			T832	1		T716	7		T502	1
values[43]	212	1			T832	1		T716	3		T502	1
values[44]	214	1			T832	1		T716	10		T502	1
values[45]	184	1			T832	1		T716	5		T502	1
values[46]	189	1			T832	1		T716	8		T502	1
values[47]	236	1			T832	1		T716	17		T502	1
values[48]	179	1			T832	1		T716	11		T502	1
values[49]	195	1			T832	1		T716	6		T502	1
values[50]	200	1			T832	1		T716	5		T502	1
values[51]	197	1			T832	1		T716	3		T502	1
values[52]	170	1			T832	1		T716	8		T502	1
values[53]	152	1			T832	1		T716	6		T502	1
values[54]	170	1			T832	1		T716	3		T502	1
values[55]	127	1			T832	1		T716	9		T502	1
values[56]	168	1			T832	1		T716	7		T502	1
values[57]	166	1			T832	1		T716	6		T502	2
values[58]	143	1			T832	1		T716	3		T502	1
values[59]	147	1			T832	1		T716	10		T502	1
values[60]	142	1			T832	1		T716	17		T502	1
values[61]	122	1			T832	1		T716	9		T502	1
values[62]	129	1			T832	1		T716	11		T502	1
values[63]	153	1			T832	1		T716	15		T502	1
values[64]	153	1			T832	1		T716	2		T502	1
values[65]	117	1			T832	1		T502	1		T479	1
values[66]	94	1			T832	1		T502	1		T479	2
values[67]	111	1			T832	1		T502	1		T479	2
values[68]	104	1			T832	1		T502	1		T479	3
values[69]	111	1			T832	1		T502	1		T479	10
values[70]	98	1			T832	1		T502	1		T479	7
values[71]	90	1			T832	1		T502	1		T479	1
values[72]	77	1			T832	1		T502	1		T479	2
values[73]	79	1			T832	1		T502	1		T479	3
values[74]	80	1			T832	1		T502	1		T479	1
values[75]	64	1			T832	1		T502	1		T479	2
values[76]	83	1			T832	1		T502	1		T479	13
values[77]	87	1			T832	2		T502	1		T479	9
values[78]	94	1			T832	1		T502	1		T479	4
values[79]	90	1			T832	1		T502	1		T479	4
values[80]	74	1			T832	1		T502	1		T479	5
values[81]	81	1			T832	1		T502	2		T479	14
values[82]	79	1			T832	1		T502	1		T479	10
values[83]	76	1			T832	1		T502	4		T479	7
values[84]	70	1			T832	1		T502	9		T479	2
values[85]	60	1			T832	1		T502	3		T479	2
values[86]	74	1			T832	1		T502	3		T479	3
values[87]	67	1			T832	1		T502	4		T479	2
values[88]	89	1			T832	1		T502	9		T479	4
values[89]	89	1			T832	1		T502	8		T479	2
values[90]	85	1			T832	1		T502	3		T479	7
values[91]	76	1			T832	1		T502	4		T479	5
values[92]	77	1			T832	1		T502	3		T479	1
values[93]	76	1			T832	1		T502	1		T479	2
values[94]	58	1			T832	1		T502	1		T479	2
values[95]	72	1			T832	1		T502	2		T479	3
values[96]	84	1			T832	1		T502	5		T479	7
values[97]	84	1			T832	1		T502	1		T479	2
values[98]	78	1			T832	1		T502	2		T479	1
values[99]	85	1			T832	1		T502	1		T479	3
values[100]	68	1			T832	1		T502	2		T479	3
values[101]	68	1			T832	1		T502	3		T479	4
values[102]	75	1			T832	1		T502	5		T479	6
values[103]	66	1			T832	1		T502	1		T479	8
values[104]	78	1			T832	1		T502	1		T479	4
values[105]	70	1			T832	1		T502	1		T479	2
values[106]	74	1			T832	1		T502	1		T479	1
values[107]	69	1			T832	1		T502	2		T479	5
values[108]	70	1			T832	1		T502	2		T479	6
values[109]	66	1			T832	1		T502	3		T479	3
values[110]	84	1			T832	1		T502	2		T479	3
values[111]	113	1			T832	1		T502	2		T479	4
values[112]	76	1			T832	1		T502	1		T479	2
values[113]	71	1			T832	1		T502	2		T479	4
values[114]	70	1			T832	1		T502	1		T479	3
values[115]	69	1			T832	1		T502	3		T479	1
values[116]	56	1			T832	1		T502	2		T479	3
values[117]	66	1			T832	1		T502	1		T479	3
values[118]	72	1			T832	1		T502	3		T479	3
values[119]	66	1			T832	1		T502	3		T479	2
values[120]	64	1			T832	1		T502	1		T479	1
values[121]	67	1			T832	1		T502	2		T479	4
values[122]	79	1			T832	1		T502	3		T479	14
values[123]	67	1			T832	1		T502	2		T479	10
values[124]	75	1			T832	1		T502	1		T479	7
values[125]	75	1			T832	1		T502	3		T479	14
values[126]	77	1			T832	1		T502	2		T479	21
values[127]	671	1			T832	33		T502	32		T479	28
values[128]	5437	1			T832	271		T502	233		T479	7