Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.sram_ctrl_ret_aon__ram_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	139765	1			T77	236		T82	3		T84	7
values[2]	9157	1			T77	1		T83	11		T566	1
values[3]	3667	1			T83	8		T553	8		T555	4
values[4]	2137	1			T83	9		T553	4		T497	3
values[5]	1198	1			T553	3		T497	11		T607	16
values[6]	870	1			T553	1		T497	11		T607	9
values[7]	554	1			T553	2		T497	6		T607	2
values[8]	376	1			T553	5		T497	10		T680	11
values[9]	272	1			T553	3		T497	3		T680	9
values[10]	294	1			T553	6		T497	15		T680	11
values[11]	246	1			T553	9		T497	6		T680	4
values[12]	222	1			T553	10		T497	10		T680	13
values[13]	200	1			T553	4		T497	3		T680	7
values[14]	210	1			T553	3		T497	4		T859	30
values[15]	226	1			T553	4		T497	6		T859	21
values[16]	263	1			T553	4		T497	10		T859	32
values[17]	260	1			T553	3		T497	5		T859	19
values[18]	210	1			T553	2		T497	15		T859	7
values[19]	220	1			T553	7		T497	12		T859	13
values[20]	207	1			T553	2		T497	9		T859	7
values[21]	221	1			T553	1		T497	6		T859	14
values[22]	202	1			T553	3		T497	4		T859	16
values[23]	169	1			T553	9		T497	3		T859	6
values[24]	212	1			T553	1		T497	9		T859	7
values[25]	233	1			T553	1		T497	3		T859	8
values[26]	192	1			T553	2		T497	5		T859	10
values[27]	201	1			T553	1		T497	8		T859	8
values[28]	199	1			T553	1		T497	10		T859	10
values[29]	230	1			T553	3		T497	22		T859	13
values[30]	209	1			T553	1		T497	8		T859	7
values[31]	176	1			T553	1		T497	9		T859	2
values[32]	195	1			T553	3		T497	5		T860	7
values[33]	220	1			T553	4		T497	4		T860	6
values[34]	180	1			T553	3		T497	7		T860	6
values[35]	189	1			T553	3		T497	19		T860	5
values[36]	183	1			T553	7		T497	5		T860	4
values[37]	200	1			T553	7		T497	6		T860	5
values[38]	244	1			T553	6		T497	6		T860	15
values[39]	214	1			T553	2		T497	7		T860	9
values[40]	168	1			T553	2		T497	6		T860	7
values[41]	206	1			T553	5		T497	18		T860	11
values[42]	183	1			T553	1		T497	8		T860	3
values[43]	201	1			T553	9		T497	3		T860	12
values[44]	169	1			T553	3		T497	4		T860	10
values[45]	184	1			T553	4		T497	7		T860	6
values[46]	184	1			T553	2		T497	12		T860	5
values[47]	174	1			T553	2		T497	2		T860	6
values[48]	166	1			T553	6		T497	4		T860	2
values[49]	186	1			T553	10		T497	11		T860	6
values[50]	190	1			T553	8		T497	18		T860	6
values[51]	183	1			T553	5		T497	8		T860	7
values[52]	191	1			T553	3		T497	3		T860	3
values[53]	167	1			T553	2		T497	9		T860	2
values[54]	167	1			T553	2		T497	17		T860	13
values[55]	169	1			T553	3		T497	9		T860	6
values[56]	146	1			T553	2		T497	3		T860	6
values[57]	164	1			T553	2		T497	5		T860	10
values[58]	149	1			T553	1		T497	14		T860	6
values[59]	152	1			T553	1		T497	20		T860	6
values[60]	126	1			T553	1		T497	5		T860	7
values[61]	120	1			T553	2		T497	2		T860	7
values[62]	161	1			T553	3		T497	4		T860	12
values[63]	123	1			T553	5		T497	2		T860	4
values[64]	137	1			T553	13		T497	6		T860	7
values[65]	153	1			T553	2		T497	9		T860	4
values[66]	115	1			T553	2		T497	6		T860	2
values[67]	109	1			T553	1		T497	4		T860	3
values[68]	104	1			T553	6		T497	7		T860	7
values[69]	93	1			T553	2		T497	8		T860	5
values[70]	99	1			T553	5		T497	5		T860	11
values[71]	126	1			T553	5		T497	5		T860	13
values[72]	91	1			T553	6		T497	2		T860	10
values[73]	79	1			T553	4		T497	6		T860	11
values[74]	86	1			T553	5		T497	7		T860	15
values[75]	70	1			T553	7		T497	2		T860	9
values[76]	71	1			T553	8		T860	12		T849	1
values[77]	90	1			T553	8		T860	12		T849	1
values[78]	87	1			T553	2		T860	11		T849	1
values[79]	66	1			T553	5		T860	7		T849	1
values[80]	67	1			T553	1		T860	9		T849	1
values[81]	65	1			T553	2		T860	6		T849	1
values[82]	80	1			T553	3		T860	4		T849	1
values[83]	92	1			T553	8		T860	8		T849	1
values[84]	72	1			T553	3		T860	6		T849	1
values[85]	83	1			T553	6		T860	3		T849	1
values[86]	69	1			T553	4		T860	3		T849	1
values[87]	61	1			T553	8		T860	3		T849	1
values[88]	74	1			T553	5		T860	7		T849	1
values[89]	78	1			T553	4		T860	6		T849	1
values[90]	78	1			T553	8		T860	2		T849	1
values[91]	75	1			T553	8		T860	12		T849	1
values[92]	61	1			T553	2		T860	7		T849	1
values[93]	60	1			T553	5		T860	8		T849	3
values[94]	83	1			T553	20		T860	15		T849	1
values[95]	73	1			T553	8		T860	9		T849	5
values[96]	63	1			T553	2		T860	4		T849	4
values[97]	68	1			T553	1		T860	1		T849	1
values[98]	79	1			T553	10		T860	7		T849	1
values[99]	80	1			T553	21		T860	2		T849	4
values[100]	64	1			T553	17		T860	1		T849	1
values[101]	94	1			T553	15		T860	7		T849	2
values[102]	68	1			T553	6		T860	2		T849	1
values[103]	59	1			T553	4		T860	4		T849	1
values[104]	54	1			T553	3		T860	5		T849	4
values[105]	62	1			T553	4		T860	7		T849	1
values[106]	49	1			T860	2		T849	1		T499	2
values[107]	59	1			T860	3		T849	1		T499	2
values[108]	72	1			T860	7		T849	1		T499	3
values[109]	58	1			T860	8		T849	1		T499	5
values[110]	49	1			T860	5		T849	2		T499	4
values[111]	48	1			T860	8		T849	1		T499	1
values[112]	49	1			T860	5		T849	3		T499	2
values[113]	64	1			T860	5		T849	2		T499	2
values[114]	61	1			T860	6		T849	4		T499	1
values[115]	56	1			T860	3		T849	3		T499	2
values[116]	62	1			T860	2		T849	1		T499	2
values[117]	59	1			T860	3		T849	1		T499	2
values[118]	77	1			T860	15		T849	1		T499	2
values[119]	73	1			T860	6		T849	3		T499	1
values[120]	61	1			T860	10		T849	6		T499	1
values[121]	59	1			T860	9		T849	1		T499	3
values[122]	51	1			T860	5		T849	1		T499	2
values[123]	63	1			T860	4		T849	2		T499	8
values[124]	44	1			T860	2		T849	5		T499	2
values[125]	48	1			T860	1		T849	2		T499	2
values[126]	104	1			T860	2		T849	1		T499	3
values[127]	717	1			T860	4		T849	29		T499	21
values[128]	5575	1			T860	1		T849	359		T499	286