Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.uart1_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	136598	1			T77	259		T82	11		T84	5
values[2]	8092	1			T452	2		T564	1		T453	9
values[3]	2870	1			T453	1		T565	2		T561	1
values[4]	1810	1			T565	1		T840	4		T571	1
values[5]	1239	1			T565	1		T840	4		T502	1
values[6]	907	1			T565	2		T502	1		T846	7
values[7]	660	1			T565	1		T502	1		T846	1
values[8]	575	1			T565	5		T502	1		T848	22
values[9]	391	1			T565	6		T502	1		T848	15
values[10]	339	1			T565	6		T502	1		T848	19
values[11]	330	1			T565	9		T502	1		T848	8
values[12]	283	1			T565	2		T502	1		T848	3
values[13]	284	1			T565	2		T502	1		T848	2
values[14]	268	1			T565	5		T502	1		T848	7
values[15]	251	1			T565	4		T502	1		T848	3
values[16]	309	1			T565	5		T502	1		T848	5
values[17]	274	1			T565	3		T502	1		T848	7
values[18]	244	1			T565	1		T502	1		T848	9
values[19]	275	1			T565	1		T502	1		T848	10
values[20]	222	1			T565	1		T502	1		T848	8
values[21]	225	1			T565	1		T502	1		T848	21
values[22]	225	1			T565	3		T502	1		T848	26
values[23]	223	1			T565	4		T502	1		T848	3
values[24]	236	1			T565	13		T502	1		T848	7
values[25]	225	1			T565	4		T502	1		T848	4
values[26]	259	1			T565	2		T502	1		T848	4
values[27]	239	1			T565	2		T502	1		T848	6
values[28]	274	1			T565	3		T502	1		T848	4
values[29]	235	1			T565	2		T502	1		T848	7
values[30]	274	1			T565	2		T502	1		T848	8
values[31]	292	1			T565	2		T502	1		T848	19
values[32]	203	1			T565	1		T502	1		T848	8
values[33]	243	1			T565	1		T502	1		T848	12
values[34]	222	1			T565	1		T502	1		T848	18
values[35]	215	1			T565	4		T502	1		T848	7
values[36]	208	1			T565	7		T502	1		T848	6
values[37]	231	1			T565	4		T502	1		T848	9
values[38]	216	1			T565	14		T502	1		T848	7
values[39]	241	1			T565	5		T502	1		T848	8
values[40]	190	1			T565	3		T502	1		T848	3
values[41]	198	1			T565	4		T502	1		T848	4
values[42]	219	1			T565	3		T502	1		T848	7
values[43]	200	1			T565	5		T502	1		T848	7
values[44]	223	1			T565	6		T502	1		T848	7
values[45]	196	1			T565	1		T502	1		T848	8
values[46]	184	1			T565	4		T502	1		T848	3
values[47]	182	1			T565	3		T502	1		T834	1
values[48]	182	1			T565	1		T502	1		T834	1
values[49]	180	1			T565	6		T502	1		T834	1
values[50]	181	1			T565	3		T502	1		T834	1
values[51]	162	1			T565	1		T502	1		T834	1
values[52]	189	1			T565	2		T502	1		T834	1
values[53]	163	1			T565	2		T502	1		T834	1
values[54]	128	1			T565	4		T502	1		T834	1
values[55]	143	1			T565	2		T502	1		T834	1
values[56]	146	1			T565	2		T502	1		T834	1
values[57]	189	1			T565	2		T502	1		T834	1
values[58]	166	1			T565	1		T502	1		T834	1
values[59]	161	1			T565	2		T502	1		T834	1
values[60]	145	1			T565	4		T502	1		T834	1
values[61]	147	1			T565	2		T502	1		T834	1
values[62]	125	1			T565	3		T502	2		T834	1
values[63]	110	1			T565	2		T502	1		T834	1
values[64]	102	1			T565	2		T502	1		T834	1
values[65]	98	1			T565	1		T502	1		T834	1
values[66]	113	1			T565	1		T502	1		T834	1
values[67]	103	1			T565	2		T502	1		T834	1
values[68]	111	1			T565	1		T502	1		T834	1
values[69]	136	1			T565	2		T502	1		T834	1
values[70]	108	1			T565	4		T502	1		T834	1
values[71]	87	1			T565	4		T502	1		T834	1
values[72]	94	1			T565	3		T502	1		T834	1
values[73]	91	1			T565	2		T502	1		T834	1
values[74]	102	1			T565	4		T502	1		T834	1
values[75]	84	1			T565	6		T502	1		T834	1
values[76]	91	1			T565	10		T502	1		T834	1
values[77]	114	1			T565	15		T502	1		T834	1
values[78]	77	1			T565	6		T502	1		T834	1
values[79]	89	1			T565	7		T502	1		T834	1
values[80]	114	1			T565	14		T502	1		T834	1
values[81]	104	1			T565	3		T502	1		T834	1
values[82]	70	1			T565	1		T502	1		T834	1
values[83]	84	1			T565	4		T502	1		T834	1
values[84]	61	1			T565	3		T502	1		T834	1
values[85]	82	1			T565	1		T502	3		T834	1
values[86]	98	1			T565	4		T502	2		T834	1
values[87]	88	1			T565	7		T502	2		T834	1
values[88]	78	1			T565	10		T502	6		T834	1
values[89]	116	1			T565	12		T502	4		T834	1
values[90]	83	1			T565	11		T502	1		T834	1
values[91]	59	1			T565	3		T502	1		T834	1
values[92]	76	1			T565	3		T502	4		T834	1
values[93]	67	1			T565	3		T502	5		T834	1
values[94]	59	1			T565	7		T502	5		T834	1
values[95]	68	1			T565	5		T502	1		T834	1
values[96]	46	1			T565	4		T502	1		T834	1
values[97]	66	1			T565	4		T502	6		T834	1
values[98]	56	1			T565	6		T502	2		T834	1
values[99]	66	1			T565	4		T502	1		T834	1
values[100]	70	1			T565	6		T502	4		T834	1
values[101]	63	1			T565	4		T502	1		T834	1
values[102]	56	1			T565	2		T502	2		T834	1
values[103]	59	1			T565	11		T502	3		T834	1
values[104]	67	1			T565	4		T502	6		T834	2
values[105]	82	1			T565	13		T502	1		T834	1
values[106]	52	1			T565	5		T502	5		T834	1
values[107]	56	1			T565	5		T502	2		T834	1
values[108]	59	1			T565	8		T502	3		T834	1
values[109]	59	1			T565	4		T502	1		T834	1
values[110]	60	1			T565	5		T502	3		T834	1
values[111]	47	1			T565	1		T502	1		T834	1
values[112]	48	1			T502	1		T834	1		T861	2
values[113]	39	1			T502	1		T834	1		T861	4
values[114]	56	1			T502	1		T834	1		T861	4
values[115]	61	1			T502	1		T834	1		T861	3
values[116]	62	1			T502	2		T834	1		T861	5
values[117]	48	1			T502	1		T834	1		T861	5
values[118]	44	1			T502	1		T834	1		T861	2
values[119]	52	1			T502	1		T834	1		T861	2
values[120]	54	1			T502	2		T834	1		T861	3
values[121]	47	1			T502	4		T834	1		T861	3
values[122]	44	1			T502	1		T834	1		T861	4
values[123]	51	1			T502	2		T834	1		T861	6
values[124]	63	1			T502	1		T834	2		T861	4
values[125]	68	1			T502	2		T834	3		T861	2
values[126]	160	1			T502	2		T834	2		T861	11
values[127]	653	1			T502	30		T834	28		T861	79
values[128]	4078	1			T502	286		T834	331		T861	576