Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	50	0	50	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	50	0	50	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	50	0	50	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	448	1			T83	1		T551	1		T454	1
all_values[1]	494	1			T453	3		T454	1		T830	4
all_values[2]	460	1			T454	4		T830	3		T866	3
all_values[3]	483	1			T83	1		T453	3		T565	1
all_values[4]	496	1			T83	1		T453	1		T553	1
all_values[5]	466	1			T77	2		T83	3		T453	3
all_values[6]	509	1			T464	1		T453	1		T551	1
all_values[7]	512	1			T83	1		T453	3		T830	2
all_values[8]	459	1			T453	2		T454	3		T563	1
all_values[9]	465	1			T77	1		T83	2		T453	3
all_values[10]	496	1			T83	2		T464	1		T453	1
all_values[11]	505	1			T83	2		T453	2		T454	1
all_values[12]	444	1			T464	1		T453	1		T454	2
all_values[13]	466	1			T77	1		T83	2		T453	4
all_values[14]	490	1			T83	1		T453	3		T454	2
all_values[15]	479	1			T83	1		T464	1		T453	3
all_values[16]	503	1			T83	5		T453	1		T830	1
all_values[17]	497	1			T83	2		T464	1		T453	1
all_values[18]	473	1			T83	1		T464	1		T454	4
all_values[19]	480	1			T453	2		T454	2		T830	4
all_values[20]	504	1			T83	3		T464	1		T453	1
all_values[21]	496	1			T83	2		T453	2		T565	1
all_values[22]	473	1			T83	1		T453	2		T454	2
all_values[23]	488	1			T83	1		T453	2		T565	1
all_values[24]	472	1			T453	1		T565	1		T454	1
all_values[25]	495	1			T453	1		T553	1		T565	1
all_values[26]	465	1			T83	2		T453	3		T553	1
all_values[27]	532	1			T453	1		T454	2		T830	1
all_values[28]	465	1			T83	4		T453	4		T551	1
all_values[29]	499	1			T83	1		T453	2		T551	1
all_values[30]	462	1			T77	1		T464	1		T551	1
all_values[31]	472	1			T464	1		T453	1		T565	1
all_values[32]	472	1			T75	1		T453	1		T454	2
all_values[33]	509	1			T83	2		T453	4		T454	3
all_values[34]	456	1			T464	1		T453	1		T565	1
all_values[35]	466	1			T83	1		T453	2		T551	1
all_values[36]	479	1			T565	1		T454	1		T830	6
all_values[37]	485	1			T83	1		T464	1		T453	3
all_values[38]	472	1			T464	1		T453	1		T830	6
all_values[39]	440	1			T83	2		T453	2		T551	1
all_values[40]	488	1			T565	1		T454	2		T830	4
all_values[41]	518	1			T77	1		T83	1		T453	3
all_values[42]	509	1			T83	2		T464	1		T453	1
all_values[43]	501	1			T83	1		T464	1		T453	4
all_values[44]	486	1			T77	1		T83	1		T565	1
all_values[45]	462	1			T83	2		T453	1		T553	1
all_values[46]	457	1			T453	2		T553	1		T563	1
all_values[47]	438	1			T83	1		T464	1		T453	1
all_values[48]	487	1			T83	1		T453	1		T454	2
all_values[49]	486	1			T83	1		T453	3		T830	1