Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	3724	1			T77	1		T83	10		T453	6
all_values[1]	3732	1			T83	4		T453	12		T454	18
all_values[2]	3666	1			T77	4		T83	7		T453	9
all_values[3]	3559	1			T77	2		T83	6		T453	9
all_values[4]	3739	1			T77	2		T83	16		T453	8
all_values[5]	3633	1			T77	5		T83	12		T453	10
all_values[6]	3650	1			T77	2		T83	4		T453	9
all_values[7]	3750	1			T83	6		T453	14		T454	12
all_values[8]	3687	1			T77	6		T83	6		T453	11
all_values[9]	3597	1			T77	3		T83	9		T453	7
all_values[10]	3634	1			T77	2		T83	11		T453	5
all_values[11]	3659	1			T77	3		T83	4		T453	6
all_values[12]	3522	1			T77	4		T83	10		T453	10
all_values[13]	3659	1			T77	4		T83	8		T453	9
all_values[14]	3609	1			T77	7		T83	6		T453	13
all_values[15]	3633	1			T83	14		T453	8		T454	12
all_values[16]	3609	1			T77	2		T83	10		T453	6
all_values[17]	3612	1			T77	3		T83	7		T453	11
all_values[18]	3611	1			T77	5		T83	16		T453	9
all_values[19]	3596	1			T77	5		T83	7		T453	9
all_values[20]	3656	1			T77	2		T83	13		T453	9
all_values[21]	3683	1			T77	1		T83	5		T453	3
all_values[22]	3626	1			T83	4		T453	12		T454	21
all_values[23]	3613	1			T77	1		T83	8		T453	5
all_values[24]	3663	1			T77	1		T83	11		T453	11
all_values[25]	3836	1			T77	4		T83	8		T453	3
all_values[26]	3691	1			T77	4		T83	13		T453	8
all_values[27]	3693	1			T77	5		T83	11		T453	7
all_values[28]	3616	1			T77	2		T83	3		T453	3
all_values[29]	3700	1			T77	4		T83	12		T453	3
all_values[30]	3617	1			T77	3		T83	12		T453	13
all_values[31]	3710	1			T77	5		T83	13		T453	12
all_values[32]	3541	1			T77	2		T83	10		T453	6
all_values[33]	3584	1			T77	3		T83	4		T453	12
all_values[34]	3649	1			T77	2		T83	5		T453	6
all_values[35]	3540	1			T77	2		T83	5		T453	6
all_values[36]	3704	1			T77	1		T83	7		T453	6
all_values[37]	3633	1			T77	5		T83	12		T453	7
all_values[38]	3597	1			T77	3		T83	8		T453	10
all_values[39]	3659	1			T77	4		T83	13		T453	6
all_values[40]	3620	1			T83	9		T453	7		T454	17
all_values[41]	3663	1			T77	5		T83	6		T453	9
all_values[42]	3622	1			T77	1		T83	6		T453	8
all_values[43]	3598	1			T77	4		T83	4		T453	9
all_values[44]	3580	1			T77	3		T83	13		T453	6
all_values[45]	3665	1			T77	6		T83	4		T453	13
all_values[46]	3599	1			T77	2		T83	5		T453	9
all_values[47]	3721	1			T77	1		T83	7		T453	9
all_values[48]	3598	1			T77	3		T83	9		T453	12
all_values[49]	3619	1			T77	1		T83	13		T453	6
all_values[50]	3652	1			T77	2		T83	11		T453	9
all_values[51]	3722	1			T77	3		T83	13		T453	11
all_values[52]	3581	1			T77	3		T83	8		T453	5
all_values[53]	3620	1			T77	2		T83	8		T453	9
all_values[54]	3609	1			T77	5		T83	10		T453	12
all_values[55]	3489	1			T77	5		T83	13		T453	1
all_values[56]	3572	1			T77	2		T83	11		T453	10
all_values[57]	3687	1			T77	1		T83	8		T453	5
all_values[58]	3713	1			T77	3		T83	7		T453	5
all_values[59]	3601	1			T77	6		T83	8		T453	5
all_values[60]	3633	1			T77	2		T83	13		T453	10
all_values[61]	3589	1			T77	7		T83	5		T453	9
all_values[62]	3607	1			T77	2		T83	4		T453	12
all_values[63]	3654	1			T77	4		T83	8		T453	8