LINE 16833
EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO185_OFFSET)
--------------------------1--------------------------
| -1- | Status | Tests |
|---|---|---|
| 0 | Covered | T3,T4,T91 |
| 1 | Covered | T262,T321,T161 |
LINE 16834
EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_IP_0_OFFSET)
-------------------------1------------------------
| -1- | Status | Tests |
|---|---|---|
| 0 | Covered | T3,T4,T91 |
| 1 | Covered | T76,T133,T152 |
LINE 16835
EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_IP_1_OFFSET)
-------------------------1------------------------
| -1- | Status | Tests |
|---|---|---|
| 0 | Covered | T3,T4,T91 |
| 1 | Covered | T76,T133,T152 |
LINE 16836
EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_IP_2_OFFSET)
-------------------------1------------------------
| -1- | Status | Tests |
|---|---|---|
| 0 | Covered | T3,T4,T91 |
| 1 | Covered | T76,T133,T152 |
LINE 16837
EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_IP_3_OFFSET)
-------------------------1------------------------
| -1- | Status | Tests |
|---|---|---|
| 0 | Covered | T3,T4,T91 |
| 1 | Covered | T76,T133,T152 |
LINE 16838
EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_IP_4_OFFSET)
-------------------------1------------------------
| -1- | Status | Tests |
|---|---|---|
| 0 | Covered | T3,T4,T91 |
| 1 | Covered | T699,T700,T701 |
LINE 16839
EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_IP_5_OFFSET)
-------------------------1------------------------
| -1- | Status | Tests |
|---|---|---|
| 0 | Covered | T3,T4,T91 |
| 1 | Covered | T76,T133,T152 |
LINE 16840
EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_IE0_0_OFFSET)
-------------------------1-------------------------
| -1- | Status | Tests |
|---|---|---|
| 0 | Covered | T3,T4,T91 |
| 1 | Covered | T91,T14,T95 |
LINE 16841
EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_IE0_1_OFFSET)
-------------------------1-------------------------
| -1- | Status | Tests |
|---|---|---|
| 0 | Covered | T3,T4,T91 |
| 1 | Covered | T14,T262,T321 |
LINE 16842
EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_IE0_2_OFFSET)
-------------------------1-------------------------
| -1- | Status | Tests |
|---|---|---|
| 0 | Covered | T3,T4,T91 |
| 1 | Covered | T262,T321,T16 |
LINE 16843
EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_IE0_3_OFFSET)
-------------------------1-------------------------
| -1- | Status | Tests |
|---|---|---|
| 0 | Covered | T3,T4,T91 |
| 1 | Covered | T4,T63,T221 |
LINE 16844
EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_IE0_4_OFFSET)
-------------------------1-------------------------
| -1- | Status | Tests |
|---|---|---|
| 0 | Covered | T3,T4,T91 |
| 1 | Covered | T3,T4,T59 |
LINE 16845
EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_IE0_5_OFFSET)
-------------------------1-------------------------
| -1- | Status | Tests |
|---|---|---|
| 0 | Covered | T3,T4,T91 |
| 1 | Covered | T130,T99,T12 |
LINE 16846
EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_THRESHOLD0_OFFSET)
----------------------------1---------------------------
| -1- | Status | Tests |
|---|---|---|
| 0 | Covered | T3,T4,T91 |
| 1 | Covered | T3,T4,T91 |
LINE 16847
EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_CC0_OFFSET)
------------------------1------------------------
| -1- | Status | Tests |
|---|---|---|
| 0 | Covered | T3,T4,T91 |
| 1 | Covered | T3,T91,T59 |
LINE 16848
EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_MSIP0_OFFSET)
-------------------------1-------------------------
| -1- | Status | Tests |
|---|---|---|
| 0 | Covered | T3,T4,T91 |
| 1 | Covered | T257,T258,T259 |
LINE 16849
EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_ALERT_TEST_OFFSET)
----------------------------1---------------------------
| -1- | Status | Tests |
|---|---|---|
| 0 | Covered | T3,T4,T91 |
| 1 | Covered | T49,T50,T51 |
LINE 16852
EXPRESSION ((reg_re || reg_we) ? ((~|addr_hit)) : 1'b0)
---------1--------
| -1- | Status | Tests |
|---|---|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T3,T4,T91 |
LINE 16852
SUB-EXPRESSION (reg_re || reg_we)
---1-- ---2--
| -1- | -2- | Status | Tests |
|---|---|---|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T3,T4,T91 |
| 1 | 0 | Covered | T3,T4,T91 |
LINE 16856
EXPRESSION
Number Term
1 reg_we &
2 ((addr_hit[0] & ((|(4'b1 & (~reg_be))))) | (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | (addr_hit[5] & ((|(4'b1 & (~reg_be))))) | (addr_hit[6] & ((|(4'b1 & (~reg_be))))) | (addr_hit[7] & ((|(4'b1 & (~reg_be))))) | (addr_hit[8] & ((|(4'b1 & (~reg_be))))) | (addr_hit[9] & ((|(4'b1 & (~reg_be))))) | (addr_hit[10] & ((|(4'b1 & (~reg_be))))) | (addr_hit[11] & ((|(4'b1 & (~reg_be))))) | (addr_hit[12] & ((|(4'b1 & (~reg_be))))) | (addr_hit[13] & ((|(4'b1 & (~reg_be))))) | (addr_hit[14] & ((|(4'b1 & (~reg_be))))) | (addr_hit[15] & ((|(4'b1 & (~reg_be))))) | (addr_hit[16] & ((|(4'b1 & (~reg_be))))) | (addr_hit[17] & ((|(4'b1 & (~reg_be))))) | (addr_hit[18] & ((|(4'b1 & (~reg_be))))) | (addr_hit[19] & ((|(4'b1 & (~reg_be))))) | (addr_hit[20] & ((|(4'b1 & (~reg_be))))) | (addr_hit[21] & ((|(4'b1 & (~reg_be))))) | (addr_hit[22] & ((|(4'b1 & (~reg_be))))) | (addr_hit[23] & ((|(4'b1 & (~reg_be))))) | (addr_hit[24] & ((|(4'b1 & (~reg_be))))) | (addr_hit[25] & ((|(4'b1 & (~reg_be))))) | (addr_hit[26] & ((|(4'b1 & (~reg_be))))) | (addr_hit[27] & ((|(4'b1 & (~reg_be))))) | (addr_hit[28] & ((|(4'b1 & (~reg_be))))) | (addr_hit[29] & ((|(4'b1 & (~reg_be))))) | (addr_hit[30] & ((|(4'b1 & (~reg_be))))) | (addr_hit[31] & ((|(4'b1 & (~reg_be))))) | (addr_hit[32] & ((|(4'b1 & (~reg_be))))) | (addr_hit[33] & ((|(4'b1 & (~reg_be))))) | (addr_hit[34] & ((|(4'b1 & (~reg_be))))) | (addr_hit[35] & ((|(4'b1 & (~reg_be))))) | (addr_hit[36] & ((|(4'b1 & (~reg_be))))) | (addr_hit[37] & ((|(4'b1 & (~reg_be))))) | (addr_hit[38] & ((|(4'b1 & (~reg_be))))) | (addr_hit[39] & ((|(4'b1 & (~reg_be))))) | (addr_hit[40] & ((|(4'b1 & (~reg_be))))) | (addr_hit[41] & ((|(4'b1 & (~reg_be))))) | (addr_hit[42] & ((|(4'b1 & (~reg_be))))) | (addr_hit[43] & ((|(4'b1 & (~reg_be))))) | (addr_hit[44] & ((|(4'b1 & (~reg_be))))) | (addr_hit[45] & ((|(4'b1 & (~reg_be))))) | (addr_hit[46] & ((|(4'b1 & (~reg_be))))) | (addr_hit[47] & ((|(4'b1 & (~reg_be))))) | (addr_hit[48] & ((|(4'b1 & (~reg_be))))) | (addr_hit[49] & ((|(4'b1 & (~reg_be))))) | (addr_hit[50] & ((|(4'b1 & (~reg_be))))) | (addr_hit[51] & ((|(4'b1 & (~reg_be))))) | (addr_hit[52] & ((|(4'b1 & (~reg_be))))) | (addr_hit[53] & ((|(4'b1 & (~reg_be))))) | (addr_hit[54] & ((|(4'b1 & (~reg_be))))) | (addr_hit[55] & ((|(4'b1 & (~reg_be))))) | (addr_hit[56] & ((|(4'b1 & (~reg_be))))) | (addr_hit[57] & ((|(4'b1 & (~reg_be))))) | (addr_hit[58] & ((|(4'b1 & (~reg_be))))) | (addr_hit[59] & ((|(4'b1 & (~reg_be))))) | (addr_hit[60] & ((|(4'b1 & (~reg_be))))) | (addr_hit[61] & ((|(4'b1 & (~reg_be))))) | (addr_hit[62] & ((|(4'b1 & (~reg_be))))) | (addr_hit[63] & ((|(4'b1 & (~reg_be))))) | (addr_hit[64] & ((|(4'b1 & (~reg_be))))) | (addr_hit[65] & ((|(4'b1 & (~reg_be))))) | (addr_hit[66] & ((|(4'b1 & (~reg_be))))) | (addr_hit[67] & ((|(4'b1 & (~reg_be))))) | (addr_hit[68] & ((|(4'b1 & (~reg_be))))) | (addr_hit[69] & ((|(4'b1 & (~reg_be))))) | (addr_hit[70] & ((|(4'b1 & (~reg_be))))) | (addr_hit[71] & ((|(4'b1 & (~reg_be))))) | (addr_hit[72] & ((|(4'b1 & (~reg_be))))) | (addr_hit[73] & ((|(4'b1 & (~reg_be))))) | (addr_hit[74] & ((|(4'b1 & (~reg_be))))) | (addr_hit[75] & ((|(4'b1 & (~reg_be))))) | (addr_hit[76] & ((|(4'b1 & (~reg_be))))) | (addr_hit[77] & ((|(4'b1 & (~reg_be))))) | (addr_hit[78] & ((|(4'b1 & (~reg_be))))) | (addr_hit[79] & ((|(4'b1 & (~reg_be))))) | (addr_hit[80] & ((|(4'b1 & (~reg_be))))) | (addr_hit[81] & ((|(4'b1 & (~reg_be))))) | (addr_hit[82] & ((|(4'b1 & (~reg_be))))) | (addr_hit[83] & ((|(4'b1 & (~reg_be))))) | (addr_hit[84] & ((|(4'b1 & (~reg_be))))) | (addr_hit[85] & ((|(4'b1 & (~reg_be))))) | (addr_hit[86] & ((|(4'b1 & (~reg_be))))) | (addr_hit[87] & ((|(4'b1 & (~reg_be))))) | (addr_hit[88] & ((|(4'b1 & (~reg_be))))) | (addr_hit[89] & ((|(4'b1 & (~reg_be))))) | (addr_hit[90] & ((|(4'b1 & (~reg_be))))) | (addr_hit[91] & ((|(4'b1 & (~reg_be))))) | (addr_hit[92] & ((|(4'b1 & (~reg_be))))) | (addr_hit[93] & ((|(4'b1 & (~reg_be))))) | (addr_hit[94] & ((|(4'b1 & (~reg_be))))) | (addr_hit[95] & ((|(4'b1 & (~reg_be))))) | (addr_hit[96] & ((|(4'b1 & (~reg_be))))) | (addr_hit[97] & ((|(4'b1 & (~reg_be))))) | (addr_hit[98] & ((|(4'b1 & (~reg_be))))) | (addr_hit[99] & ((|(4'b1 & (~reg_be))))) | (addr_hit[100] & ((|(4'b1 & (~reg_be))))) | (addr_hit[101] & ((|(4'b1 & (~reg_be))))) | (addr_hit[102] & ((|(4'b1 & (~reg_be))))) | (addr_hit[103] & ((|(4'b1 & (~reg_be))))) | (addr_hit[104] & ((|(4'b1 & (~reg_be))))) | (addr_hit[105] & ((|(4'b1 & (~reg_be))))) | (addr_hit[106] & ((|(4'b1 & (~reg_be))))) | (addr_hit[107] & ((|(4'b1 & (~reg_be))))) | (addr_hit[108] & ((|(4'b1 & (~reg_be))))) | (addr_hit[109] & ((|(4'b1 & (~reg_be))))) | (addr_hit[110] & ((|(4'b1 & (~reg_be))))) | (addr_hit[111] & ((|(4'b1 & (~reg_be))))) | (addr_hit[112] & ((|(4'b1 & (~reg_be))))) | (addr_hit[113] & ((|(4'b1 & (~reg_be))))) | (addr_hit[114] & ((|(4'b1 & (~reg_be))))) | (addr_hit[115] & ((|(4'b1 & (~reg_be))))) | (addr_hit[116] & ((|(4'b1 & (~reg_be))))) | (addr_hit[117] & ((|(4'b1 & (~reg_be))))) | (addr_hit[118] & ((|(4'b1 & (~reg_be))))) | (addr_hit[119] & ((|(4'b1 & (~reg_be))))) | (addr_hit[120] & ((|(4'b1 & (~reg_be))))) | (addr_hit[121] & ((|(4'b1 & (~reg_be))))) | (addr_hit[122] & ((|(4'b1 & (~reg_be))))) | (addr_hit[123] & ((|(4'b1 & (~reg_be))))) | (addr_hit[124] & ((|(4'b1 & (~reg_be))))) | (addr_hit[125] & ((|(4'b1 & (~reg_be))))) | (addr_hit[126] & ((|(4'b1 & (~reg_be))))) | (addr_hit[127] & ((|(4'b1 & (~reg_be))))) | (addr_hit[128] & ((|(4'b1 & (~reg_be))))) | (addr_hit[129] & ((|(4'b1 & (~reg_be))))) | (addr_hit[130] & ((|(4'b1 & (~reg_be))))) | (addr_hit[131] & ((|(4'b1 & (~reg_be))))) | (addr_hit[132] & ((|(4'b1 & (~reg_be))))) | (addr_hit[133] & ((|(4'b1 & (~reg_be))))) | (addr_hit[134] & ((|(4'b1 & (~reg_be))))) | (addr_hit[135] & ((|(4'b1 & (~reg_be))))) | (addr_hit[136] & ((|(4'b1 & (~reg_be))))) | (addr_hit[137] & ((|(4'b1 & (~reg_be))))) | (addr_hit[138] & ((|(4'b1 & (~reg_be))))) | (addr_hit[139] & ((|(4'b1 & (~reg_be))))) | (addr_hit[140] & ((|(4'b1 & (~reg_be))))) | (addr_hit[141] & ((|(4'b1 & (~reg_be))))) | (addr_hit[142] & ((|(4'b1 & (~reg_be))))) | (addr_hit[143] & ((|(4'b1 & (~reg_be))))) | (addr_hit[144] & ((|(4'b1 & (~reg_be))))) | (addr_hit[145] & ((|(4'b1 & (~reg_be))))) | (addr_hit[146] & ((|(4'b1 & (~reg_be))))) | (addr_hit[147] & ((|(4'b1 & (~reg_be))))) | (addr_hit[148] & ((|(4'b1 & (~reg_be))))) | (addr_hit[149] & ((|(4'b1 & (~reg_be))))) | (addr_hit[150] & ((|(4'b1 & (~reg_be))))) | (addr_hit[151] & ((|(4'b1 & (~reg_be))))) | (addr_hit[152] & ((|(4'b1 & (~reg_be))))) | (addr_hit[153] & ((|(4'b1 & (~reg_be))))) | (addr_hit[154] & ((|(4'b1 & (~reg_be))))) | (addr_hit[155] & ((|(4'b1 & (~reg_be))))) | (addr_hit[156] & ((|(4'b1 & (~reg_be))))) | (addr_hit[157] & ((|(4'b1 & (~reg_be))))) | (addr_hit[158] & ((|(4'b1 & (~reg_be))))) | (addr_hit[159] & ((|(4'b1 & (~reg_be))))) | (addr_hit[160] & ((|(4'b1 & (~reg_be))))) | (addr_hit[161] & ((|(4'b1 & (~reg_be))))) | (addr_hit[162] & ((|(4'b1 & (~reg_be))))) | (addr_hit[163] & ((|(4'b1 & (~reg_be))))) | (addr_hit[164] & ((|(4'b1 & (~reg_be))))) | (addr_hit[165] & ((|(4'b1 & (~reg_be))))) | (addr_hit[166] & ((|(4'b1 & (~reg_be))))) | (addr_hit[167] & ((|(4'b1 & (~reg_be))))) | (addr_hit[168] & ((|(4'b1 & (~reg_be))))) | (addr_hit[169] & ((|(4'b1 & (~reg_be))))) | (addr_hit[170] & ((|(4'b1 & (~reg_be))))) | (addr_hit[171] & ((|(4'b1 & (~reg_be))))) | (addr_hit[172] & ((|(4'b1 & (~reg_be))))) | (addr_hit[173] & ((|(4'b1 & (~reg_be))))) | (addr_hit[174] & ((|(4'b1 & (~reg_be))))) | (addr_hit[175] & ((|(4'b1 & (~reg_be))))) | (addr_hit[176] & ((|(4'b1 & (~reg_be))))) | (addr_hit[177] & ((|(4'b1 & (~reg_be))))) | (addr_hit[178] & ((|(4'b1 & (~reg_be))))) | (addr_hit[179] & ((|(4'b1 & (~reg_be))))) | (addr_hit[180] & ((|(4'b1 & (~reg_be))))) | (addr_hit[181] & ((|(4'b1 & (~reg_be))))) | (addr_hit[182] & ((|(4'b1 & (~reg_be))))) | (addr_hit[183] & ((|(4'b1 & (~reg_be))))) | (addr_hit[184] & ((|(4'b1 & (~reg_be))))) | (addr_hit[185] & ((|(4'b1 & (~reg_be))))) | (addr_hit[186] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[187] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[188] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[189] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[190] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[191] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[192] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[193] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[194] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[195] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[196] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[197] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[198] & ((|(4'b1 & (~reg_be))))) | (addr_hit[199] & ((|(4'b1 & (~reg_be))))) | (addr_hit[200] & ((|(4'b1 & (~reg_be))))) | (addr_hit[201] & ((|(4'b1 & (~reg_be)))))))
| -1- | -2- | Status | Tests |
|---|---|---|---|
| 0 | 1 | Covered | T3,T4,T91 |
| 1 | 0 | Covered | T3,T4,T91 |
| 1 | 1 | Covered | T76,T552,T579 |
LINE 16856
SUB-EXPRESSION
Number Term
1 (addr_hit[0] & ((|(4'b1 & (~reg_be))))) |
2 (addr_hit[1] & ((|(4'b1 & (~reg_be))))) |
3 (addr_hit[2] & ((|(4'b1 & (~reg_be))))) |
4 (addr_hit[3] & ((|(4'b1 & (~reg_be))))) |
5 (addr_hit[4] & ((|(4'b1 & (~reg_be))))) |
6 (addr_hit[5] & ((|(4'b1 & (~reg_be))))) |
7 (addr_hit[6] & ((|(4'b1 & (~reg_be))))) |
8 (addr_hit[7] & ((|(4'b1 & (~reg_be))))) |
9 (addr_hit[8] & ((|(4'b1 & (~reg_be))))) |
10 (addr_hit[9] & ((|(4'b1 & (~reg_be))))) |
11 (addr_hit[10] & ((|(4'b1 & (~reg_be))))) |
12 (addr_hit[11] & ((|(4'b1 & (~reg_be))))) |
13 (addr_hit[12] & ((|(4'b1 & (~reg_be))))) |
14 (addr_hit[13] & ((|(4'b1 & (~reg_be))))) |
15 (addr_hit[14] & ((|(4'b1 & (~reg_be))))) |
16 (addr_hit[15] & ((|(4'b1 & (~reg_be))))) |
17 (addr_hit[16] & ((|(4'b1 & (~reg_be))))) |
18 (addr_hit[17] & ((|(4'b1 & (~reg_be))))) |
19 (addr_hit[18] & ((|(4'b1 & (~reg_be))))) |
20 (addr_hit[19] & ((|(4'b1 & (~reg_be))))) |
21 (addr_hit[20] & ((|(4'b1 & (~reg_be))))) |
22 (addr_hit[21] & ((|(4'b1 & (~reg_be))))) |
23 (addr_hit[22] & ((|(4'b1 & (~reg_be))))) |
24 (addr_hit[23] & ((|(4'b1 & (~reg_be))))) |
25 (addr_hit[24] & ((|(4'b1 & (~reg_be))))) |
26 (addr_hit[25] & ((|(4'b1 & (~reg_be))))) |
27 (addr_hit[26] & ((|(4'b1 & (~reg_be))))) |
28 (addr_hit[27] & ((|(4'b1 & (~reg_be))))) |
29 (addr_hit[28] & ((|(4'b1 & (~reg_be))))) |
30 (addr_hit[29] & ((|(4'b1 & (~reg_be))))) |
31 (addr_hit[30] & ((|(4'b1 & (~reg_be))))) |
32 (addr_hit[31] & ((|(4'b1 & (~reg_be))))) |
33 (addr_hit[32] & ((|(4'b1 & (~reg_be))))) |
34 (addr_hit[33] & ((|(4'b1 & (~reg_be))))) |
35 (addr_hit[34] & ((|(4'b1 & (~reg_be))))) |
36 (addr_hit[35] & ((|(4'b1 & (~reg_be))))) |
37 (addr_hit[36] & ((|(4'b1 & (~reg_be))))) |
38 (addr_hit[37] & ((|(4'b1 & (~reg_be))))) |
39 (addr_hit[38] & ((|(4'b1 & (~reg_be))))) |
40 (addr_hit[39] & ((|(4'b1 & (~reg_be))))) |
41 (addr_hit[40] & ((|(4'b1 & (~reg_be))))) |
42 (addr_hit[41] & ((|(4'b1 & (~reg_be))))) |
43 (addr_hit[42] & ((|(4'b1 & (~reg_be))))) |
44 (addr_hit[43] & ((|(4'b1 & (~reg_be))))) |
45 (addr_hit[44] & ((|(4'b1 & (~reg_be))))) |
46 (addr_hit[45] & ((|(4'b1 & (~reg_be))))) |
47 (addr_hit[46] & ((|(4'b1 & (~reg_be))))) |
48 (addr_hit[47] & ((|(4'b1 & (~reg_be))))) |
49 (addr_hit[48] & ((|(4'b1 & (~reg_be))))) |
50 (addr_hit[49] & ((|(4'b1 & (~reg_be))))) |
51 (addr_hit[50] & ((|(4'b1 & (~reg_be))))) |
52 (addr_hit[51] & ((|(4'b1 & (~reg_be))))) |
53 (addr_hit[52] & ((|(4'b1 & (~reg_be))))) |
54 (addr_hit[53] & ((|(4'b1 & (~reg_be))))) |
55 (addr_hit[54] & ((|(4'b1 & (~reg_be))))) |
56 (addr_hit[55] & ((|(4'b1 & (~reg_be))))) |
57 (addr_hit[56] & ((|(4'b1 & (~reg_be))))) |
58 (addr_hit[57] & ((|(4'b1 & (~reg_be))))) |
59 (addr_hit[58] & ((|(4'b1 & (~reg_be))))) |
60 (addr_hit[59] & ((|(4'b1 & (~reg_be))))) |
61 (addr_hit[60] & ((|(4'b1 & (~reg_be))))) |
62 (addr_hit[61] & ((|(4'b1 & (~reg_be))))) |
63 (addr_hit[62] & ((|(4'b1 & (~reg_be))))) |
64 (addr_hit[63] & ((|(4'b1 & (~reg_be))))) |
65 (addr_hit[64] & ((|(4'b1 & (~reg_be))))) |
66 (addr_hit[65] & ((|(4'b1 & (~reg_be))))) |
67 (addr_hit[66] & ((|(4'b1 & (~reg_be))))) |
68 (addr_hit[67] & ((|(4'b1 & (~reg_be))))) |
69 (addr_hit[68] & ((|(4'b1 & (~reg_be))))) |
70 (addr_hit[69] & ((|(4'b1 & (~reg_be))))) |
71 (addr_hit[70] & ((|(4'b1 & (~reg_be))))) |
72 (addr_hit[71] & ((|(4'b1 & (~reg_be))))) |
73 (addr_hit[72] & ((|(4'b1 & (~reg_be))))) |
74 (addr_hit[73] & ((|(4'b1 & (~reg_be))))) |
75 (addr_hit[74] & ((|(4'b1 & (~reg_be))))) |
76 (addr_hit[75] & ((|(4'b1 & (~reg_be))))) |
77 (addr_hit[76] & ((|(4'b1 & (~reg_be))))) |
78 (addr_hit[77] & ((|(4'b1 & (~reg_be))))) |
79 (addr_hit[78] & ((|(4'b1 & (~reg_be))))) |
80 (addr_hit[79] & ((|(4'b1 & (~reg_be))))) |
81 (addr_hit[80] & ((|(4'b1 & (~reg_be))))) |
82 (addr_hit[81] & ((|(4'b1 & (~reg_be))))) |
83 (addr_hit[82] & ((|(4'b1 & (~reg_be))))) |
84 (addr_hit[83] & ((|(4'b1 & (~reg_be))))) |
85 (addr_hit[84] & ((|(4'b1 & (~reg_be))))) |
86 (addr_hit[85] & ((|(4'b1 & (~reg_be))))) |
87 (addr_hit[86] & ((|(4'b1 & (~reg_be))))) |
88 (addr_hit[87] & ((|(4'b1 & (~reg_be))))) |
89 (addr_hit[88] & ((|(4'b1 & (~reg_be))))) |
90 (addr_hit[89] & ((|(4'b1 & (~reg_be))))) |
91 (addr_hit[90] & ((|(4'b1 & (~reg_be))))) |
92 (addr_hit[91] & ((|(4'b1 & (~reg_be))))) |
93 (addr_hit[92] & ((|(4'b1 & (~reg_be))))) |
94 (addr_hit[93] & ((|(4'b1 & (~reg_be))))) |
95 (addr_hit[94] & ((|(4'b1 & (~reg_be))))) |
96 (addr_hit[95] & ((|(4'b1 & (~reg_be))))) |
97 (addr_hit[96] & ((|(4'b1 & (~reg_be))))) |
98 (addr_hit[97] & ((|(4'b1 & (~reg_be))))) |
99 (addr_hit[98] & ((|(4'b1 & (~reg_be))))) |
100 (addr_hit[99] & ((|(4'b1 & (~reg_be))))) |
101 (addr_hit[100] & ((|(4'b1 & (~reg_be))))) |
102 (addr_hit[101] & ((|(4'b1 & (~reg_be))))) |
103 (addr_hit[102] & ((|(4'b1 & (~reg_be))))) |
104 (addr_hit[103] & ((|(4'b1 & (~reg_be))))) |
105 (addr_hit[104] & ((|(4'b1 & (~reg_be))))) |
106 (addr_hit[105] & ((|(4'b1 & (~reg_be))))) |
107 (addr_hit[106] & ((|(4'b1 & (~reg_be))))) |
108 (addr_hit[107] & ((|(4'b1 & (~reg_be))))) |
109 (addr_hit[108] & ((|(4'b1 & (~reg_be))))) |
110 (addr_hit[109] & ((|(4'b1 & (~reg_be))))) |
111 (addr_hit[110] & ((|(4'b1 & (~reg_be))))) |
112 (addr_hit[111] & ((|(4'b1 & (~reg_be))))) |
113 (addr_hit[112] & ((|(4'b1 & (~reg_be))))) |
114 (addr_hit[113] & ((|(4'b1 & (~reg_be))))) |
115 (addr_hit[114] & ((|(4'b1 & (~reg_be))))) |
116 (addr_hit[115] & ((|(4'b1 & (~reg_be))))) |
117 (addr_hit[116] & ((|(4'b1 & (~reg_be))))) |
118 (addr_hit[117] & ((|(4'b1 & (~reg_be))))) |
119 (addr_hit[118] & ((|(4'b1 & (~reg_be))))) |
120 (addr_hit[119] & ((|(4'b1 & (~reg_be))))) |
121 (addr_hit[120] & ((|(4'b1 & (~reg_be))))) |
122 (addr_hit[121] & ((|(4'b1 & (~reg_be))))) |
123 (addr_hit[122] & ((|(4'b1 & (~reg_be))))) |
124 (addr_hit[123] & ((|(4'b1 & (~reg_be))))) |
125 (addr_hit[124] & ((|(4'b1 & (~reg_be))))) |
126 (addr_hit[125] & ((|(4'b1 & (~reg_be))))) |
127 (addr_hit[126] & ((|(4'b1 & (~reg_be))))) |
128 (addr_hit[127] & ((|(4'b1 & (~reg_be))))) |
129 (addr_hit[128] & ((|(4'b1 & (~reg_be))))) |
130 (addr_hit[129] & ((|(4'b1 & (~reg_be))))) |
131 (addr_hit[130] & ((|(4'b1 & (~reg_be))))) |
132 (addr_hit[131] & ((|(4'b1 & (~reg_be))))) |
133 (addr_hit[132] & ((|(4'b1 & (~reg_be))))) |
134 (addr_hit[133] & ((|(4'b1 & (~reg_be))))) |
135 (addr_hit[134] & ((|(4'b1 & (~reg_be))))) |
136 (addr_hit[135] & ((|(4'b1 & (~reg_be))))) |
137 (addr_hit[136] & ((|(4'b1 & (~reg_be))))) |
138 (addr_hit[137] & ((|(4'b1 & (~reg_be))))) |
139 (addr_hit[138] & ((|(4'b1 & (~reg_be))))) |
140 (addr_hit[139] & ((|(4'b1 & (~reg_be))))) |
141 (addr_hit[140] & ((|(4'b1 & (~reg_be))))) |
142 (addr_hit[141] & ((|(4'b1 & (~reg_be))))) |
143 (addr_hit[142] & ((|(4'b1 & (~reg_be))))) |
144 (addr_hit[143] & ((|(4'b1 & (~reg_be))))) |
145 (addr_hit[144] & ((|(4'b1 & (~reg_be))))) |
146 (addr_hit[145] & ((|(4'b1 & (~reg_be))))) |
147 (addr_hit[146] & ((|(4'b1 & (~reg_be))))) |
148 (addr_hit[147] & ((|(4'b1 & (~reg_be))))) |
149 (addr_hit[148] & ((|(4'b1 & (~reg_be))))) |
150 (addr_hit[149] & ((|(4'b1 & (~reg_be))))) |
151 (addr_hit[150] & ((|(4'b1 & (~reg_be))))) |
152 (addr_hit[151] & ((|(4'b1 & (~reg_be))))) |
153 (addr_hit[152] & ((|(4'b1 & (~reg_be))))) |
154 (addr_hit[153] & ((|(4'b1 & (~reg_be))))) |
155 (addr_hit[154] & ((|(4'b1 & (~reg_be))))) |
156 (addr_hit[155] & ((|(4'b1 & (~reg_be))))) |
157 (addr_hit[156] & ((|(4'b1 & (~reg_be))))) |
158 (addr_hit[157] & ((|(4'b1 & (~reg_be))))) |
159 (addr_hit[158] & ((|(4'b1 & (~reg_be))))) |
160 (addr_hit[159] & ((|(4'b1 & (~reg_be))))) |
161 (addr_hit[160] & ((|(4'b1 & (~reg_be))))) |
162 (addr_hit[161] & ((|(4'b1 & (~reg_be))))) |
163 (addr_hit[162] & ((|(4'b1 & (~reg_be))))) |
164 (addr_hit[163] & ((|(4'b1 & (~reg_be))))) |
165 (addr_hit[164] & ((|(4'b1 & (~reg_be))))) |
166 (addr_hit[165] & ((|(4'b1 & (~reg_be))))) |
167 (addr_hit[166] & ((|(4'b1 & (~reg_be))))) |
168 (addr_hit[167] & ((|(4'b1 & (~reg_be))))) |
169 (addr_hit[168] & ((|(4'b1 & (~reg_be))))) |
170 (addr_hit[169] & ((|(4'b1 & (~reg_be))))) |
171 (addr_hit[170] & ((|(4'b1 & (~reg_be))))) |
172 (addr_hit[171] & ((|(4'b1 & (~reg_be))))) |
173 (addr_hit[172] & ((|(4'b1 & (~reg_be))))) |
174 (addr_hit[173] & ((|(4'b1 & (~reg_be))))) |
175 (addr_hit[174] & ((|(4'b1 & (~reg_be))))) |
176 (addr_hit[175] & ((|(4'b1 & (~reg_be))))) |
177 (addr_hit[176] & ((|(4'b1 & (~reg_be))))) |
178 (addr_hit[177] & ((|(4'b1 & (~reg_be))))) |
179 (addr_hit[178] & ((|(4'b1 & (~reg_be))))) |
180 (addr_hit[179] & ((|(4'b1 & (~reg_be))))) |
181 (addr_hit[180] & ((|(4'b1 & (~reg_be))))) |
182 (addr_hit[181] & ((|(4'b1 & (~reg_be))))) |
183 (addr_hit[182] & ((|(4'b1 & (~reg_be))))) |
184 (addr_hit[183] & ((|(4'b1 & (~reg_be))))) |
185 (addr_hit[184] & ((|(4'b1 & (~reg_be))))) |
186 (addr_hit[185] & ((|(4'b1 & (~reg_be))))) |
187 (addr_hit[186] & ((|(4'b1111 & (~reg_be))))) |
188 (addr_hit[187] & ((|(4'b1111 & (~reg_be))))) |
189 (addr_hit[188] & ((|(4'b1111 & (~reg_be))))) |
190 (addr_hit[189] & ((|(4'b1111 & (~reg_be))))) |
191 (addr_hit[190] & ((|(4'b1111 & (~reg_be))))) |
192 (addr_hit[191] & ((|(4'b1111 & (~reg_be))))) |
193 (addr_hit[192] & ((|(4'b1111 & (~reg_be))))) |
194 (addr_hit[193] & ((|(4'b1111 & (~reg_be))))) |
195 (addr_hit[194] & ((|(4'b1111 & (~reg_be))))) |
196 (addr_hit[195] & ((|(4'b1111 & (~reg_be))))) |
197 (addr_hit[196] & ((|(4'b1111 & (~reg_be))))) |
198 (addr_hit[197] & ((|(4'b1111 & (~reg_be))))) |
199 (addr_hit[198] & ((|(4'b1 & (~reg_be))))) |
200 (addr_hit[199] & ((|(4'b1 & (~reg_be))))) |
201 (addr_hit[200] & ((|(4'b1 & (~reg_be))))) |
202 (addr_hit[201] & ((|(4'b1 & (~reg_be))))))
| Sensitive Expression == 1 | Status | Tests |
|---|---|---|
| ALL ZEROS | Covered | T3,T4,T91 |
| 202 (addr_hit[201] & ((|(4... | Covered | T76,T393,T552 |
| 201 (addr_hit[200] & ((|(4... | Covered | T76,T393,T552 |
| 200 (addr_hit[199] & ((|(4... | Covered | T76,T393,T552 |
| 199 (addr_hit[198] & ((|(4... | Covered | T76,T152,T552 |
| 198 (addr_hit[197] & ((|(4... | Covered | T76,T152,T393 |
| 197 (addr_hit[196] & ((|(4... | Covered | T76,T152,T393 |
| 196 (addr_hit[195] & ((|(4... | Covered | T76,T152,T393 |
| 195 (addr_hit[194] & ((|(4... | Covered | T76,T152,T393 |
| 194 (addr_hit[193] & ((|(4... | Covered | T76,T152,T393 |
| 193 (addr_hit[192] & ((|(4... | Covered | T76,T152,T393 |
| 192 (addr_hit[191] & ((|(4... | Covered | T76,T393,T552 |
| 191 (addr_hit[190] & ((|(4... | Covered | T76,T393,T552 |
| 190 (addr_hit[189] & ((|(4... | Covered | T76,T552,T144 |
| 189 (addr_hit[188] & ((|(4... | Covered | T76,T393,T552 |
| 188 (addr_hit[187] & ((|(4... | Covered | T76,T393,T552 |
| 187 (addr_hit[186] & ((|(4... | Covered | T76,T552,T579 |
| 186 (addr_hit[185] & ((|(4... | Covered | T76,T552,T144 |
| 185 (addr_hit[184] & ((|(4... | Covered | T76,T552,T579 |
| 184 (addr_hit[183] & ((|(4... | Covered | T76,T393,T552 |
| 183 (addr_hit[182] & ((|(4... | Covered | T76,T152,T393 |
| 182 (addr_hit[181] & ((|(4... | Covered | T76,T393,T552 |
| 181 (addr_hit[180] & ((|(4... | Covered | T76,T152,T552 |
| 180 (addr_hit[179] & ((|(4... | Covered | T76,T393,T552 |
| 179 (addr_hit[178] & ((|(4... | Covered | T76,T393,T552 |
| 178 (addr_hit[177] & ((|(4... | Covered | T76,T393,T552 |
| 177 (addr_hit[176] & ((|(4... | Covered | T152,T393,T552 |
| 176 (addr_hit[175] & ((|(4... | Covered | T76,T393,T552 |
| 175 (addr_hit[174] & ((|(4... | Covered | T76,T393,T552 |
| 174 (addr_hit[173] & ((|(4... | Covered | T76,T393,T552 |
| 173 (addr_hit[172] & ((|(4... | Covered | T76,T152,T393 |
| 172 (addr_hit[171] & ((|(4... | Covered | T76,T393,T552 |
| 171 (addr_hit[170] & ((|(4... | Covered | T76,T152,T393 |
| 170 (addr_hit[169] & ((|(4... | Covered | T76,T393,T552 |
| 169 (addr_hit[168] & ((|(4... | Covered | T76,T152,T552 |
| 168 (addr_hit[167] & ((|(4... | Covered | T76,T152,T393 |
| 167 (addr_hit[166] & ((|(4... | Covered | T76,T393,T552 |
| 166 (addr_hit[165] & ((|(4... | Covered | T76,T393,T552 |
| 165 (addr_hit[164] & ((|(4... | Covered | T76,T152,T552 |
| 164 (addr_hit[163] & ((|(4... | Covered | T76,T393,T552 |
| 163 (addr_hit[162] & ((|(4... | Covered | T76,T152,T552 |
| 162 (addr_hit[161] & ((|(4... | Covered | T76,T393,T552 |
| 161 (addr_hit[160] & ((|(4... | Covered | T76,T152,T393 |
| 160 (addr_hit[159] & ((|(4... | Covered | T76,T393,T552 |
| 159 (addr_hit[158] & ((|(4... | Covered | T76,T152,T552 |
| 158 (addr_hit[157] & ((|(4... | Covered | T76,T393,T552 |
| 157 (addr_hit[156] & ((|(4... | Covered | T76,T152,T393 |
| 156 (addr_hit[155] & ((|(4... | Covered | T76,T393,T552 |
| 155 (addr_hit[154] & ((|(4... | Covered | T76,T552,T144 |
| 154 (addr_hit[153] & ((|(4... | Covered | T76,T393,T552 |
| 153 (addr_hit[152] & ((|(4... | Covered | T76,T552,T144 |
| 152 (addr_hit[151] & ((|(4... | Covered | T76,T552,T144 |
| 151 (addr_hit[150] & ((|(4... | Covered | T76,T393,T552 |
| 150 (addr_hit[149] & ((|(4... | Covered | T76,T393,T552 |
| 149 (addr_hit[148] & ((|(4... | Covered | T76,T393,T552 |
| 148 (addr_hit[147] & ((|(4... | Covered | T76,T152,T393 |
| 147 (addr_hit[146] & ((|(4... | Covered | T76,T393,T552 |
| 146 (addr_hit[145] & ((|(4... | Covered | T76,T393,T552 |
| 145 (addr_hit[144] & ((|(4... | Covered | T76,T552,T579 |
| 144 (addr_hit[143] & ((|(4... | Covered | T76,T393,T552 |
| 143 (addr_hit[142] & ((|(4... | Covered | T76,T393,T552 |
| 142 (addr_hit[141] & ((|(4... | Covered | T76,T393,T552 |
| 141 (addr_hit[140] & ((|(4... | Covered | T76,T393,T552 |
| 140 (addr_hit[139] & ((|(4... | Covered | T76,T393,T552 |
| 139 (addr_hit[138] & ((|(4... | Covered | T76,T393,T552 |
| 138 (addr_hit[137] & ((|(4... | Covered | T76,T552,T579 |
| 137 (addr_hit[136] & ((|(4... | Covered | T76,T393,T552 |
| 136 (addr_hit[135] & ((|(4... | Covered | T552,T144,T579 |
| 135 (addr_hit[134] & ((|(4... | Covered | T76,T552,T144 |
| 134 (addr_hit[133] & ((|(4... | Covered | T76,T393,T552 |
| 133 (addr_hit[132] & ((|(4... | Covered | T76,T393,T552 |
| 132 (addr_hit[131] & ((|(4... | Covered | T76,T393,T552 |
| 131 (addr_hit[130] & ((|(4... | Covered | T76,T393,T552 |
| 130 (addr_hit[129] & ((|(4... | Covered | T76,T393,T552 |
| 129 (addr_hit[128] & ((|(4... | Covered | T76,T393,T552 |
| 128 (addr_hit[127] & ((|(4... | Covered | T76,T393,T552 |
| 127 (addr_hit[126] & ((|(4... | Covered | T76,T393,T552 |
| 126 (addr_hit[125] & ((|(4... | Covered | T393,T552,T144 |
| 125 (addr_hit[124] & ((|(4... | Covered | T76,T393,T552 |
| 124 (addr_hit[123] & ((|(4... | Covered | T76,T393,T552 |
| 123 (addr_hit[122] & ((|(4... | Covered | T76,T393,T552 |
| 122 (addr_hit[121] & ((|(4... | Covered | T76,T393,T552 |
| 121 (addr_hit[120] & ((|(4... | Covered | T76,T152,T552 |
| 120 (addr_hit[119] & ((|(4... | Covered | T76,T152,T393 |
| 119 (addr_hit[118] & ((|(4... | Covered | T76,T393,T552 |
| 118 (addr_hit[117] & ((|(4... | Covered | T76,T393,T552 |
| 117 (addr_hit[116] & ((|(4... | Covered | T76,T152,T393 |
| 116 (addr_hit[115] & ((|(4... | Covered | T76,T393,T552 |
| 115 (addr_hit[114] & ((|(4... | Covered | T76,T152,T552 |
| 114 (addr_hit[113] & ((|(4... | Covered | T76,T393,T552 |
| 113 (addr_hit[112] & ((|(4... | Covered | T76,T393,T552 |
| 112 (addr_hit[111] & ((|(4... | Covered | T76,T152,T393 |
| 111 (addr_hit[110] & ((|(4... | Covered | T76,T393,T552 |
| 110 (addr_hit[109] & ((|(4... | Covered | T76,T393,T552 |
| 109 (addr_hit[108] & ((|(4... | Covered | T393,T552,T579 |
| 108 (addr_hit[107] & ((|(4... | Covered | T76,T393,T552 |
| 107 (addr_hit[106] & ((|(4... | Covered | T393,T552,T579 |
| 106 (addr_hit[105] & ((|(4... | Covered | T76,T552,T144 |
| 105 (addr_hit[104] & ((|(4... | Covered | T76,T393,T552 |
| 104 (addr_hit[103] & ((|(4... | Covered | T76,T393,T552 |
| 103 (addr_hit[102] & ((|(4... | Covered | T76,T552,T579 |
| 102 (addr_hit[101] & ((|(4... | Covered | T76,T552,T579 |
| 101 (addr_hit[100] & ((|(4... | Covered | T76,T393,T552 |
| 100 (addr_hit[99] & ((|(4'... | Covered | T76,T552,T144 |
| 99 (addr_hit[98] & ((|(4'... | Covered | T76,T393,T552 |
| 98 (addr_hit[97] & ((|(4'... | Covered | T76,T393,T552 |
| 97 (addr_hit[96] & ((|(4'... | Covered | T76,T393,T552 |
| 96 (addr_hit[95] & ((|(4'... | Covered | T76,T393,T552 |
| 95 (addr_hit[94] & ((|(4'... | Covered | T76,T393,T552 |
| 94 (addr_hit[93] & ((|(4'... | Covered | T152,T393,T552 |
| 93 (addr_hit[92] & ((|(4'... | Covered | T76,T152,T393 |
| 92 (addr_hit[91] & ((|(4'... | Covered | T76,T393,T552 |
| 91 (addr_hit[90] & ((|(4'... | Covered | T76,T393,T552 |
| 90 (addr_hit[89] & ((|(4'... | Covered | T76,T393,T552 |
| 89 (addr_hit[88] & ((|(4'... | Covered | T76,T152,T393 |
| 88 (addr_hit[87] & ((|(4'... | Covered | T76,T393,T552 |
| 87 (addr_hit[86] & ((|(4'... | Covered | T76,T552,T579 |
| 86 (addr_hit[85] & ((|(4'... | Covered | T76,T152,T393 |
| 85 (addr_hit[84] & ((|(4'... | Covered | T393,T552,T579 |
| 84 (addr_hit[83] & ((|(4'... | Covered | T76,T393,T552 |
| 83 (addr_hit[82] & ((|(4'... | Covered | T76,T393,T552 |
| 82 (addr_hit[81] & ((|(4'... | Covered | T76,T393,T552 |
| 81 (addr_hit[80] & ((|(4'... | Covered | T76,T393,T552 |
| 80 (addr_hit[79] & ((|(4'... | Covered | T76,T393,T552 |
| 79 (addr_hit[78] & ((|(4'... | Covered | T76,T152,T552 |
| 78 (addr_hit[77] & ((|(4'... | Covered | T76,T393,T552 |
| 77 (addr_hit[76] & ((|(4'... | Covered | T76,T393,T552 |
| 76 (addr_hit[75] & ((|(4'... | Covered | T76,T152,T393 |
| 75 (addr_hit[74] & ((|(4'... | Covered | T76,T393,T552 |
| 74 (addr_hit[73] & ((|(4'... | Covered | T76,T393,T552 |
| 73 (addr_hit[72] & ((|(4'... | Covered | T76,T552,T579 |
| 72 (addr_hit[71] & ((|(4'... | Covered | T76,T393,T552 |
| 71 (addr_hit[70] & ((|(4'... | Covered | T76,T152,T393 |
| 70 (addr_hit[69] & ((|(4'... | Covered | T76,T393,T552 |
| 69 (addr_hit[68] & ((|(4'... | Covered | T76,T393,T552 |
| 68 (addr_hit[67] & ((|(4'... | Covered | T76,T152,T552 |
| 67 (addr_hit[66] & ((|(4'... | Covered | T76,T393,T552 |
| 66 (addr_hit[65] & ((|(4'... | Covered | T152,T393,T552 |
| 65 (addr_hit[64] & ((|(4'... | Covered | T76,T393,T552 |
| 64 (addr_hit[63] & ((|(4'... | Covered | T76,T152,T552 |
| 63 (addr_hit[62] & ((|(4'... | Covered | T76,T393,T552 |
| 62 (addr_hit[61] & ((|(4'... | Covered | T76,T393,T552 |
| 61 (addr_hit[60] & ((|(4'... | Covered | T76,T152,T552 |
| 60 (addr_hit[59] & ((|(4'... | Covered | T76,T393,T552 |
| 59 (addr_hit[58] & ((|(4'... | Covered | T76,T393,T552 |
| 58 (addr_hit[57] & ((|(4'... | Covered | T76,T552,T579 |
| 57 (addr_hit[56] & ((|(4'... | Covered | T76,T152,T393 |
| 56 (addr_hit[55] & ((|(4'... | Covered | T76,T393,T552 |
| 55 (addr_hit[54] & ((|(4'... | Covered | T76,T393,T552 |
| 54 (addr_hit[53] & ((|(4'... | Covered | T76,T393,T552 |
| 53 (addr_hit[52] & ((|(4'... | Covered | T76,T393,T552 |
| 52 (addr_hit[51] & ((|(4'... | Covered | T76,T393,T552 |
| 51 (addr_hit[50] & ((|(4'... | Covered | T76,T152,T393 |
| 50 (addr_hit[49] & ((|(4'... | Covered | T76,T393,T552 |
| 49 (addr_hit[48] & ((|(4'... | Covered | T76,T552,T579 |
| 48 (addr_hit[47] & ((|(4'... | Covered | T76,T393,T552 |
| 47 (addr_hit[46] & ((|(4'... | Covered | T76,T152,T393 |
| 46 (addr_hit[45] & ((|(4'... | Covered | T76,T393,T552 |
| 45 (addr_hit[44] & ((|(4'... | Covered | T76,T393,T552 |
| 44 (addr_hit[43] & ((|(4'... | Covered | T76,T552,T579 |
| 43 (addr_hit[42] & ((|(4'... | Covered | T76,T393,T552 |
| 42 (addr_hit[41] & ((|(4'... | Covered | T552,T579,T568 |
| 41 (addr_hit[40] & ((|(4'... | Covered | T76,T152,T552 |
| 40 (addr_hit[39] & ((|(4'... | Covered | T76,T552,T579 |
| 39 (addr_hit[38] & ((|(4'... | Covered | T76,T393,T552 |
| 38 (addr_hit[37] & ((|(4'... | Covered | T76,T393,T552 |
| 37 (addr_hit[36] & ((|(4'... | Covered | T76,T393,T552 |
| 36 (addr_hit[35] & ((|(4'... | Covered | T76,T152,T393 |
| 35 (addr_hit[34] & ((|(4'... | Covered | T76,T152,T393 |
| 34 (addr_hit[33] & ((|(4'... | Covered | T76,T393,T552 |
| 33 (addr_hit[32] & ((|(4'... | Covered | T76,T552,T579 |
| 32 (addr_hit[31] & ((|(4'... | Covered | T76,T393,T552 |
| 31 (addr_hit[30] & ((|(4'... | Covered | T76,T393,T552 |
| 30 (addr_hit[29] & ((|(4'... | Covered | T76,T393,T552 |
| 29 (addr_hit[28] & ((|(4'... | Covered | T76,T393,T552 |
| 28 (addr_hit[27] & ((|(4'... | Covered | T76,T393,T552 |
| 27 (addr_hit[26] & ((|(4'... | Covered | T76,T393,T552 |
| 26 (addr_hit[25] & ((|(4'... | Covered | T76,T393,T552 |
| 25 (addr_hit[24] & ((|(4'... | Covered | T76,T393,T552 |
| 24 (addr_hit[23] & ((|(4'... | Covered | T76,T393,T552 |
| 23 (addr_hit[22] & ((|(4'... | Covered | T76,T393,T552 |
| 22 (addr_hit[21] & ((|(4'... | Covered | T76,T393,T552 |
| 21 (addr_hit[20] & ((|(4'... | Covered | T76,T152,T552 |
| 20 (addr_hit[19] & ((|(4'... | Covered | T76,T393,T552 |
| 19 (addr_hit[18] & ((|(4'... | Covered | T76,T393,T552 |
| 18 (addr_hit[17] & ((|(4'... | Covered | T552,T144,T579 |
| 17 (addr_hit[16] & ((|(4'... | Covered | T76,T393,T552 |
| 16 (addr_hit[15] & ((|(4'... | Covered | T76,T393,T552 |
| 15 (addr_hit[14] & ((|(4'... | Covered | T76,T393,T552 |
| 14 (addr_hit[13] & ((|(4'... | Covered | T76,T393,T552 |
| 13 (addr_hit[12] & ((|(4'... | Covered | T76,T393,T552 |
| 12 (addr_hit[11] & ((|(4'... | Covered | T76,T552,T144 |
| 11 (addr_hit[10] & ((|(4'... | Covered | T552,T579,T568 |
| 10 (addr_hit[9] & ((|(4'b... | Covered | T76,T393,T552 |
| 9 (addr_hit[8] & ((|(4'b... | Covered | T76,T393,T552 |
| 8 (addr_hit[7] & ((|(4'b... | Covered | T76,T552,T579 |
| 7 (addr_hit[6] & ((|(4'b... | Covered | T76,T393,T552 |
| 6 (addr_hit[5] & ((|(4'b... | Covered | T76,T152,T552 |
| 5 (addr_hit[4] & ((|(4'b... | Covered | T76,T393,T552 |
| 4 (addr_hit[3] & ((|(4'b... | Covered | T152,T393,T552 |
| 3 (addr_hit[2] & ((|(4'b... | Covered | T76,T393,T579 |
| 2 (addr_hit[1] & ((|(4'b... | Covered | T76,T552,T144 |
| 1 (addr_hit[0] & ((|(4'b... | Covered | T3,T4,T91 |
LINE 16856
SUB-EXPRESSION (addr_hit[0] & ((|(4'b1 & (~reg_be)))))
-----1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|---|---|---|
| 0 | 1 | Covered | T76,T77,T82 |
| 1 | 0 | Covered | T257,T258,T259 |
| 1 | 1 | Covered | T3,T4,T91 |
LINE 16856
SUB-EXPRESSION (addr_hit[1] & ((|(4'b1 & (~reg_be)))))
-----1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|---|---|---|
| 0 | 1 | Covered | T3,T4,T91 |
| 1 | 0 | Covered | T95,T262,T307 |
| 1 | 1 | Covered | T76,T552,T144 |
LINE 16856
SUB-EXPRESSION (addr_hit[2] & ((|(4'b1 & (~reg_be)))))
-----1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|---|---|---|
| 0 | 1 | Covered | T3,T4,T91 |
| 1 | 0 | Covered | T95,T262,T307 |
| 1 | 1 | Covered | T76,T393,T579 |
LINE 16856
SUB-EXPRESSION (addr_hit[3] & ((|(4'b1 & (~reg_be)))))
-----1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|---|---|---|
| 0 | 1 | Covered | T3,T4,T91 |
| 1 | 0 | Covered | T95,T262,T307 |
| 1 | 1 | Covered | T152,T393,T552 |
LINE 16856
SUB-EXPRESSION (addr_hit[4] & ((|(4'b1 & (~reg_be)))))
-----1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|---|---|---|
| 0 | 1 | Covered | T3,T4,T91 |
| 1 | 0 | Covered | T95,T262,T307 |
| 1 | 1 | Covered | T76,T393,T552 |
LINE 16856
SUB-EXPRESSION (addr_hit[5] & ((|(4'b1 & (~reg_be)))))
-----1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|---|---|---|
| 0 | 1 | Covered | T3,T4,T91 |
| 1 | 0 | Covered | T95,T262,T307 |
| 1 | 1 | Covered | T76,T152,T552 |
LINE 16856
SUB-EXPRESSION (addr_hit[6] & ((|(4'b1 & (~reg_be)))))
-----1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|---|---|---|
| 0 | 1 | Covered | T3,T4,T91 |
| 1 | 0 | Covered | T95,T262,T307 |
| 1 | 1 | Covered | T76,T393,T552 |
LINE 16856
SUB-EXPRESSION (addr_hit[7] & ((|(4'b1 & (~reg_be)))))
-----1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|---|---|---|
| 0 | 1 | Covered | T3,T4,T91 |
| 1 | 0 | Covered | T95,T262,T307 |
| 1 | 1 | Covered | T76,T552,T579 |
LINE 16856
SUB-EXPRESSION (addr_hit[8] & ((|(4'b1 & (~reg_be)))))
-----1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|---|---|---|
| 0 | 1 | Covered | T3,T4,T91 |
| 1 | 0 | Covered | T95,T262,T307 |
| 1 | 1 | Covered | T76,T393,T552 |
LINE 16856
SUB-EXPRESSION (addr_hit[9] & ((|(4'b1 & (~reg_be)))))
-----1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|---|---|---|
| 0 | 1 | Covered | T3,T4,T91 |
| 1 | 0 | Covered | T95,T262,T307 |
| 1 | 1 | Covered | T76,T393,T552 |
LINE 16856
SUB-EXPRESSION (addr_hit[10] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|---|---|---|
| 0 | 1 | Covered | T3,T4,T91 |
| 1 | 0 | Covered | T91,T262,T321 |
| 1 | 1 | Covered | T552,T579,T568 |
LINE 16856
SUB-EXPRESSION (addr_hit[11] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|---|---|---|
| 0 | 1 | Covered | T3,T4,T91 |
| 1 | 0 | Covered | T91,T262,T321 |
| 1 | 1 | Covered | T76,T552,T144 |
LINE 16856
SUB-EXPRESSION (addr_hit[12] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|---|---|---|
| 0 | 1 | Covered | T3,T4,T91 |
| 1 | 0 | Covered | T91,T262,T321 |
| 1 | 1 | Covered | T76,T393,T552 |
LINE 16856
SUB-EXPRESSION (addr_hit[13] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|---|---|---|
| 0 | 1 | Covered | T3,T4,T91 |
| 1 | 0 | Covered | T91,T262,T321 |
| 1 | 1 | Covered | T76,T393,T552 |
LINE 16856
SUB-EXPRESSION (addr_hit[14] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|---|---|---|
| 0 | 1 | Covered | T3,T4,T91 |
| 1 | 0 | Covered | T91,T262,T321 |
| 1 | 1 | Covered | T76,T393,T552 |
LINE 16856
SUB-EXPRESSION (addr_hit[15] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|---|---|---|
| 0 | 1 | Covered | T3,T4,T91 |
| 1 | 0 | Covered | T91,T262,T321 |
| 1 | 1 | Covered | T76,T393,T552 |
LINE 16856
SUB-EXPRESSION (addr_hit[16] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|---|---|---|
| 0 | 1 | Covered | T3,T4,T91 |
| 1 | 0 | Covered | T91,T262,T321 |
| 1 | 1 | Covered | T76,T393,T552 |
LINE 16856
SUB-EXPRESSION (addr_hit[17] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|---|---|---|
| 0 | 1 | Covered | T3,T4,T91 |
| 1 | 0 | Covered | T91,T262,T321 |
| 1 | 1 | Covered | T552,T144,T579 |
LINE 16856
SUB-EXPRESSION (addr_hit[18] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|---|---|---|
| 0 | 1 | Covered | T3,T4,T91 |
| 1 | 0 | Covered | T91,T262,T321 |
| 1 | 1 | Covered | T76,T393,T552 |
LINE 16856
SUB-EXPRESSION (addr_hit[19] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|---|---|---|
| 0 | 1 | Covered | T3,T4,T91 |
| 1 | 0 | Covered | T262,T154,T321 |
| 1 | 1 | Covered | T76,T393,T552 |
LINE 16856
SUB-EXPRESSION (addr_hit[20] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|---|---|---|
| 0 | 1 | Covered | T3,T4,T91 |
| 1 | 0 | Covered | T262,T154,T321 |
| 1 | 1 | Covered | T76,T152,T552 |
LINE 16856
SUB-EXPRESSION (addr_hit[21] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|---|---|---|
| 0 | 1 | Covered | T3,T4,T91 |
| 1 | 0 | Covered | T262,T154,T321 |
| 1 | 1 | Covered | T76,T393,T552 |
LINE 16856
SUB-EXPRESSION (addr_hit[22] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|---|---|---|
| 0 | 1 | Covered | T3,T4,T91 |
| 1 | 0 | Covered | T262,T154,T321 |
| 1 | 1 | Covered | T76,T393,T552 |
LINE 16856
SUB-EXPRESSION (addr_hit[23] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|---|---|---|
| 0 | 1 | Covered | T3,T4,T91 |
| 1 | 0 | Covered | T262,T154,T321 |
| 1 | 1 | Covered | T76,T393,T552 |
LINE 16856
SUB-EXPRESSION (addr_hit[24] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|---|---|---|
| 0 | 1 | Covered | T3,T4,T91 |
| 1 | 0 | Covered | T262,T154,T321 |
| 1 | 1 | Covered | T76,T393,T552 |
LINE 16856
SUB-EXPRESSION (addr_hit[25] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|---|---|---|
| 0 | 1 | Covered | T3,T4,T91 |
| 1 | 0 | Covered | T262,T154,T321 |
| 1 | 1 | Covered | T76,T393,T552 |
LINE 16856
SUB-EXPRESSION (addr_hit[26] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|---|---|---|
| 0 | 1 | Covered | T3,T4,T91 |
| 1 | 0 | Covered | T262,T154,T321 |
| 1 | 1 | Covered | T76,T393,T552 |
LINE 16856
SUB-EXPRESSION (addr_hit[27] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|---|---|---|
| 0 | 1 | Covered | T3,T4,T91 |
| 1 | 0 | Covered | T262,T154,T321 |
| 1 | 1 | Covered | T76,T393,T552 |
LINE 16856
SUB-EXPRESSION (addr_hit[28] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|---|---|---|
| 0 | 1 | Covered | T3,T4,T91 |
| 1 | 0 | Covered | T14,T262,T321 |
| 1 | 1 | Covered | T76,T393,T552 |
LINE 16856
SUB-EXPRESSION (addr_hit[29] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|---|---|---|
| 0 | 1 | Covered | T3,T4,T91 |
| 1 | 0 | Covered | T14,T262,T321 |
| 1 | 1 | Covered | T76,T393,T552 |
LINE 16856
SUB-EXPRESSION (addr_hit[30] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|---|---|---|
| 0 | 1 | Covered | T3,T4,T91 |
| 1 | 0 | Covered | T14,T262,T321 |
| 1 | 1 | Covered | T76,T393,T552 |
LINE 16856
SUB-EXPRESSION (addr_hit[31] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|---|---|---|
| 0 | 1 | Covered | T3,T4,T91 |
| 1 | 0 | Covered | T14,T262,T321 |
| 1 | 1 | Covered | T76,T393,T552 |
LINE 16856
SUB-EXPRESSION (addr_hit[32] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|---|---|---|
| 0 | 1 | Covered | T3,T4,T91 |
| 1 | 0 | Covered | T14,T262,T321 |
| 1 | 1 | Covered | T76,T552,T579 |
LINE 16856
SUB-EXPRESSION (addr_hit[33] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|---|---|---|
| 0 | 1 | Covered | T3,T4,T91 |
| 1 | 0 | Covered | T14,T262,T321 |
| 1 | 1 | Covered | T76,T393,T552 |
LINE 16856
SUB-EXPRESSION (addr_hit[34] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|---|---|---|
| 0 | 1 | Covered | T3,T4,T91 |
| 1 | 0 | Covered | T14,T262,T321 |
| 1 | 1 | Covered | T76,T152,T393 |
LINE 16856
SUB-EXPRESSION (addr_hit[35] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|---|---|---|
| 0 | 1 | Covered | T3,T4,T91 |
| 1 | 0 | Covered | T14,T262,T321 |
| 1 | 1 | Covered | T76,T152,T393 |
LINE 16856
SUB-EXPRESSION (addr_hit[36] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|---|---|---|
| 0 | 1 | Covered | T3,T4,T91 |
| 1 | 0 | Covered | T14,T262,T321 |
| 1 | 1 | Covered | T76,T393,T552 |
LINE 16856
SUB-EXPRESSION (addr_hit[37] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|---|---|---|
| 0 | 1 | Covered | T3,T4,T91 |
| 1 | 0 | Covered | T262,T321,T16 |
| 1 | 1 | Covered | T76,T393,T552 |
LINE 16856
SUB-EXPRESSION (addr_hit[38] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|---|---|---|
| 0 | 1 | Covered | T3,T4,T91 |
| 1 | 0 | Covered | T262,T321,T16 |
| 1 | 1 | Covered | T76,T393,T552 |
LINE 16856
SUB-EXPRESSION (addr_hit[39] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|---|---|---|
| 0 | 1 | Covered | T3,T4,T91 |
| 1 | 0 | Covered | T262,T321,T16 |
| 1 | 1 | Covered | T76,T552,T579 |
LINE 16856
SUB-EXPRESSION (addr_hit[40] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|---|---|---|
| 0 | 1 | Covered | T3,T4,T91 |
| 1 | 0 | Covered | T262,T321,T16 |
| 1 | 1 | Covered | T76,T152,T552 |
LINE 16856
SUB-EXPRESSION (addr_hit[41] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|---|---|---|
| 0 | 1 | Covered | T3,T4,T91 |
| 1 | 0 | Covered | T262,T321,T16 |
| 1 | 1 | Covered | T552,T579,T568 |
LINE 16856
SUB-EXPRESSION (addr_hit[42] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|---|---|---|
| 0 | 1 | Covered | T3,T4,T91 |
| 1 | 0 | Covered | T262,T321,T16 |
| 1 | 1 | Covered | T76,T393,T552 |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |