Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.rom_ctrl__regs_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	154579	1			T79	2		T80	7		T81	30
values[2]	4044	1			T81	1		T137	9		T391	18
values[3]	1843	1			T391	3		T514	1		T629	2
values[4]	1406	1			T391	8		T514	1		T841	1
values[5]	1271	1			T391	7		T514	1		T841	1
values[6]	1206	1			T391	4		T514	1		T841	1
values[7]	1074	1			T391	8		T514	1		T841	1
values[8]	803	1			T391	2		T514	1		T841	1
values[9]	644	1			T391	1		T514	1		T841	1
values[10]	464	1			T391	4		T514	1		T841	1
values[11]	376	1			T391	11		T514	1		T841	1
values[12]	446	1			T391	8		T514	1		T841	1
values[13]	459	1			T391	4		T514	1		T841	1
values[14]	477	1			T391	3		T514	1		T841	1
values[15]	409	1			T391	4		T514	1		T841	1
values[16]	376	1			T391	3		T514	1		T841	1
values[17]	336	1			T391	4		T514	1		T841	1
values[18]	254	1			T391	6		T514	1		T841	1
values[19]	286	1			T391	16		T514	1		T841	1
values[20]	268	1			T391	18		T514	1		T841	1
values[21]	286	1			T391	31		T514	1		T841	1
values[22]	266	1			T391	25		T514	1		T841	1
values[23]	262	1			T391	6		T514	1		T841	1
values[24]	216	1			T391	4		T514	1		T841	1
values[25]	186	1			T391	6		T514	1		T841	1
values[26]	230	1			T391	4		T514	1		T841	1
values[27]	172	1			T391	2		T514	1		T841	1
values[28]	126	1			T391	2		T514	1		T841	1
values[29]	101	1			T391	6		T514	1		T841	1
values[30]	89	1			T391	4		T514	1		T841	1
values[31]	89	1			T514	1		T841	1		T846	1
values[32]	90	1			T514	1		T841	1		T846	1
values[33]	96	1			T514	1		T841	1		T846	1
values[34]	67	1			T514	1		T841	1		T846	1
values[35]	75	1			T514	1		T841	1		T846	1
values[36]	61	1			T514	1		T841	1		T846	1
values[37]	60	1			T514	1		T841	1		T846	1
values[38]	98	1			T514	2		T841	1		T846	1
values[39]	109	1			T514	1		T841	1		T846	1
values[40]	80	1			T514	1		T841	1		T846	1
values[41]	66	1			T514	1		T841	1		T846	1
values[42]	58	1			T514	1		T841	1		T846	1
values[43]	44	1			T514	1		T841	1		T846	1
values[44]	47	1			T514	1		T841	1		T846	1
values[45]	47	1			T514	1		T841	1		T846	1
values[46]	42	1			T514	1		T841	1		T846	1
values[47]	43	1			T514	1		T841	1		T846	1
values[48]	42	1			T514	1		T841	1		T846	1
values[49]	48	1			T514	1		T841	1		T846	1
values[50]	50	1			T514	1		T841	1		T846	1
values[51]	39	1			T514	1		T841	1		T846	1
values[52]	42	1			T514	1		T841	1		T846	1
values[53]	52	1			T514	1		T841	1		T846	1
values[54]	43	1			T514	1		T841	1		T846	1
values[55]	50	1			T514	1		T841	1		T846	1
values[56]	48	1			T514	1		T841	1		T846	1
values[57]	59	1			T514	1		T841	1		T846	1
values[58]	44	1			T514	1		T841	1		T846	1
values[59]	51	1			T514	1		T841	1		T846	1
values[60]	56	1			T514	1		T841	1		T846	1
values[61]	47	1			T514	1		T841	1		T846	1
values[62]	46	1			T514	1		T841	1		T846	1
values[63]	50	1			T514	1		T841	1		T846	2
values[64]	55	1			T514	1		T841	1		T846	1
values[65]	52	1			T514	1		T841	1		T846	1
values[66]	44	1			T514	1		T841	1		T846	1
values[67]	40	1			T514	1		T841	1		T846	1
values[68]	51	1			T514	1		T841	1		T846	1
values[69]	47	1			T514	1		T841	1		T846	1
values[70]	51	1			T514	1		T841	1		T846	1
values[71]	49	1			T514	1		T841	1		T846	1
values[72]	44	1			T514	1		T841	1		T846	1
values[73]	41	1			T514	1		T841	1		T846	1
values[74]	42	1			T514	1		T841	1		T846	1
values[75]	47	1			T514	1		T841	2		T846	1
values[76]	52	1			T514	1		T841	1		T846	1
values[77]	57	1			T514	1		T841	1		T846	1
values[78]	51	1			T514	1		T841	1		T846	1
values[79]	50	1			T514	1		T841	1		T846	1
values[80]	57	1			T514	1		T841	1		T846	1
values[81]	47	1			T514	1		T841	1		T846	1
values[82]	48	1			T514	1		T841	1		T846	1
values[83]	61	1			T514	1		T841	1		T846	1
values[84]	55	1			T514	1		T841	1		T846	1
values[85]	66	1			T514	1		T841	1		T846	1
values[86]	62	1			T514	1		T841	1		T846	1
values[87]	59	1			T514	1		T841	1		T846	1
values[88]	57	1			T514	1		T841	1		T846	1
values[89]	58	1			T514	1		T841	1		T846	1
values[90]	54	1			T514	1		T841	1		T846	1
values[91]	50	1			T514	1		T841	1		T846	1
values[92]	47	1			T514	1		T841	1		T846	1
values[93]	54	1			T514	2		T841	1		T846	1
values[94]	50	1			T514	1		T841	1		T846	1
values[95]	64	1			T514	1		T841	1		T846	1
values[96]	64	1			T514	1		T841	1		T846	1
values[97]	65	1			T514	1		T841	1		T846	1
values[98]	64	1			T514	4		T841	1		T846	1
values[99]	78	1			T514	4		T841	1		T846	1
values[100]	61	1			T514	1		T841	1		T846	1
values[101]	69	1			T514	6		T841	1		T846	1
values[102]	72	1			T514	1		T841	1		T846	1
values[103]	63	1			T514	2		T841	1		T846	1
values[104]	74	1			T514	2		T841	1		T846	1
values[105]	57	1			T514	1		T841	1		T846	1
values[106]	71	1			T514	1		T841	1		T846	1
values[107]	64	1			T514	1		T841	1		T846	1
values[108]	67	1			T514	1		T841	1		T846	1
values[109]	77	1			T514	2		T841	1		T846	1
values[110]	87	1			T514	1		T841	3		T846	1
values[111]	74	1			T514	2		T841	1		T846	1
values[112]	85	1			T514	1		T841	1		T846	1
values[113]	69	1			T514	1		T841	3		T846	1
values[114]	83	1			T514	2		T841	1		T846	1
values[115]	68	1			T514	4		T841	2		T846	1
values[116]	93	1			T514	4		T841	1		T846	1
values[117]	97	1			T514	2		T841	2		T846	1
values[118]	79	1			T514	3		T841	5		T846	1
values[119]	72	1			T514	1		T841	4		T846	1
values[120]	100	1			T514	4		T841	5		T846	3
values[121]	102	1			T514	2		T841	5		T846	3
values[122]	99	1			T514	1		T841	1		T846	3
values[123]	140	1			T514	2		T841	2		T846	3
values[124]	205	1			T514	2		T841	1		T846	2
values[125]	397	1			T514	1		T841	3		T846	1
values[126]	849	1			T514	24		T841	13		T846	31
values[127]	2844	1			T514	121		T841	96		T846	158
values[128]	4923	1			T514	230		T841	190		T846	257