Total Coverage Summary 

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.09	95.39	93.88	95.50		94.82	97.35	99.58

Total tests in report: 2935

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Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
39.71	39.71	43.80	43.80	44.05	44.05	31.05	31.05			57.51	57.51	58.74	58.74	3.14	3.14	/workspace/coverage/default/2.chip_sw_alert_test.1308471732
49.39	9.67	49.72	5.92	60.48	16.43	32.75	1.70			67.98	10.47	81.82	23.08	3.57	0.43	/workspace/coverage/cover_reg_top/11.chip_csr_rw.2972077645
55.35	5.96	59.63	9.91	61.36	0.88	34.32	1.56			68.17	0.19	81.82	0.00	26.80	23.23	/workspace/coverage/cover_reg_top/27.xbar_access_same_device_slow_rsp.3606597919
60.41	5.07	71.16	11.54	68.74	7.38	35.65	1.33			78.32	10.15	81.82	0.00	26.80	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_20.267162680
64.05	3.64	71.16	0.00	69.11	0.37	35.65	0.00			78.32	0.00	81.82	0.00	48.27	21.47	/workspace/coverage/cover_reg_top/37.xbar_access_same_device_slow_rsp.1454479348
67.20	3.15	76.48	5.31	73.13	4.02	39.21	3.56			80.11	1.79	86.01	4.20	48.27	0.00	/workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.653383327
69.96	2.76	79.06	2.58	74.68	1.55	48.60	9.39			82.26	2.15	86.89	0.87	48.28	0.01	/workspace/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.4147199232
72.46	2.50	82.40	3.34	77.19	2.51	52.19	3.60			84.59	2.33	90.03	3.15	48.33	0.05	/workspace/coverage/default/2.chip_jtag_csr_rw.2703723971
74.94	2.48	82.40	0.00	77.19	0.00	67.08	14.89			84.59	0.00	90.03	0.00	48.33	0.00	/workspace/coverage/default/2.chip_sw_keymgr_sideload_otbn.1868547150
77.26	2.32	82.40	0.00	77.19	0.00	67.08	0.00			84.59	0.00	90.03	0.00	62.25	13.92	/workspace/coverage/cover_reg_top/68.xbar_access_same_device_slow_rsp.3821716671
79.17	1.92	82.40	0.01	77.96	0.77	70.20	3.12			84.66	0.06	90.03	0.00	69.78	7.53	/workspace/coverage/cover_reg_top/26.xbar_stress_all_with_reset_error.4151252029
80.91	1.74	82.40	0.00	77.96	0.01	70.20	0.00			84.66	0.00	90.03	0.00	80.21	10.43	/workspace/coverage/cover_reg_top/29.xbar_access_same_device_slow_rsp.2139555498
82.54	1.63	82.69	0.29	78.11	0.15	79.01	8.80			84.84	0.18	90.38	0.35	80.21	0.00	/workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.974208213
83.99	1.45	85.49	2.80	79.47	1.36	81.57	2.56			85.75	0.92	91.43	1.05	80.21	0.00	/workspace/coverage/default/2.chip_sw_power_virus.1832713075
85.25	1.26	85.49	0.00	79.49	0.01	81.57	0.00			85.75	0.00	91.43	0.00	87.76	7.54	/workspace/coverage/cover_reg_top/86.xbar_access_same_device_slow_rsp.1630408630
86.45	1.20	87.18	1.69	80.67	1.19	84.64	3.07			86.83	1.08	91.61	0.17	87.76	0.00	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod.412737385
87.64	1.19	89.37	2.19	82.70	2.02	85.13	0.49			89.27	2.43	91.61	0.00	87.76	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_0.612030182
88.53	0.89	90.54	1.17	84.50	1.80	85.28	0.15			91.51	2.24	91.61	0.00	87.76	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.3280785421
89.29	0.76	90.87	0.32	84.67	0.17	85.29	0.01			91.69	0.19	95.45	3.85	87.76	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.3079740769
90.04	0.75	90.87	0.00	84.79	0.12	85.29	0.00			91.69	0.00	95.45	0.00	92.14	4.38	/workspace/coverage/cover_reg_top/56.xbar_access_same_device_slow_rsp.2347546098
90.52	0.48	90.87	0.00	85.18	0.38	85.29	0.00			91.70	0.01	95.45	0.00	94.65	2.51	/workspace/coverage/cover_reg_top/43.xbar_stress_all.4143729388
90.98	0.46	90.88	0.01	87.50	2.32	85.29	0.00			91.70	0.00	95.45	0.00	95.05	0.40	/workspace/coverage/cover_reg_top/17.chip_tl_errors.2523326365
91.43	0.45	91.99	1.11	88.12	0.62	85.69	0.40			92.25	0.55	95.45	0.00	95.05	0.00	/workspace/coverage/default/1.chip_sw_gpio.816144229
91.83	0.40	92.56	0.57	88.60	0.49	85.93	0.24			92.84	0.59	95.98	0.52	95.05	0.00	/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.130679918
92.19	0.36	92.63	0.07	88.63	0.02	88.00	2.07			92.87	0.02	95.98	0.00	95.05	0.00	/workspace/coverage/default/0.chip_sw_otbn_randomness.1711187372
92.47	0.28	93.12	0.49	89.08	0.45	88.25	0.25			93.33	0.46	95.98	0.00	95.05	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_10.3697949231
92.72	0.25	93.38	0.25	89.18	0.10	89.33	1.08			93.39	0.06	95.98	0.00	95.05	0.00	/workspace/coverage/default/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.1432125572
92.93	0.21	93.69	0.31	90.00	0.82	89.36	0.03			93.50	0.11	95.98	0.00	95.05	0.00	/workspace/coverage/cover_reg_top/15.chip_same_csr_outstanding.890166696
93.11	0.18	93.69	0.00	90.00	0.00	89.36	0.00			93.50	0.00	95.98	0.00	96.16	1.10	/workspace/coverage/cover_reg_top/41.xbar_access_same_device_slow_rsp.1856567404
93.29	0.17	93.83	0.14	90.20	0.20	89.80	0.44			93.74	0.24	95.98	0.00	96.17	0.01	/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.3119381838
93.44	0.15	93.83	0.00	90.22	0.02	90.04	0.24			93.74	0.00	95.98	0.00	96.80	0.63	/workspace/coverage/cover_reg_top/59.xbar_smoke_large_delays.2662286466
93.58	0.15	94.04	0.21	90.54	0.32	90.40	0.35			93.74	0.00	95.98	0.00	96.80	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.127048013
93.71	0.13	94.04	0.00	90.68	0.14	90.40	0.00			93.75	0.02	95.98	0.00	97.44	0.63	/workspace/coverage/cover_reg_top/77.xbar_stress_all.2596569468
93.83	0.12	94.06	0.02	90.99	0.31	90.42	0.03			94.11	0.36	95.98	0.00	97.44	0.00	/workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.449080180
93.95	0.12	94.06	0.01	91.01	0.02	90.91	0.49			94.11	0.00	96.15	0.17	97.44	0.00	/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.2914988699
94.05	0.10	94.10	0.04	91.05	0.04	91.44	0.52			94.14	0.03	96.15	0.00	97.44	0.00	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.1576757791
94.15	0.10	94.10	0.00	91.05	0.00	92.03	0.60			94.14	0.00	96.15	0.00	97.44	0.00	/workspace/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.1593622433
94.25	0.10	94.10	0.00	91.63	0.58	92.03	0.00			94.14	0.00	96.15	0.00	97.44	0.00	/workspace/coverage/cover_reg_top/21.chip_tl_errors.3442523775
94.34	0.09	94.10	0.00	91.64	0.01	92.58	0.55			94.14	0.00	96.15	0.00	97.44	0.00	/workspace/coverage/default/65.chip_sw_all_escalation_resets.3282270819
94.43	0.09	94.10	0.00	91.64	0.00	93.11	0.53			94.14	0.00	96.15	0.00	97.44	0.00	/workspace/coverage/default/1.chip_sw_flash_init.255831530
94.51	0.08	94.12	0.02	91.73	0.10	93.13	0.01			94.16	0.02	96.50	0.35	97.44	0.00	/workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.85993857
94.60	0.08	94.12	0.00	91.73	0.00	93.13	0.00			94.16	0.00	96.50	0.00	97.93	0.49	/workspace/coverage/cover_reg_top/72.xbar_access_same_device_slow_rsp.3649788405
94.68	0.08	94.30	0.18	91.84	0.11	93.22	0.10			94.26	0.10	96.50	0.00	97.93	0.00	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.4109156035
94.74	0.06	94.30	0.00	91.84	0.00	93.58	0.36			94.26	0.00	96.50	0.00	97.93	0.00	/workspace/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.2457962826
94.78	0.05	94.33	0.03	91.87	0.03	93.61	0.02			94.28	0.02	96.68	0.17	97.94	0.01	/workspace/coverage/default/3.chip_sw_all_escalation_resets.2136790466
94.83	0.05	94.38	0.05	92.01	0.14	93.61	0.00			94.38	0.10	96.68	0.00	97.94	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_retention.2890250510
94.88	0.05	94.38	0.00	92.03	0.02	93.61	0.00			94.38	0.00	96.68	0.00	98.21	0.27	/workspace/coverage/cover_reg_top/4.xbar_stress_all_with_reset_error.2647637071
94.92	0.04	94.39	0.01	92.04	0.01	93.85	0.24			94.38	0.00	96.68	0.00	98.21	0.00	/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.1531698934
94.97	0.04	94.39	0.00	92.15	0.11	93.85	0.01			94.51	0.13	96.68	0.00	98.21	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.2350099096
95.01	0.04	94.39	0.00	92.39	0.24	93.85	0.00			94.51	0.00	96.68	0.00	98.21	0.00	/workspace/coverage/cover_reg_top/29.chip_tl_errors.3934105425
95.05	0.04	94.40	0.01	92.41	0.01	93.85	0.00			94.53	0.02	96.85	0.17	98.23	0.01	/workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.2889240215
95.08	0.04	94.40	0.01	92.42	0.01	93.86	0.01			94.54	0.01	97.03	0.17	98.24	0.01	/workspace/coverage/default/16.chip_sw_all_escalation_resets.4163301232
95.12	0.04	94.41	0.01	92.43	0.01	93.87	0.01			94.55	0.01	97.20	0.17	98.25	0.01	/workspace/coverage/default/70.chip_sw_all_escalation_resets.3713301547
95.15	0.04	94.41	0.01	92.44	0.01	93.87	0.00			94.56	0.01	97.38	0.17	98.26	0.01	/workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.3686306021
95.19	0.04	94.41	0.00	92.45	0.01	94.08	0.21			94.56	0.00	97.38	0.00	98.26	0.00	/workspace/coverage/default/0.rom_e2e_jtag_debug_rma.3920986063
95.22	0.04	94.52	0.11	92.46	0.01	94.16	0.09			94.56	0.00	97.38	0.00	98.26	0.00	/workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.437782020
95.26	0.03	94.52	0.00	92.46	0.00	94.35	0.19			94.56	0.00	97.38	0.00	98.26	0.00	/workspace/coverage/default/2.chip_sw_flash_rma_unlocked.865660838
95.28	0.03	94.52	0.00	92.64	0.18	94.35	0.00			94.56	0.00	97.38	0.00	98.26	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_0.3788250889
95.31	0.03	94.60	0.07	92.66	0.03	94.38	0.02			94.60	0.05	97.38	0.00	98.26	0.00	/workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.4291751432
95.34	0.03	94.60	0.00	92.73	0.07	94.38	0.00			94.64	0.03	97.38	0.00	98.33	0.07	/workspace/coverage/cover_reg_top/59.xbar_stress_all_with_rand_reset.815111099
95.37	0.03	94.63	0.03	92.77	0.04	94.43	0.05			94.68	0.04	97.38	0.00	98.33	0.00	/workspace/coverage/default/0.chip_sw_usbdev_pincfg.2197779389
95.39	0.02	94.70	0.07	92.77	0.00	94.50	0.06			94.69	0.01	97.38	0.00	98.33	0.00	/workspace/coverage/default/4.chip_tap_straps_testunlock0.2867553281
95.42	0.02	94.70	0.00	92.82	0.05	94.50	0.00			94.69	0.00	97.38	0.00	98.43	0.09	/workspace/coverage/cover_reg_top/16.xbar_stress_all_with_rand_reset.4126035491
95.44	0.02	94.70	0.00	92.82	0.00	94.63	0.14			94.69	0.00	97.38	0.00	98.43	0.00	/workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.3040823167
95.46	0.02	94.70	0.00	92.87	0.06	94.63	0.00			94.70	0.02	97.38	0.00	98.48	0.06	/workspace/coverage/cover_reg_top/82.xbar_stress_all_with_rand_reset.430198194
95.48	0.02	94.70	0.00	92.87	0.00	94.75	0.12			94.70	0.00	97.38	0.00	98.48	0.00	/workspace/coverage/default/1.chip_sw_power_idle_load.4008640934
95.50	0.02	94.76	0.06	92.92	0.05	94.75	0.00			94.72	0.02	97.38	0.00	98.48	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_wake.3645180868
95.52	0.02	94.77	0.01	92.98	0.06	94.75	0.00			94.77	0.05	97.38	0.00	98.48	0.00	/workspace/coverage/default/0.chip_sw_spi_device_pinmux_sleep_retention.2556794378
95.54	0.02	94.77	0.00	93.09	0.11	94.75	0.00			94.77	0.00	97.38	0.00	98.48	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_20.2871278134
95.56	0.02	94.77	0.00	93.09	0.00	94.86	0.10			94.77	0.00	97.38	0.00	98.48	0.00	/workspace/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.3387641170
95.57	0.02	94.77	0.01	93.09	0.01	94.93	0.08			94.77	0.01	97.38	0.00	98.48	0.00	/workspace/coverage/cover_reg_top/0.chip_csr_hw_reset.2791238378
95.59	0.02	94.77	0.00	93.12	0.03	94.93	0.00			94.77	0.00	97.38	0.00	98.55	0.07	/workspace/coverage/cover_reg_top/61.xbar_stress_all.230006931
95.60	0.01	94.77	0.00	93.18	0.06	94.93	0.00			94.77	0.00	97.38	0.00	98.58	0.02	/workspace/coverage/cover_reg_top/18.chip_tl_errors.1459992673
95.61	0.01	94.78	0.01	93.25	0.07	94.93	0.00			94.77	0.00	97.38	0.00	98.58	0.00	/workspace/coverage/cover_reg_top/5.chip_same_csr_outstanding.38719883
95.63	0.01	94.78	0.00	93.31	0.07	94.93	0.00			94.77	0.00	97.38	0.00	98.58	0.00	/workspace/coverage/cover_reg_top/31.xbar_stress_all.2155413277
95.64	0.01	94.78	0.00	93.32	0.01	94.99	0.06			94.77	0.00	97.38	0.00	98.58	0.00	/workspace/coverage/default/2.rom_e2e_shutdown_output.4176427338
95.65	0.01	94.78	0.00	93.32	0.00	95.06	0.06			94.77	0.00	97.38	0.00	98.58	0.00	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.2768462824
95.66	0.01	94.78	0.00	93.34	0.02	95.06	0.00			94.79	0.02	97.38	0.00	98.60	0.02	/workspace/coverage/cover_reg_top/36.xbar_stress_all_with_rand_reset.4152002898
95.67	0.01	94.78	0.00	93.34	0.00	95.12	0.06			94.79	0.00	97.38	0.00	98.60	0.00	/workspace/coverage/default/1.chip_sw_flash_rma_unlocked.4249522749
95.68	0.01	94.78	0.00	93.39	0.05	95.12	0.00			94.79	0.00	97.38	0.00	98.60	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_0.1556478945
95.68	0.01	94.78	0.00	93.39	0.00	95.12	0.00			94.79	0.00	97.38	0.00	98.65	0.05	/workspace/coverage/cover_reg_top/85.xbar_stress_all_with_reset_error.3937763051
95.69	0.01	94.78	0.00	93.39	0.00	95.12	0.00			94.79	0.00	97.38	0.00	98.70	0.05	/workspace/coverage/cover_reg_top/9.xbar_stress_all_with_reset_error.2834203136
95.70	0.01	94.78	0.01	93.41	0.02	95.14	0.02			94.79	0.00	97.38	0.00	98.70	0.00	/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx1.728513015
95.71	0.01	94.78	0.00	93.44	0.03	95.14	0.00			94.81	0.02	97.38	0.00	98.70	0.00	/workspace/coverage/cover_reg_top/31.xbar_stress_all_with_rand_reset.885674708
95.71	0.01	94.78	0.00	93.44	0.00	95.18	0.04			94.81	0.00	97.38	0.00	98.70	0.00	/workspace/coverage/default/1.chip_sw_ast_clk_rst_inputs.4229400459
95.72	0.01	94.78	0.00	93.44	0.00	95.22	0.04			94.81	0.00	97.38	0.00	98.70	0.00	/workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.1962269225
95.73	0.01	94.78	0.00	93.44	0.00	95.26	0.04			94.81	0.00	97.38	0.00	98.70	0.00	/workspace/coverage/default/0.chip_sw_flash_rma_unlocked.3306258849
95.73	0.01	94.78	0.00	93.47	0.04	95.26	0.00			94.81	0.00	97.38	0.00	98.70	0.00	/workspace/coverage/cover_reg_top/20.chip_tl_errors.2642456181
95.74	0.01	94.78	0.00	93.51	0.04	95.26	0.00			94.81	0.00	97.38	0.00	98.70	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_20.504287819
95.74	0.01	94.78	0.00	93.51	0.00	95.26	0.00			94.81	0.00	97.38	0.00	98.73	0.04	/workspace/coverage/cover_reg_top/61.xbar_stress_all_with_reset_error.4129121977
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95.95	0.01	94.81	0.00	93.76	0.00	95.39	0.00			94.81	0.00	97.38	0.00	99.57	0.01	/workspace/coverage/default/96.chip_sw_all_escalation_resets.1919019360
95.95	0.01	94.81	0.00	93.76	0.00	95.39	0.00			94.81	0.00	97.38	0.00	99.58	0.01	/workspace/coverage/default/98.chip_sw_all_escalation_resets.930404952
95.96	0.01	94.81	0.01	93.76	0.00	95.40	0.01			94.81	0.00	97.38	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.2282600794
95.96	0.01	94.81	0.00	93.77	0.01	95.40	0.00			94.81	0.00	97.38	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/54.xbar_random_slow_rsp.1415607901
95.96	0.01	94.81	0.00	93.78	0.01	95.40	0.00			94.81	0.00	97.38	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.1928262956
95.96	0.01	94.81	0.00	93.80	0.01	95.40	0.00			94.81	0.00	97.38	0.00	99.58	0.00	/workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.306734933
95.96	0.01	94.81	0.00	93.81	0.01	95.40	0.00			94.81	0.00	97.38	0.00	99.58	0.00	/workspace/coverage/default/2.chip_sw_pwrmgr_lowpower_cancel.3282923435
95.96	0.01	94.81	0.01	93.81	0.00	95.41	0.01			94.81	0.00	97.38	0.00	99.58	0.00	/workspace/coverage/default/27.chip_sw_all_escalation_resets.2906093149
95.97	0.01	94.81	0.00	93.81	0.00	95.42	0.01			94.81	0.00	97.38	0.00	99.58	0.00	/workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.63079378
95.97	0.01	94.81	0.00	93.81	0.00	95.42	0.01			94.81	0.00	97.38	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.1011714872
95.97	0.01	94.81	0.00	93.81	0.00	95.43	0.01			94.81	0.00	97.38	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.910074652
95.97	0.01	94.81	0.00	93.81	0.00	95.43	0.00			94.82	0.01	97.38	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.964887743
95.97	0.01	94.81	0.00	93.81	0.01	95.43	0.00			94.82	0.00	97.38	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/1.chip_tl_errors.881554306
95.97	0.01	94.81	0.00	93.82	0.01	95.43	0.00			94.82	0.00	97.38	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/2.xbar_stress_all.1494444296
95.97	0.01	94.81	0.00	93.83	0.01	95.43	0.00			94.82	0.00	97.38	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/37.xbar_access_same_device.1086264748
95.98	0.01	94.81	0.00	93.83	0.01	95.43	0.00			94.82	0.00	97.38	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_rstmgr_alert_info.2211420567
95.98	0.01	94.81	0.00	93.84	0.01	95.43	0.00			94.82	0.00	97.38	0.00	99.58	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_10.4002482627
95.98	0.01	94.81	0.00	93.84	0.00	95.44	0.01			94.82	0.00	97.38	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/2.chip_csr_hw_reset.1221357663
95.98	0.01	94.81	0.00	93.84	0.00	95.45	0.01			94.82	0.00	97.38	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3252956865
95.98	0.01	94.81	0.00	93.84	0.00	95.45	0.01			94.82	0.00	97.38	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.4151496967
95.98	0.01	94.81	0.00	93.84	0.01	95.46	0.01			94.82	0.00	97.38	0.00	99.58	0.00	/workspace/coverage/default/0.chip_jtag_csr_rw.794713476
95.98	0.01	94.81	0.00	93.84	0.00	95.46	0.01			94.82	0.00	97.38	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_edn_sw_mode.2828191313
95.98	0.01	94.81	0.00	93.84	0.00	95.47	0.01			94.82	0.00	97.38	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_flash_init.659931423
95.98	0.01	94.81	0.00	93.84	0.00	95.47	0.01			94.82	0.00	97.38	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_lc_ctrl_program_error.1346979602
95.98	0.01	94.81	0.00	93.84	0.00	95.48	0.01			94.82	0.00	97.38	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.996566862
95.98	0.01	94.81	0.00	93.84	0.00	95.48	0.01			94.82	0.00	97.38	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.3809821863
95.99	0.01	94.81	0.00	93.84	0.00	95.49	0.01			94.82	0.00	97.38	0.00	99.58	0.00	/workspace/coverage/default/1.chip_sw_keymgr_sideload_aes.1416013209
95.99	0.01	94.81	0.00	93.85	0.01	95.49	0.00			94.82	0.00	97.38	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/12.xbar_stress_all.1496567316
95.99	0.01	94.81	0.00	93.85	0.01	95.49	0.00			94.82	0.00	97.38	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/26.xbar_stress_all_with_error.15920965
95.99	0.01	94.81	0.00	93.86	0.01	95.49	0.00			94.82	0.00	97.38	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/6.chip_tl_errors.3225132169
95.99	0.01	94.81	0.00	93.86	0.01	95.49	0.00			94.82	0.00	97.38	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/63.xbar_stress_all_with_error.146418738
95.99	0.01	94.81	0.00	93.86	0.01	95.49	0.00			94.82	0.00	97.38	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/83.xbar_stress_all_with_error.1268263505
95.99	0.01	94.81	0.00	93.87	0.01	95.49	0.00			94.82	0.00	97.38	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_hmac_enc.4248903229
95.99	0.01	94.81	0.00	93.87	0.01	95.49	0.00			94.82	0.00	97.38	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.718372724
95.99	0.01	94.81	0.00	93.87	0.01	95.49	0.00			94.82	0.00	97.38	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.3762471154
95.99	0.01	94.81	0.00	93.88	0.01	95.49	0.00			94.82	0.00	97.38	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.1512680640
95.99	0.01	94.81	0.00	93.88	0.01	95.49	0.00			94.82	0.00	97.38	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.919964909
95.99	0.01	94.81	0.00	93.88	0.00	95.49	0.01			94.82	0.00	97.38	0.00	99.58	0.00	/workspace/coverage/default/0.chip_tap_straps_rma.1106400984
95.99	0.01	94.81	0.00	93.88	0.00	95.49	0.01			94.82	0.00	97.38	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/3.chip_csr_hw_reset.867146212
95.99	0.01	94.81	0.00	93.88	0.00	95.49	0.01			94.82	0.00	97.38	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_edn_boot_mode.2833870172
95.99	0.01	94.81	0.00	93.88	0.00	95.50	0.01			94.82	0.00	97.38	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.342010999
95.99	0.01	94.81	0.00	93.88	0.00	95.50	0.01			94.82	0.00	97.38	0.00	99.58	0.00	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.2446555345

---

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.chip_csr_aliasing.1884209678
/workspace/coverage/cover_reg_top/0.chip_csr_bit_bash.1274217575
/workspace/coverage/cover_reg_top/0.chip_csr_mem_rw_with_rand_reset.3309450817
/workspace/coverage/cover_reg_top/0.chip_csr_rw.114769232
/workspace/coverage/cover_reg_top/0.chip_prim_tl_access.1916802172
/workspace/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.110637710
/workspace/coverage/cover_reg_top/0.chip_same_csr_outstanding.111613907
/workspace/coverage/cover_reg_top/0.chip_tl_errors.2548840741
/workspace/coverage/cover_reg_top/0.xbar_access_same_device.471563413
/workspace/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.136899040
/workspace/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.2350007744
/workspace/coverage/cover_reg_top/0.xbar_error_random.1692864048
/workspace/coverage/cover_reg_top/0.xbar_random.13821266
/workspace/coverage/cover_reg_top/0.xbar_random_large_delays.2125246835
/workspace/coverage/cover_reg_top/0.xbar_random_slow_rsp.3291689064
/workspace/coverage/cover_reg_top/0.xbar_random_zero_delays.684541139
/workspace/coverage/cover_reg_top/0.xbar_same_source.4178988458
/workspace/coverage/cover_reg_top/0.xbar_smoke.4024463689
/workspace/coverage/cover_reg_top/0.xbar_smoke_large_delays.94243316
/workspace/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.3413861947
/workspace/coverage/cover_reg_top/0.xbar_smoke_zero_delays.845876864
/workspace/coverage/cover_reg_top/0.xbar_stress_all.40812759
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_error.103410191
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.3726104890
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.960717281
/workspace/coverage/cover_reg_top/0.xbar_unmapped_addr.3709093455
/workspace/coverage/cover_reg_top/1.chip_csr_bit_bash.3090751793
/workspace/coverage/cover_reg_top/1.chip_csr_mem_rw_with_rand_reset.2724558892
/workspace/coverage/cover_reg_top/1.chip_csr_rw.1847361739
/workspace/coverage/cover_reg_top/1.chip_prim_tl_access.2917098274
/workspace/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.466327323
/workspace/coverage/cover_reg_top/1.xbar_access_same_device.2931088885
/workspace/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.627598353
/workspace/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.3322126493
/workspace/coverage/cover_reg_top/1.xbar_error_random.4242622185
/workspace/coverage/cover_reg_top/1.xbar_random.1696392290
/workspace/coverage/cover_reg_top/1.xbar_random_large_delays.2453223510
/workspace/coverage/cover_reg_top/1.xbar_random_slow_rsp.81661605
/workspace/coverage/cover_reg_top/1.xbar_random_zero_delays.511054742
/workspace/coverage/cover_reg_top/1.xbar_same_source.2768661510
/workspace/coverage/cover_reg_top/1.xbar_smoke.3167241636
/workspace/coverage/cover_reg_top/1.xbar_smoke_large_delays.3807646151
/workspace/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.1966145682
/workspace/coverage/cover_reg_top/1.xbar_smoke_zero_delays.310988355
/workspace/coverage/cover_reg_top/1.xbar_stress_all.559765700
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_error.3334392022
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.3204388717
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.4178593791
/workspace/coverage/cover_reg_top/1.xbar_unmapped_addr.3316419306
/workspace/coverage/cover_reg_top/10.chip_csr_mem_rw_with_rand_reset.4091941208
/workspace/coverage/cover_reg_top/10.chip_csr_rw.433526455
/workspace/coverage/cover_reg_top/10.chip_same_csr_outstanding.3850187320
/workspace/coverage/cover_reg_top/10.chip_tl_errors.3907395493
/workspace/coverage/cover_reg_top/10.xbar_access_same_device.3874999868
/workspace/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.533522878
/workspace/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.3821767446
/workspace/coverage/cover_reg_top/10.xbar_error_random.4292646488
/workspace/coverage/cover_reg_top/10.xbar_random.3669642485
/workspace/coverage/cover_reg_top/10.xbar_random_large_delays.1174074075
/workspace/coverage/cover_reg_top/10.xbar_random_slow_rsp.4073923532
/workspace/coverage/cover_reg_top/10.xbar_random_zero_delays.1293451813
/workspace/coverage/cover_reg_top/10.xbar_same_source.3936539145
/workspace/coverage/cover_reg_top/10.xbar_smoke.1067633090
/workspace/coverage/cover_reg_top/10.xbar_smoke_large_delays.3164410712
/workspace/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.963331340
/workspace/coverage/cover_reg_top/10.xbar_smoke_zero_delays.3450113540
/workspace/coverage/cover_reg_top/10.xbar_stress_all.1649494506
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_error.2864191055
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.3580333249
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.2571029440
/workspace/coverage/cover_reg_top/10.xbar_unmapped_addr.1641599403
/workspace/coverage/cover_reg_top/11.chip_csr_mem_rw_with_rand_reset.4046255040
/workspace/coverage/cover_reg_top/11.chip_same_csr_outstanding.3876219023
/workspace/coverage/cover_reg_top/11.chip_tl_errors.570726422
/workspace/coverage/cover_reg_top/11.xbar_access_same_device.308547161
/workspace/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.3481332918
/workspace/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.3818642538
/workspace/coverage/cover_reg_top/11.xbar_error_random.2815896555
/workspace/coverage/cover_reg_top/11.xbar_random.680696018
/workspace/coverage/cover_reg_top/11.xbar_random_large_delays.1213726717
/workspace/coverage/cover_reg_top/11.xbar_random_slow_rsp.2746845098
/workspace/coverage/cover_reg_top/11.xbar_random_zero_delays.3442618276
/workspace/coverage/cover_reg_top/11.xbar_same_source.709500766
/workspace/coverage/cover_reg_top/11.xbar_smoke.1488952247
/workspace/coverage/cover_reg_top/11.xbar_smoke_large_delays.1502434743
/workspace/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.1008794538
/workspace/coverage/cover_reg_top/11.xbar_smoke_zero_delays.1687411158
/workspace/coverage/cover_reg_top/11.xbar_stress_all.381232508
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_error.1310083266
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.3589797486
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.957017705
/workspace/coverage/cover_reg_top/11.xbar_unmapped_addr.4275016580
/workspace/coverage/cover_reg_top/12.chip_csr_mem_rw_with_rand_reset.1483866372
/workspace/coverage/cover_reg_top/12.chip_csr_rw.2388993871
/workspace/coverage/cover_reg_top/12.chip_same_csr_outstanding.1911647461
/workspace/coverage/cover_reg_top/12.chip_tl_errors.1814550867
/workspace/coverage/cover_reg_top/12.xbar_access_same_device.3279196996
/workspace/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.962079651
/workspace/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.3864372728
/workspace/coverage/cover_reg_top/12.xbar_error_random.1356392
/workspace/coverage/cover_reg_top/12.xbar_random.2318376030
/workspace/coverage/cover_reg_top/12.xbar_random_large_delays.3731660227
/workspace/coverage/cover_reg_top/12.xbar_random_slow_rsp.2595772599
/workspace/coverage/cover_reg_top/12.xbar_random_zero_delays.2955080692
/workspace/coverage/cover_reg_top/12.xbar_same_source.457864810
/workspace/coverage/cover_reg_top/12.xbar_smoke.2471965763
/workspace/coverage/cover_reg_top/12.xbar_smoke_large_delays.2233877442
/workspace/coverage/cover_reg_top/12.xbar_smoke_slow_rsp.3136302642
/workspace/coverage/cover_reg_top/12.xbar_smoke_zero_delays.3035026319
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_error.3537234934
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_rand_reset.24719183
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_reset_error.127968757
/workspace/coverage/cover_reg_top/12.xbar_unmapped_addr.3439558846
/workspace/coverage/cover_reg_top/13.chip_csr_mem_rw_with_rand_reset.2404267289
/workspace/coverage/cover_reg_top/13.chip_csr_rw.1369287536
/workspace/coverage/cover_reg_top/13.chip_same_csr_outstanding.1650550061
/workspace/coverage/cover_reg_top/13.chip_tl_errors.2664065706
/workspace/coverage/cover_reg_top/13.xbar_access_same_device.2991717859
/workspace/coverage/cover_reg_top/13.xbar_access_same_device_slow_rsp.3279190034
/workspace/coverage/cover_reg_top/13.xbar_error_and_unmapped_addr.2879012795
/workspace/coverage/cover_reg_top/13.xbar_error_random.1267893051
/workspace/coverage/cover_reg_top/13.xbar_random.1200812679
/workspace/coverage/cover_reg_top/13.xbar_random_large_delays.1599613264
/workspace/coverage/cover_reg_top/13.xbar_random_slow_rsp.2985345835
/workspace/coverage/cover_reg_top/13.xbar_random_zero_delays.4180527772
/workspace/coverage/cover_reg_top/13.xbar_same_source.2239280355
/workspace/coverage/cover_reg_top/13.xbar_smoke.2098581797
/workspace/coverage/cover_reg_top/13.xbar_smoke_large_delays.212684644
/workspace/coverage/cover_reg_top/13.xbar_smoke_slow_rsp.751515442
/workspace/coverage/cover_reg_top/13.xbar_smoke_zero_delays.1550950459
/workspace/coverage/cover_reg_top/13.xbar_stress_all.1650767765
/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_error.1388792497
/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_rand_reset.3058018163
/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_reset_error.2789475459
/workspace/coverage/cover_reg_top/13.xbar_unmapped_addr.2726767717
/workspace/coverage/cover_reg_top/14.chip_csr_mem_rw_with_rand_reset.3681890134
/workspace/coverage/cover_reg_top/14.chip_csr_rw.1863316711
/workspace/coverage/cover_reg_top/14.chip_same_csr_outstanding.3658753221
/workspace/coverage/cover_reg_top/14.chip_tl_errors.3748756109
/workspace/coverage/cover_reg_top/14.xbar_access_same_device.1918092833
/workspace/coverage/cover_reg_top/14.xbar_access_same_device_slow_rsp.931722728
/workspace/coverage/cover_reg_top/14.xbar_error_and_unmapped_addr.136445306
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/workspace/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.1129884442
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/workspace/coverage/default/2.chip_sw_rv_plic_smoketest.4038908161
/workspace/coverage/default/2.chip_sw_rv_timer_irq.809666219
/workspace/coverage/default/2.chip_sw_rv_timer_smoketest.3309066863
/workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.3263526636
/workspace/coverage/default/2.chip_sw_sensor_ctrl_status.4018106056
/workspace/coverage/default/2.chip_sw_sleep_pin_retention.3428185573
/workspace/coverage/default/2.chip_sw_sleep_pin_wake.1089429863
/workspace/coverage/default/2.chip_sw_sleep_pwm_pulses.1955177449
/workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.884466217
/workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.4058278122
/workspace/coverage/default/2.chip_sw_spi_device_pass_through.1100679738
/workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.2447138909
/workspace/coverage/default/2.chip_sw_spi_device_pinmux_sleep_retention.3723243619
/workspace/coverage/default/2.chip_sw_spi_device_tpm.3987524170
/workspace/coverage/default/2.chip_sw_sram_ctrl_execution_main.4012996507
/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.746742566
/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.1181695164
/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.3784996020
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/workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.3281674267
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.1498712318
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/workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.151743946
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.2455731388
/workspace/coverage/default/2.chip_sw_uart_rand_baudrate.1314874364
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/workspace/coverage/default/2.chip_sw_uart_tx_rx.1888712712
/workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.3206236875
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/workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_invalid_meas.940794840
/workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_meas.2507351583
/workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_no_meas.1531902493
/workspace/coverage/default/2.rom_e2e_self_hash.4220090982
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/workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.3187867736
/workspace/coverage/default/24.chip_sw_all_escalation_resets.3529707143
/workspace/coverage/default/26.chip_sw_all_escalation_resets.3954999461
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/workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.380632540
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/workspace/coverage/default/3.chip_sw_uart_rand_baudrate.1330896646
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/workspace/coverage/default/3.chip_tap_straps_rma.1390236355
/workspace/coverage/default/3.chip_tap_straps_testunlock0.3270860043
/workspace/coverage/default/30.chip_sw_all_escalation_resets.4198748736
/workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.3820934977
/workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.2430336146
/workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.2240864437
/workspace/coverage/default/33.chip_sw_all_escalation_resets.23545203
/workspace/coverage/default/34.chip_sw_all_escalation_resets.1483098602
/workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.3798598532
/workspace/coverage/default/35.chip_sw_all_escalation_resets.3922241763
/workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.3940164373
/workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.2898910640
/workspace/coverage/default/38.chip_sw_all_escalation_resets.731323771
/workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.2606576761
/workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.313617803
/workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.526266059
/workspace/coverage/default/4.chip_sw_csrng_edn_concurrency.1303654403
/workspace/coverage/default/4.chip_sw_data_integrity_escalation.415670257
/workspace/coverage/default/4.chip_sw_lc_ctrl_transition.2028116250
/workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.3747788812
/workspace/coverage/default/4.chip_sw_uart_rand_baudrate.2679284653
/workspace/coverage/default/4.chip_sw_uart_tx_rx.3167989546
/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.3953176346
/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1343665837
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.2584152145
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.3786719089
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.3162500779
/workspace/coverage/default/4.chip_tap_straps_dev.2314586352
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/workspace/coverage/default/4.chip_tap_straps_rma.3094837181
/workspace/coverage/default/40.chip_sw_all_escalation_resets.1347136815
/workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.2400036884
/workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.1936090354
/workspace/coverage/default/42.chip_sw_all_escalation_resets.840667258
/workspace/coverage/default/43.chip_sw_all_escalation_resets.2890966324
/workspace/coverage/default/44.chip_sw_all_escalation_resets.177563633
/workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.1654777892
/workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.1072501103
/workspace/coverage/default/46.chip_sw_all_escalation_resets.652311608
/workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.2780037013
/workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.4208370180
/workspace/coverage/default/5.chip_sw_all_escalation_resets.1277337346
/workspace/coverage/default/5.chip_sw_csrng_edn_concurrency.2057176553
/workspace/coverage/default/5.chip_sw_data_integrity_escalation.3332795370
/workspace/coverage/default/5.chip_sw_lc_ctrl_transition.710628435
/workspace/coverage/default/5.chip_sw_uart_rand_baudrate.3793882001
/workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.2233770078
/workspace/coverage/default/50.chip_sw_all_escalation_resets.1129492605
/workspace/coverage/default/51.chip_sw_all_escalation_resets.77558576
/workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.1320975695
/workspace/coverage/default/52.chip_sw_all_escalation_resets.2387169639
/workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.4182591047
/workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.184326007
/workspace/coverage/default/55.chip_sw_all_escalation_resets.757775412
/workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.3839933484
/workspace/coverage/default/56.chip_sw_all_escalation_resets.2684669685
/workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.3035448038
/workspace/coverage/default/57.chip_sw_all_escalation_resets.1007401920
/workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.3866594794
/workspace/coverage/default/58.chip_sw_all_escalation_resets.2503169580
/workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.3897203509
/workspace/coverage/default/59.chip_sw_all_escalation_resets.1192483144
/workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.2032196756
/workspace/coverage/default/6.chip_sw_all_escalation_resets.501606992
/workspace/coverage/default/6.chip_sw_csrng_edn_concurrency.606322277
/workspace/coverage/default/6.chip_sw_lc_ctrl_transition.3512985814
/workspace/coverage/default/6.chip_sw_uart_rand_baudrate.1433590992
/workspace/coverage/default/60.chip_sw_all_escalation_resets.3069359258
/workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.3269039891
/workspace/coverage/default/61.chip_sw_all_escalation_resets.1959480958
/workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.1536267937
/workspace/coverage/default/62.chip_sw_all_escalation_resets.1226927752
/workspace/coverage/default/63.chip_sw_all_escalation_resets.1061662135
/workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.1303946376
/workspace/coverage/default/64.chip_sw_all_escalation_resets.1405543559
/workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.3526419876
/workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.3812126697
/workspace/coverage/default/68.chip_sw_all_escalation_resets.218348914
/workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.698682087
/workspace/coverage/default/7.chip_sw_all_escalation_resets.2874043366
/workspace/coverage/default/7.chip_sw_csrng_edn_concurrency.1712244903
/workspace/coverage/default/7.chip_sw_lc_ctrl_transition.4074088490
/workspace/coverage/default/7.chip_sw_uart_rand_baudrate.889213470
/workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.356198862
/workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.3835200867
/workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.2282158805
/workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.406787319
/workspace/coverage/default/73.chip_sw_all_escalation_resets.1082446425
/workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.231721879
/workspace/coverage/default/74.chip_sw_all_escalation_resets.2579078876
/workspace/coverage/default/75.chip_sw_all_escalation_resets.3007639572
/workspace/coverage/default/76.chip_sw_all_escalation_resets.2712668335
/workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.2044172973
/workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.1421804123
/workspace/coverage/default/78.chip_sw_all_escalation_resets.1521433925
/workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.1265082691
/workspace/coverage/default/79.chip_sw_all_escalation_resets.2475397272
/workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.77396001
/workspace/coverage/default/8.chip_sw_all_escalation_resets.3114368488
/workspace/coverage/default/8.chip_sw_csrng_edn_concurrency.3896771499
/workspace/coverage/default/8.chip_sw_lc_ctrl_transition.1803840595
/workspace/coverage/default/8.chip_sw_uart_rand_baudrate.3464666440
/workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.2299463042
/workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.2579728742
/workspace/coverage/default/81.chip_sw_all_escalation_resets.2239686132
/workspace/coverage/default/82.chip_sw_all_escalation_resets.621566700
/workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.4046829066
/workspace/coverage/default/83.chip_sw_all_escalation_resets.3607151083
/workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.3801628871
/workspace/coverage/default/84.chip_sw_all_escalation_resets.3210919716
/workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.1899212234
/workspace/coverage/default/85.chip_sw_all_escalation_resets.855394819
/workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.2296847409
/workspace/coverage/default/86.chip_sw_all_escalation_resets.1143429588
/workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.2485457168
/workspace/coverage/default/87.chip_sw_all_escalation_resets.1527344093
/workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.471750142
/workspace/coverage/default/88.chip_sw_all_escalation_resets.3840078170
/workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.1337809478
/workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.914264553
/workspace/coverage/default/9.chip_sw_all_escalation_resets.2252312159
/workspace/coverage/default/9.chip_sw_csrng_edn_concurrency.3992241867
/workspace/coverage/default/9.chip_sw_lc_ctrl_transition.3559338183
/workspace/coverage/default/9.chip_sw_uart_rand_baudrate.1506082511
/workspace/coverage/default/90.chip_sw_all_escalation_resets.494243598
/workspace/coverage/default/91.chip_sw_all_escalation_resets.3379894938
/workspace/coverage/default/92.chip_sw_all_escalation_resets.3169348177
/workspace/coverage/default/93.chip_sw_all_escalation_resets.362424133
/workspace/coverage/default/94.chip_sw_all_escalation_resets.3078634178
/workspace/coverage/default/95.chip_sw_all_escalation_resets.3494593639
/workspace/coverage/default/97.chip_sw_all_escalation_resets.1527007143
/workspace/coverage/default/99.chip_sw_all_escalation_resets.1991969145
/workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.170713513
/workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.4219510203
/workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.1042589280
/workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.255529957
/workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.557756084
/workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.1787389213
/workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.181456242
/workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.2966118887

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Total test records in report: 2935

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TEST NO	TEST LOCATION	TEST NAME	STATUS	STARTED	FINISHED	SIMULATION TIME
T1	/workspace/coverage/default/2.chip_sw_alert_handler_entropy.3824319842			Aug 10 08:35:11 PM PDT 24	Aug 10 08:40:58 PM PDT 24	3433651259 ps
T2	/workspace/coverage/default/0.chip_sw_otbn_mem_scramble.1187610465			Aug 10 08:10:51 PM PDT 24	Aug 10 08:18:35 PM PDT 24	3683580440 ps
T3	/workspace/coverage/default/2.chip_sw_uart_tx_rx.1888712712			Aug 10 08:28:59 PM PDT 24	Aug 10 08:40:50 PM PDT 24	3706658572 ps
T4	/workspace/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.4147199232			Aug 10 08:18:25 PM PDT 24	Aug 10 08:28:35 PM PDT 24	4929106186 ps
T5	/workspace/coverage/default/1.chip_sw_power_idle_load.4008640934			Aug 10 08:27:48 PM PDT 24	Aug 10 08:40:09 PM PDT 24	4153961928 ps
T54	/workspace/coverage/default/2.chip_sw_alert_test.1308471732			Aug 10 08:35:03 PM PDT 24	Aug 10 08:40:58 PM PDT 24	2963065400 ps
T15	/workspace/coverage/default/6.chip_sw_uart_rand_baudrate.1433590992			Aug 10 08:43:09 PM PDT 24	Aug 10 08:50:37 PM PDT 24	3790271900 ps
T48	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod.412737385			Aug 10 08:17:35 PM PDT 24	Aug 10 09:30:39 PM PDT 24	15258192860 ps
T34	/workspace/coverage/default/2.chip_sw_rstmgr_sw_req.4140960540			Aug 10 08:31:14 PM PDT 24	Aug 10 08:37:25 PM PDT 24	3240668078 ps
T90	/workspace/coverage/default/0.chip_sw_uart_rand_baudrate.246102565			Aug 10 08:13:59 PM PDT 24	Aug 10 08:25:39 PM PDT 24	5017774600 ps
T131	/workspace/coverage/default/0.chip_sw_otbn_randomness.1711187372			Aug 10 08:12:06 PM PDT 24	Aug 10 08:24:34 PM PDT 24	6603639384 ps
T135	/workspace/coverage/default/1.chip_sw_entropy_src_smoketest.2156958102			Aug 10 08:28:40 PM PDT 24	Aug 10 08:39:41 PM PDT 24	4422749670 ps
T49	/workspace/coverage/default/0.rom_e2e_jtag_debug_rma.3920986063			Aug 10 08:16:44 PM PDT 24	Aug 10 08:56:09 PM PDT 24	11686834954 ps
T64	/workspace/coverage/default/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.1432125572			Aug 10 08:22:39 PM PDT 24	Aug 11 12:07:02 AM PDT 24	255516224318 ps
T178	/workspace/coverage/default/1.chip_sw_rv_core_ibex_icache_invalidate.1030579477			Aug 10 08:27:23 PM PDT 24	Aug 10 08:31:02 PM PDT 24	2697748903 ps
T65	/workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.3291327749			Aug 10 08:46:53 PM PDT 24	Aug 10 08:52:51 PM PDT 24	3684391760 ps
T66	/workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.914264553			Aug 10 08:43:49 PM PDT 24	Aug 10 08:49:19 PM PDT 24	3389685112 ps
T258	/workspace/coverage/default/1.chip_sw_aes_masking_off.2972526559			Aug 10 08:23:24 PM PDT 24	Aug 10 08:29:24 PM PDT 24	2508768552 ps
T228	/workspace/coverage/default/2.chip_sw_aon_timer_smoketest.1922306746			Aug 10 08:38:46 PM PDT 24	Aug 10 08:45:28 PM PDT 24	3519477500 ps
T136	/workspace/coverage/default/1.chip_sw_entropy_src_kat_test.2956080867			Aug 10 08:22:58 PM PDT 24	Aug 10 08:26:01 PM PDT 24	2423521548 ps
T259	/workspace/coverage/default/0.chip_sw_edn_sw_mode.2828191313			Aug 10 08:12:48 PM PDT 24	Aug 10 08:46:32 PM PDT 24	10012761712 ps
T6	/workspace/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.2457962826			Aug 10 08:10:45 PM PDT 24	Aug 10 08:14:00 PM PDT 24	3784957012 ps
T67	/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.3119381838			Aug 10 08:11:59 PM PDT 24	Aug 10 08:33:21 PM PDT 24	10325456133 ps
T68	/workspace/coverage/default/23.chip_sw_all_escalation_resets.72565828			Aug 10 08:46:55 PM PDT 24	Aug 10 08:57:37 PM PDT 24	5356058106 ps
T52	/workspace/coverage/default/4.chip_tap_straps_testunlock0.2867553281			Aug 10 08:40:55 PM PDT 24	Aug 10 08:43:41 PM PDT 24	2145982464 ps
T122	/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.2914988699			Aug 10 08:14:42 PM PDT 24	Aug 10 08:23:31 PM PDT 24	3359330061 ps
T138	/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_power_glitch_reset.3452110732			Aug 10 08:33:02 PM PDT 24	Aug 10 08:41:19 PM PDT 24	6395321800 ps
T193	/workspace/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.4102760343			Aug 10 08:20:36 PM PDT 24	Aug 10 08:35:54 PM PDT 24	7803869800 ps
T22	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_outputs.2850761667			Aug 10 08:33:32 PM PDT 24	Aug 10 08:40:11 PM PDT 24	3522302216 ps
T164	/workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.3839933484			Aug 10 08:48:16 PM PDT 24	Aug 10 08:53:12 PM PDT 24	4296848624 ps
T130	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_wake_5_bug.2026322918			Aug 10 08:17:34 PM PDT 24	Aug 10 08:23:18 PM PDT 24	6308454494 ps
T7	/workspace/coverage/default/1.chip_sw_inject_scramble_seed.2087327716			Aug 10 08:19:14 PM PDT 24	Aug 10 11:37:13 PM PDT 24	65518909928 ps
T194	/workspace/coverage/default/2.chip_sw_flash_crash_alert.4094473887			Aug 10 08:38:21 PM PDT 24	Aug 10 08:50:10 PM PDT 24	5203343352 ps
T735	/workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.416944324			Aug 10 08:43:59 PM PDT 24	Aug 10 08:50:58 PM PDT 24	3779904544 ps
T8	/workspace/coverage/default/2.chip_sw_rom_ctrl_integrity_check.2179610898			Aug 10 08:36:18 PM PDT 24	Aug 10 08:47:35 PM PDT 24	8481184159 ps
T903	/workspace/coverage/default/2.chip_sw_entropy_src_kat_test.3799399759			Aug 10 08:33:01 PM PDT 24	Aug 10 08:38:32 PM PDT 24	3225044102 ps
T215	/workspace/coverage/default/39.chip_sw_all_escalation_resets.1772010136			Aug 10 08:44:55 PM PDT 24	Aug 10 08:54:31 PM PDT 24	5029932792 ps
T219	/workspace/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.3768719527			Aug 10 08:22:21 PM PDT 24	Aug 10 08:32:26 PM PDT 24	4066954840 ps
T88	/workspace/coverage/default/0.chip_sw_usbdev_vbus.2741209403			Aug 10 08:11:30 PM PDT 24	Aug 10 08:15:00 PM PDT 24	3250204582 ps
T16	/workspace/coverage/default/1.chip_sw_gpio.816144229			Aug 10 08:18:21 PM PDT 24	Aug 10 08:24:56 PM PDT 24	3608396360 ps
T72	/workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.138035102			Aug 10 08:16:37 PM PDT 24	Aug 10 08:23:01 PM PDT 24	4532945180 ps
T403	/workspace/coverage/default/2.chip_sw_flash_ctrl_access.2163966580			Aug 10 08:30:41 PM PDT 24	Aug 10 08:50:15 PM PDT 24	6138356500 ps
T382	/workspace/coverage/default/0.chip_sw_flash_scrambling_smoketest.2321959628			Aug 10 08:17:53 PM PDT 24	Aug 10 08:21:11 PM PDT 24	2195631176 ps
T76	/workspace/coverage/default/0.chip_sw_usb_ast_clk_calib.931407244			Aug 10 08:15:31 PM PDT 24	Aug 10 08:20:25 PM PDT 24	3264941202 ps
T703	/workspace/coverage/default/0.chip_sw_hmac_smoketest.1743048181			Aug 10 08:17:51 PM PDT 24	Aug 10 08:22:38 PM PDT 24	2879494660 ps
T904	/workspace/coverage/default/0.chip_sw_example_flash.3618338554			Aug 10 08:10:57 PM PDT 24	Aug 10 08:14:46 PM PDT 24	3168826496 ps
T132	/workspace/coverage/default/1.chip_sw_edn_auto_mode.243274293			Aug 10 08:23:23 PM PDT 24	Aug 10 08:56:14 PM PDT 24	7156333556 ps
T71	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.2768462824			Aug 10 08:25:54 PM PDT 24	Aug 10 08:38:52 PM PDT 24	3902085070 ps
T45	/workspace/coverage/default/2.rom_e2e_shutdown_output.4176427338			Aug 10 08:43:48 PM PDT 24	Aug 10 09:31:19 PM PDT 24	23297424932 ps
T243	/workspace/coverage/default/1.chip_sw_rom_ctrl_integrity_check.934576068			Aug 10 08:24:01 PM PDT 24	Aug 10 08:31:15 PM PDT 24	9200886748 ps
T139	/workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.1011714872			Aug 10 08:13:21 PM PDT 24	Aug 10 08:21:39 PM PDT 24	7056995144 ps
T159	/workspace/coverage/default/1.chip_sw_keymgr_key_derivation.1203701197			Aug 10 08:23:50 PM PDT 24	Aug 10 08:52:30 PM PDT 24	7180906040 ps
T57	/workspace/coverage/default/0.chip_sw_spi_device_pinmux_sleep_retention.2556794378			Aug 10 08:10:06 PM PDT 24	Aug 10 08:15:07 PM PDT 24	3669571448 ps
T105	/workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.4291751432			Aug 10 08:15:02 PM PDT 24	Aug 10 08:30:18 PM PDT 24	7483781560 ps
T106	/workspace/coverage/default/2.chip_sw_keymgr_key_derivation.699329384			Aug 10 08:36:16 PM PDT 24	Aug 10 09:21:48 PM PDT 24	12184256358 ps
T107	/workspace/coverage/default/3.chip_sw_all_escalation_resets.2136790466			Aug 10 08:40:50 PM PDT 24	Aug 10 08:48:54 PM PDT 24	5480227050 ps
T108	/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.2822343254			Aug 10 08:21:04 PM PDT 24	Aug 10 08:25:03 PM PDT 24	2867773848 ps
T75	/workspace/coverage/default/2.chip_tap_straps_dev.2367510585			Aug 10 08:35:39 PM PDT 24	Aug 10 08:58:31 PM PDT 24	14128513609 ps
T109	/workspace/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg0.3540387169			Aug 10 08:12:01 PM PDT 24	Aug 10 08:17:20 PM PDT 24	2997275848 ps
T110	/workspace/coverage/default/96.chip_sw_all_escalation_resets.1919019360			Aug 10 08:51:38 PM PDT 24	Aug 10 09:00:54 PM PDT 24	4306070260 ps
T111	/workspace/coverage/default/2.chip_sw_power_idle_load.3629213485			Aug 10 08:38:03 PM PDT 24	Aug 10 08:50:10 PM PDT 24	4193401990 ps
T112	/workspace/coverage/default/0.chip_sw_rv_core_ibex_icache_invalidate.4262871467			Aug 10 08:17:03 PM PDT 24	Aug 10 08:22:18 PM PDT 24	3114322418 ps
T50	/workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.974208213			Aug 10 08:10:30 PM PDT 24	Aug 10 09:45:47 PM PDT 24	48221023250 ps
T238	/workspace/coverage/default/2.chip_sw_hmac_multistream.2665041487			Aug 10 08:35:27 PM PDT 24	Aug 10 08:59:31 PM PDT 24	6665913506 ps
T239	/workspace/coverage/default/1.chip_sw_otbn_randomness.608803617			Aug 10 08:22:43 PM PDT 24	Aug 10 08:36:55 PM PDT 24	6609829060 ps
T203	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_inputs.2321235527			Aug 10 08:20:59 PM PDT 24	Aug 10 08:26:08 PM PDT 24	3051608000 ps
T86	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.1576757791			Aug 10 08:11:44 PM PDT 24	Aug 10 08:36:41 PM PDT 24	11736302836 ps
T726	/workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.2780037013			Aug 10 08:47:24 PM PDT 24	Aug 10 08:55:38 PM PDT 24	3654741064 ps
T212	/workspace/coverage/default/2.chip_sw_i2c_device_tx_rx.1075388725			Aug 10 08:30:38 PM PDT 24	Aug 10 08:39:17 PM PDT 24	3807213006 ps
T51	/workspace/coverage/default/2.chip_sw_lc_ctrl_rand_to_scrap.939942224			Aug 10 08:30:34 PM PDT 24	Aug 10 08:34:15 PM PDT 24	3752235614 ps
T330	/workspace/coverage/default/81.chip_sw_all_escalation_resets.2239686132			Aug 10 08:49:18 PM PDT 24	Aug 10 09:00:46 PM PDT 24	5491682760 ps
T89	/workspace/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.1954499644			Aug 10 08:10:58 PM PDT 24	Aug 11 12:16:16 AM PDT 24	78807064408 ps
T217	/workspace/coverage/default/36.chip_sw_all_escalation_resets.3722316427			Aug 10 08:46:16 PM PDT 24	Aug 10 08:56:43 PM PDT 24	5322520900 ps
T126	/workspace/coverage/default/5.chip_sw_lc_ctrl_transition.710628435			Aug 10 08:42:59 PM PDT 24	Aug 10 09:01:29 PM PDT 24	11374153164 ps
T123	/workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.4136902857			Aug 10 08:14:07 PM PDT 24	Aug 10 08:32:57 PM PDT 24	5461909772 ps
T216	/workspace/coverage/default/4.chip_sw_data_integrity_escalation.415670257			Aug 10 08:41:44 PM PDT 24	Aug 10 08:52:14 PM PDT 24	5773492940 ps
T12	/workspace/coverage/default/2.chip_sw_spi_device_pass_through.1100679738			Aug 10 08:30:32 PM PDT 24	Aug 10 08:45:04 PM PDT 24	6685275461 ps
T905	/workspace/coverage/default/2.chip_sw_otp_ctrl_ecc_error_vendor_test.285669347			Aug 10 08:31:44 PM PDT 24	Aug 10 08:36:33 PM PDT 24	3166148929 ps
T906	/workspace/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.3891436979			Aug 10 08:10:24 PM PDT 24	Aug 10 08:18:21 PM PDT 24	4072945060 ps
T9	/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.3280785421			Aug 10 08:11:06 PM PDT 24	Aug 10 08:16:51 PM PDT 24	3435475603 ps
T176	/workspace/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.3387641170			Aug 10 08:20:26 PM PDT 24	Aug 10 08:26:08 PM PDT 24	4657279056 ps
T282	/workspace/coverage/default/1.chip_plic_all_irqs_20.267162680			Aug 10 08:25:39 PM PDT 24	Aug 10 08:38:22 PM PDT 24	4800846784 ps
T684	/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_por_reset.3989435896			Aug 10 08:21:54 PM PDT 24	Aug 10 08:35:45 PM PDT 24	7553300246 ps
T283	/workspace/coverage/default/95.chip_sw_all_escalation_resets.3494593639			Aug 10 08:52:49 PM PDT 24	Aug 10 09:02:17 PM PDT 24	5041862712 ps
T218	/workspace/coverage/default/52.chip_sw_all_escalation_resets.2387169639			Aug 10 08:47:46 PM PDT 24	Aug 10 08:58:03 PM PDT 24	5240663944 ps
T288	/workspace/coverage/default/0.chip_sw_csrng_kat_test.2044043708			Aug 10 08:13:13 PM PDT 24	Aug 10 08:16:17 PM PDT 24	2317143414 ps
T46	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.3035508811			Aug 10 08:21:38 PM PDT 24	Aug 10 09:14:36 PM PDT 24	14592679952 ps
T289	/workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.1303946376			Aug 10 08:49:25 PM PDT 24	Aug 10 08:55:12 PM PDT 24	3820994456 ps
T290	/workspace/coverage/default/2.rom_e2e_asm_init_test_unlocked0.2547770670			Aug 10 08:42:21 PM PDT 24	Aug 10 09:30:06 PM PDT 24	11180649550 ps
T169	/workspace/coverage/default/65.chip_sw_all_escalation_resets.3282270819			Aug 10 08:49:06 PM PDT 24	Aug 10 08:58:26 PM PDT 24	5221956038 ps
T291	/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.821790535			Aug 10 08:31:51 PM PDT 24	Aug 10 08:54:10 PM PDT 24	16532117936 ps
T73	/workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.964887743			Aug 10 08:13:57 PM PDT 24	Aug 10 08:22:24 PM PDT 24	5875553456 ps
T74	/workspace/coverage/default/4.chip_tap_straps_rma.3094837181			Aug 10 08:42:07 PM PDT 24	Aug 10 08:55:29 PM PDT 24	7930566592 ps
T260	/workspace/coverage/default/0.chip_sw_keymgr_key_derivation.373557692			Aug 10 08:14:57 PM PDT 24	Aug 10 08:42:33 PM PDT 24	9202252906 ps
T127	/workspace/coverage/default/1.chip_sw_lc_walkthrough_prodend.1412188278			Aug 10 08:20:04 PM PDT 24	Aug 10 08:38:24 PM PDT 24	10639338435 ps
T907	/workspace/coverage/default/2.chip_sw_clkmgr_sleep_frequency.3572856195			Aug 10 08:37:06 PM PDT 24	Aug 10 08:49:06 PM PDT 24	5179311800 ps
T318	/workspace/coverage/default/1.chip_sw_aon_timer_irq.447754642			Aug 10 08:29:11 PM PDT 24	Aug 10 08:36:59 PM PDT 24	4228855176 ps
T213	/workspace/coverage/default/17.chip_sw_uart_rand_baudrate.1215815848			Aug 10 08:45:58 PM PDT 24	Aug 10 09:24:10 PM PDT 24	13495777500 ps
T292	/workspace/coverage/default/12.chip_sw_all_escalation_resets.1758862511			Aug 10 08:44:06 PM PDT 24	Aug 10 08:55:58 PM PDT 24	5124522870 ps
T18	/workspace/coverage/default/0.chip_sw_usbdev_pincfg.2197779389			Aug 10 08:10:24 PM PDT 24	Aug 10 10:12:06 PM PDT 24	31550099568 ps
T133	/workspace/coverage/default/1.chip_sw_edn_kat.2375813862			Aug 10 08:23:32 PM PDT 24	Aug 10 08:36:54 PM PDT 24	3846985024 ps
T124	/workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en.3774753477			Aug 10 08:33:47 PM PDT 24	Aug 10 08:38:43 PM PDT 24	2901526494 ps
T19	/workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.91416857			Aug 10 08:12:32 PM PDT 24	Aug 10 08:20:53 PM PDT 24	3304104864 ps
T736	/workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.3269039891			Aug 10 08:47:18 PM PDT 24	Aug 10 08:53:00 PM PDT 24	4012050348 ps
T408	/workspace/coverage/default/0.chip_sw_kmac_mode_kmac.2455122348			Aug 10 08:13:18 PM PDT 24	Aug 10 08:18:25 PM PDT 24	3133395340 ps
T908	/workspace/coverage/default/0.chip_sw_aes_enc_jitter_en.3593596371			Aug 10 08:11:08 PM PDT 24	Aug 10 08:13:53 PM PDT 24	2525086027 ps
T13	/workspace/coverage/default/0.chip_sw_spi_device_pass_through.2522754936			Aug 10 08:13:52 PM PDT 24	Aug 10 08:24:33 PM PDT 24	5849070197 ps
T909	/workspace/coverage/default/1.chip_sw_example_manufacturer.2603435897			Aug 10 08:18:04 PM PDT 24	Aug 10 08:22:13 PM PDT 24	2809254692 ps
T910	/workspace/coverage/default/0.chip_sw_entropy_src_kat_test.4067546332			Aug 10 08:12:30 PM PDT 24	Aug 10 08:15:51 PM PDT 24	2944950344 ps
T738	/workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.2987024429			Aug 10 08:46:00 PM PDT 24	Aug 10 08:51:51 PM PDT 24	4022561980 ps
T379	/workspace/coverage/default/0.rom_e2e_smoke.3276025362			Aug 10 08:19:18 PM PDT 24	Aug 10 09:20:38 PM PDT 24	15035778724 ps
T349	/workspace/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.1746207399			Aug 10 08:40:08 PM PDT 24	Aug 10 09:21:18 PM PDT 24	24672439560 ps
T23	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.4109156035			Aug 10 08:21:54 PM PDT 24	Aug 10 08:52:17 PM PDT 24	22879333768 ps
T20	/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.130679918			Aug 10 08:27:19 PM PDT 24	Aug 10 08:59:49 PM PDT 24	25125872652 ps
T396	/workspace/coverage/default/1.chip_sw_uart_smoketest.2636088582			Aug 10 08:29:47 PM PDT 24	Aug 10 08:35:16 PM PDT 24	3134793520 ps
T17	/workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1356104440			Aug 10 08:20:04 PM PDT 24	Aug 10 08:42:44 PM PDT 24	8900879457 ps
T338	/workspace/coverage/default/98.chip_sw_all_escalation_resets.930404952			Aug 10 08:51:43 PM PDT 24	Aug 10 09:00:55 PM PDT 24	5369083116 ps
T397	/workspace/coverage/default/1.chip_sw_rstmgr_smoketest.3011003581			Aug 10 08:29:25 PM PDT 24	Aug 10 08:33:36 PM PDT 24	2970956000 ps
T179	/workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.3079740769			Aug 10 08:16:27 PM PDT 24	Aug 10 08:21:02 PM PDT 24	2565589020 ps
T373	/workspace/coverage/default/1.chip_sw_clkmgr_reset_frequency.3901137812			Aug 10 08:25:39 PM PDT 24	Aug 10 08:31:50 PM PDT 24	2866235148 ps
T69	/workspace/coverage/default/3.chip_tap_straps_testunlock0.3270860043			Aug 10 08:41:30 PM PDT 24	Aug 10 08:47:56 PM PDT 24	4902083265 ps
T374	/workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.3418777203			Aug 10 08:44:07 PM PDT 24	Aug 10 08:50:50 PM PDT 24	3999820816 ps
T214	/workspace/coverage/default/2.chip_sw_uart_rand_baudrate.1314874364			Aug 10 08:30:09 PM PDT 24	Aug 10 08:39:46 PM PDT 24	3906720120 ps
T128	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.3760597860			Aug 10 08:31:00 PM PDT 24	Aug 10 08:40:40 PM PDT 24	4683726512 ps
T375	/workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.231721879			Aug 10 08:49:20 PM PDT 24	Aug 10 08:56:23 PM PDT 24	3694098104 ps
T172	/workspace/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.1973020920			Aug 10 08:10:53 PM PDT 24	Aug 10 08:12:40 PM PDT 24	3312944009 ps
T181	/workspace/coverage/default/1.chip_sw_csrng_fuse_en_sw_app_read_test.1667087780			Aug 10 08:23:38 PM PDT 24	Aug 10 08:29:26 PM PDT 24	4373524612 ps
T117	/workspace/coverage/default/0.chip_sw_power_sleep_load.188074913			Aug 10 08:14:04 PM PDT 24	Aug 10 08:20:03 PM PDT 24	4162733490 ps
T225	/workspace/coverage/default/1.chip_sw_rv_timer_irq.1852761551			Aug 10 08:21:28 PM PDT 24	Aug 10 08:25:28 PM PDT 24	3246793750 ps
T705	/workspace/coverage/default/46.chip_sw_all_escalation_resets.652311608			Aug 10 08:46:17 PM PDT 24	Aug 10 08:58:04 PM PDT 24	6327434512 ps
T150	/workspace/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.3473643011			Aug 10 08:21:27 PM PDT 24	Aug 10 08:29:03 PM PDT 24	7204403699 ps
T134	/workspace/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.1593622433			Aug 10 08:33:51 PM PDT 24	Aug 10 08:45:59 PM PDT 24	5799117591 ps
T118	/workspace/coverage/default/1.chip_sw_ast_clk_rst_inputs.4229400459			Aug 10 08:29:52 PM PDT 24	Aug 10 09:31:47 PM PDT 24	23910658326 ps
T353	/workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.2889240215			Aug 10 08:45:03 PM PDT 24	Aug 10 08:53:56 PM PDT 24	3527738164 ps
T358	/workspace/coverage/default/0.chip_sw_coremark.1904810693			Aug 10 08:13:41 PM PDT 24	Aug 11 12:13:07 AM PDT 24	72196549574 ps
T341	/workspace/coverage/default/1.chip_sw_flash_ctrl_idle_low_power.1527222178			Aug 10 08:18:43 PM PDT 24	Aug 10 08:23:24 PM PDT 24	3332482024 ps
T261	/workspace/coverage/default/2.chip_sw_keymgr_sideload_otbn.1868547150			Aug 10 08:36:04 PM PDT 24	Aug 10 09:29:01 PM PDT 24	14532392086 ps
T348	/workspace/coverage/default/13.chip_sw_lc_ctrl_transition.2163312303			Aug 10 08:45:32 PM PDT 24	Aug 10 08:53:33 PM PDT 24	7251535866 ps
T359	/workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.1598050768			Aug 10 08:38:10 PM PDT 24	Aug 10 08:44:42 PM PDT 24	3588431516 ps
T360	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.440356785			Aug 10 08:14:36 PM PDT 24	Aug 10 08:52:19 PM PDT 24	9160022802 ps
T230	/workspace/coverage/default/0.chip_sw_edn_entropy_reqs.11116479			Aug 10 08:12:43 PM PDT 24	Aug 10 08:32:00 PM PDT 24	6536121264 ps
T361	/workspace/coverage/default/1.chip_sw_edn_sw_mode.703939420			Aug 10 08:22:57 PM PDT 24	Aug 10 08:43:15 PM PDT 24	6512860858 ps
T362	/workspace/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.3785782494			Aug 10 08:28:12 PM PDT 24	Aug 10 08:33:19 PM PDT 24	2728092840 ps
T321	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1400628861			Aug 10 08:15:04 PM PDT 24	Aug 10 08:26:56 PM PDT 24	4582637387 ps
T244	/workspace/coverage/default/1.chip_sw_otbn_mem_scramble.1719385357			Aug 10 08:31:36 PM PDT 24	Aug 10 08:38:10 PM PDT 24	3598887122 ps
T737	/workspace/coverage/default/2.chip_sw_clkmgr_reset_frequency.2222329595			Aug 10 08:35:55 PM PDT 24	Aug 10 08:43:31 PM PDT 24	3575914718 ps
T911	/workspace/coverage/default/2.chip_sw_pwrmgr_smoketest.2807288739			Aug 10 08:40:07 PM PDT 24	Aug 10 08:47:34 PM PDT 24	5197210280 ps
T912	/workspace/coverage/default/4.chip_sw_lc_ctrl_transition.2028116250			Aug 10 08:41:52 PM PDT 24	Aug 10 08:54:10 PM PDT 24	6832874312 ps
T380	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.614732449			Aug 10 08:20:27 PM PDT 24	Aug 10 09:12:19 PM PDT 24	10971153608 ps
T47	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.1646995399			Aug 10 08:19:20 PM PDT 24	Aug 10 09:22:46 PM PDT 24	14413999101 ps
T913	/workspace/coverage/default/1.chip_sw_hmac_multistream.3775921985			Aug 10 08:24:33 PM PDT 24	Aug 10 08:52:07 PM PDT 24	7779761632 ps
T914	/workspace/coverage/default/1.chip_sw_flash_ctrl_access.2067479623			Aug 10 08:20:50 PM PDT 24	Aug 10 08:37:30 PM PDT 24	5806470552 ps
T729	/workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.2139803028			Aug 10 08:48:13 PM PDT 24	Aug 10 08:54:56 PM PDT 24	3641478300 ps
T294	/workspace/coverage/default/1.chip_sw_uart_rand_baudrate.3304027878			Aug 10 08:18:48 PM PDT 24	Aug 10 08:52:57 PM PDT 24	8535209360 ps
T331	/workspace/coverage/default/90.chip_sw_all_escalation_resets.494243598			Aug 10 08:51:00 PM PDT 24	Aug 10 09:02:36 PM PDT 24	6245216160 ps
T82	/workspace/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3796476627			Aug 10 08:37:43 PM PDT 24	Aug 10 08:44:10 PM PDT 24	4306148504 ps
T146	/workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.3747788812			Aug 10 08:42:29 PM PDT 24	Aug 10 08:52:44 PM PDT 24	5755002276 ps
T727	/workspace/coverage/default/55.chip_sw_all_escalation_resets.757775412			Aug 10 08:48:04 PM PDT 24	Aug 10 08:59:08 PM PDT 24	5661096570 ps
T120	/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.1531698934			Aug 10 08:15:38 PM PDT 24	Aug 11 12:56:45 AM PDT 24	124213052947 ps
T752	/workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.313617803			Aug 10 08:42:45 PM PDT 24	Aug 10 08:51:30 PM PDT 24	4049081816 ps
T734	/workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.3821283715			Aug 10 08:47:02 PM PDT 24	Aug 10 08:54:16 PM PDT 24	3334663378 ps
T240	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.2135685737			Aug 10 08:22:06 PM PDT 24	Aug 10 09:22:42 PM PDT 24	13659731252 ps
T915	/workspace/coverage/default/0.chip_sw_hmac_enc_idle.1112330168			Aug 10 08:11:21 PM PDT 24	Aug 10 08:15:34 PM PDT 24	2622199840 ps
T304	/workspace/coverage/default/1.chip_sw_entropy_src_csrng.3491584885			Aug 10 08:26:21 PM PDT 24	Aug 10 08:46:13 PM PDT 24	5839550004 ps
T202	/workspace/coverage/default/1.chip_sw_uart_tx_rx_bootstrap.4052477365			Aug 10 08:18:19 PM PDT 24	Aug 11 12:07:17 AM PDT 24	78070850493 ps
T322	/workspace/coverage/default/2.chip_sival_flash_info_access.2721589378			Aug 10 08:29:52 PM PDT 24	Aug 10 08:36:18 PM PDT 24	3211323696 ps
T325	/workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en.2439249899			Aug 10 08:24:18 PM PDT 24	Aug 10 08:28:30 PM PDT 24	2560256241 ps
T916	/workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.380632540			Aug 10 08:41:57 PM PDT 24	Aug 10 08:47:30 PM PDT 24	6482857932 ps
T371	/workspace/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.2282600794			Aug 10 08:13:20 PM PDT 24	Aug 10 08:15:30 PM PDT 24	2191534328 ps
T323	/workspace/coverage/default/2.chip_sw_flash_ctrl_ops.2431958347			Aug 10 08:30:21 PM PDT 24	Aug 10 08:40:26 PM PDT 24	4289913802 ps
T917	/workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_no_meas.2516882935			Aug 10 08:20:38 PM PDT 24	Aug 10 09:24:20 PM PDT 24	14620915808 ps
T328	/workspace/coverage/default/0.chip_sw_pattgen_ios.4038924110			Aug 10 08:11:00 PM PDT 24	Aug 10 08:15:59 PM PDT 24	3129902254 ps
T918	/workspace/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg0.1458317838			Aug 10 08:33:14 PM PDT 24	Aug 10 08:38:06 PM PDT 24	2731187776 ps
T204	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_inputs.522957803			Aug 10 08:31:42 PM PDT 24	Aug 10 08:36:46 PM PDT 24	3098375692 ps
T818	/workspace/coverage/default/85.chip_sw_all_escalation_resets.855394819			Aug 10 08:49:12 PM PDT 24	Aug 10 08:59:46 PM PDT 24	6103244648 ps
T205	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_inputs.2463098393			Aug 10 08:11:25 PM PDT 24	Aug 10 08:16:36 PM PDT 24	2530244808 ps
T919	/workspace/coverage/default/2.chip_sw_rv_core_ibex_rnd.3709731322			Aug 10 08:34:35 PM PDT 24	Aug 10 08:55:26 PM PDT 24	5492836720 ps
T920	/workspace/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.4170846107			Aug 10 08:11:15 PM PDT 24	Aug 10 08:22:12 PM PDT 24	6809310334 ps
T724	/workspace/coverage/default/97.chip_sw_all_escalation_resets.1527007143			Aug 10 08:50:52 PM PDT 24	Aug 10 08:58:36 PM PDT 24	5499281680 ps
T245	/workspace/coverage/default/3.chip_sw_data_integrity_escalation.3482335369			Aug 10 08:42:18 PM PDT 24	Aug 10 08:52:18 PM PDT 24	5703828454 ps
T746	/workspace/coverage/default/88.chip_sw_all_escalation_resets.3840078170			Aug 10 08:49:55 PM PDT 24	Aug 10 08:57:40 PM PDT 24	4935397272 ps
T921	/workspace/coverage/default/1.chip_sw_alert_handler_lpg_clkoff.2082434207			Aug 10 08:24:29 PM PDT 24	Aug 10 08:57:55 PM PDT 24	7602279198 ps
T407	/workspace/coverage/default/0.chip_sw_alert_handler_ping_timeout.3965053442			Aug 10 08:12:47 PM PDT 24	Aug 10 08:17:46 PM PDT 24	3710064180 ps
T922	/workspace/coverage/default/2.chip_sw_clkmgr_smoketest.2359612456			Aug 10 08:39:10 PM PDT 24	Aug 10 08:43:46 PM PDT 24	2683827464 ps
T704	/workspace/coverage/default/2.chip_sw_rv_dm_access_after_wakeup.48122307			Aug 10 08:38:22 PM PDT 24	Aug 10 08:48:49 PM PDT 24	5489605296 ps
T342	/workspace/coverage/default/2.chip_sw_aon_timer_irq.1047427150			Aug 10 08:32:48 PM PDT 24	Aug 10 08:40:00 PM PDT 24	3692241368 ps
T220	/workspace/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.1377524448			Aug 10 08:26:36 PM PDT 24	Aug 10 08:34:21 PM PDT 24	4411685532 ps
T305	/workspace/coverage/default/0.chip_sw_entropy_src_csrng.409350966			Aug 10 08:13:40 PM PDT 24	Aug 10 08:43:44 PM PDT 24	7796120380 ps
T923	/workspace/coverage/default/1.chip_sw_sleep_pwm_pulses.1957185998			Aug 10 08:19:57 PM PDT 24	Aug 10 08:39:26 PM PDT 24	9107284652 ps
T177	/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.746742566			Aug 10 08:37:46 PM PDT 24	Aug 10 08:47:02 PM PDT 24	4940182300 ps
T739	/workspace/coverage/default/6.chip_sw_all_escalation_resets.501606992			Aug 10 08:42:41 PM PDT 24	Aug 10 08:51:23 PM PDT 24	5480121028 ps
T332	/workspace/coverage/default/73.chip_sw_all_escalation_resets.1082446425			Aug 10 08:48:16 PM PDT 24	Aug 10 08:59:04 PM PDT 24	5050851300 ps
T924	/workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_meas.3514326608			Aug 10 08:35:07 PM PDT 24	Aug 10 09:41:51 PM PDT 24	14300279414 ps
T925	/workspace/coverage/default/1.chip_sw_pwrmgr_smoketest.1187977855			Aug 10 08:29:21 PM PDT 24	Aug 10 08:39:54 PM PDT 24	6026571000 ps
T926	/workspace/coverage/default/2.chip_sw_rv_plic_smoketest.4038908161			Aug 10 08:40:09 PM PDT 24	Aug 10 08:44:09 PM PDT 24	2528350704 ps
T27	/workspace/coverage/default/1.chip_sw_gpio_smoketest.1825309371			Aug 10 08:29:16 PM PDT 24	Aug 10 08:35:47 PM PDT 24	3764593146 ps
T927	/workspace/coverage/default/2.chip_sw_aon_timer_wdog_lc_escalate.626058462			Aug 10 08:32:59 PM PDT 24	Aug 10 08:42:38 PM PDT 24	4788310332 ps
T368	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.296315015			Aug 10 08:25:36 PM PDT 24	Aug 10 10:16:55 PM PDT 24	24387743064 ps
T24	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.3281674267			Aug 10 08:34:39 PM PDT 24	Aug 10 09:34:41 PM PDT 24	20506609206 ps
T60	/workspace/coverage/default/2.chip_jtag_csr_rw.2703723971			Aug 10 08:29:05 PM PDT 24	Aug 10 09:04:11 PM PDT 24	21367928796 ps
T386	/workspace/coverage/default/53.chip_sw_all_escalation_resets.958170103			Aug 10 08:47:20 PM PDT 24	Aug 10 08:54:59 PM PDT 24	6026211432 ps
T387	/workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.347474440			Aug 10 08:37:23 PM PDT 24	Aug 10 09:00:26 PM PDT 24	7801403009 ps
T168	/workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.3040823167			Aug 10 08:09:56 PM PDT 24	Aug 10 09:44:09 PM PDT 24	49927021524 ps
T14	/workspace/coverage/default/0.chip_sw_spi_host_tx_rx.1822326119			Aug 10 08:11:52 PM PDT 24	Aug 10 08:15:37 PM PDT 24	2710947836 ps
T307	/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.3786719089			Aug 10 08:40:50 PM PDT 24	Aug 10 08:50:01 PM PDT 24	4716675520 ps
T129	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.1729220056			Aug 10 08:35:23 PM PDT 24	Aug 10 08:46:25 PM PDT 24	4386482640 ps
T388	/workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.2604184851			Aug 10 08:48:23 PM PDT 24	Aug 10 08:55:43 PM PDT 24	3617339336 ps
T389	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.1964463908			Aug 10 08:19:05 PM PDT 24	Aug 10 09:10:28 PM PDT 24	11360884040 ps
T226	/workspace/coverage/default/2.chip_sw_rv_timer_smoketest.3309066863			Aug 10 08:39:29 PM PDT 24	Aug 10 08:44:53 PM PDT 24	3040550908 ps
T928	/workspace/coverage/default/6.chip_sw_lc_ctrl_transition.3512985814			Aug 10 08:42:41 PM PDT 24	Aug 10 08:49:09 PM PDT 24	5677361681 ps
T326	/workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en.1359185486			Aug 10 08:14:40 PM PDT 24	Aug 10 08:18:48 PM PDT 24	2946431061 ps
T354	/workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.1017891518			Aug 10 08:45:22 PM PDT 24	Aug 10 08:50:34 PM PDT 24	3990704340 ps
T929	/workspace/coverage/default/0.rom_e2e_self_hash.660519512			Aug 10 08:22:11 PM PDT 24	Aug 10 09:59:02 PM PDT 24	25776696168 ps
T339	/workspace/coverage/default/43.chip_sw_all_escalation_resets.2890966324			Aug 10 08:46:37 PM PDT 24	Aug 10 09:00:50 PM PDT 24	4621244756 ps
T930	/workspace/coverage/default/0.rom_e2e_asm_init_prod.335848582			Aug 10 08:20:57 PM PDT 24	Aug 10 09:24:16 PM PDT 24	15191562279 ps
T409	/workspace/coverage/default/0.chip_sw_kmac_entropy.3914875176			Aug 10 08:12:18 PM PDT 24	Aug 10 08:16:38 PM PDT 24	3177705900 ps
T731	/workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.624688375			Aug 10 08:44:36 PM PDT 24	Aug 10 08:51:44 PM PDT 24	3920578636 ps
T157	/workspace/coverage/default/2.chip_sw_exit_test_unlocked_bootstrap.304470675			Aug 10 08:30:07 PM PDT 24	Aug 10 11:24:06 PM PDT 24	59484810038 ps
T262	/workspace/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.3553779991			Aug 10 08:10:21 PM PDT 24	Aug 10 08:16:41 PM PDT 24	4677965565 ps
T241	/workspace/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.3856440074			Aug 10 08:12:59 PM PDT 24	Aug 10 08:18:47 PM PDT 24	3643952282 ps
T931	/workspace/coverage/default/3.chip_tap_straps_rma.1390236355			Aug 10 08:40:24 PM PDT 24	Aug 10 08:52:35 PM PDT 24	6352010553 ps
T255	/workspace/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.1284754638			Aug 10 08:38:36 PM PDT 24	Aug 10 08:42:09 PM PDT 24	3034093611 ps
T206	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_outputs.2792586470			Aug 10 08:13:20 PM PDT 24	Aug 10 08:20:27 PM PDT 24	3207647886 ps
T383	/workspace/coverage/default/0.chip_sw_rom_ctrl_integrity_check.823825361			Aug 10 08:10:53 PM PDT 24	Aug 10 08:21:25 PM PDT 24	8829207800 ps
T932	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.3423068353			Aug 10 08:20:27 PM PDT 24	Aug 10 09:33:04 PM PDT 24	15907803560 ps
T242	/workspace/coverage/default/0.rom_volatile_raw_unlock.24871076			Aug 10 08:16:39 PM PDT 24	Aug 10 08:18:16 PM PDT 24	1866230919 ps
T266	/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_rma.549820315			Aug 10 08:10:23 PM PDT 24	Aug 10 08:30:58 PM PDT 24	9401840340 ps
T140	/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.4108738657			Aug 10 08:25:41 PM PDT 24	Aug 10 08:34:07 PM PDT 24	5369181240 ps
T823	/workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.4051673138			Aug 10 08:46:48 PM PDT 24	Aug 10 08:54:18 PM PDT 24	3855231060 ps
T231	/workspace/coverage/default/1.chip_sw_rstmgr_cpu_info.3136636796			Aug 10 08:21:00 PM PDT 24	Aug 10 08:30:12 PM PDT 24	5603640440 ps
T933	/workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_no_meas.3083181933			Aug 10 08:38:18 PM PDT 24	Aug 10 09:45:17 PM PDT 24	14361181800 ps
T934	/workspace/coverage/default/2.rom_e2e_shutdown_exception_c.403950456			Aug 10 08:42:07 PM PDT 24	Aug 10 09:34:44 PM PDT 24	14633137528 ps
T935	/workspace/coverage/default/1.chip_sw_power_sleep_load.3772222829			Aug 10 08:29:30 PM PDT 24	Aug 10 08:42:45 PM PDT 24	11353822424 ps
T936	/workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.3330488636			Aug 10 08:14:53 PM PDT 24	Aug 10 08:34:05 PM PDT 24	7252270505 ps
T91	/workspace/coverage/default/35.chip_sw_all_escalation_resets.3922241763			Aug 10 08:46:31 PM PDT 24	Aug 10 08:55:33 PM PDT 24	5761620582 ps
T44	/workspace/coverage/default/2.chip_sw_power_virus.1832713075			Aug 10 08:41:34 PM PDT 24	Aug 10 09:03:56 PM PDT 24	5637961896 ps
T96	/workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.437782020			Aug 10 08:10:58 PM PDT 24	Aug 10 08:19:11 PM PDT 24	4890555022 ps
T97	/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx1.258959179			Aug 10 08:40:33 PM PDT 24	Aug 10 08:53:31 PM PDT 24	4417528064 ps
T98	/workspace/coverage/default/5.chip_sw_data_integrity_escalation.3332795370			Aug 10 08:42:35 PM PDT 24	Aug 10 08:56:39 PM PDT 24	5270531152 ps
T99	/workspace/coverage/default/1.chip_sw_clkmgr_smoketest.4171162684			Aug 10 08:33:27 PM PDT 24	Aug 10 08:38:21 PM PDT 24	3442366936 ps
T100	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_rma.4019664033			Aug 10 08:20:48 PM PDT 24	Aug 10 09:50:13 PM PDT 24	22124770336 ps
T101	/workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.406787319			Aug 10 08:50:20 PM PDT 24	Aug 10 08:56:22 PM PDT 24	3502979500 ps
T102	/workspace/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.2111120926			Aug 10 08:20:46 PM PDT 24	Aug 10 08:57:08 PM PDT 24	31221192860 ps
T103	/workspace/coverage/default/0.chip_sw_plic_sw_irq.2141113			Aug 10 08:12:57 PM PDT 24	Aug 10 08:16:51 PM PDT 24	3279455948 ps
T937	/workspace/coverage/default/2.chip_sw_entropy_src_smoketest.768891734			Aug 10 08:40:08 PM PDT 24	Aug 10 08:51:14 PM PDT 24	3948959578 ps
T173	/workspace/coverage/default/2.chip_sw_lc_ctrl_program_error.4166286264			Aug 10 08:36:17 PM PDT 24	Aug 10 08:45:10 PM PDT 24	5539138560 ps
T740	/workspace/coverage/default/62.chip_sw_all_escalation_resets.1226927752			Aug 10 08:48:48 PM PDT 24	Aug 10 08:59:50 PM PDT 24	4509119748 ps
T10	/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.2350099096			Aug 10 08:18:50 PM PDT 24	Aug 10 08:24:54 PM PDT 24	3151339571 ps
T821	/workspace/coverage/default/51.chip_sw_all_escalation_resets.77558576			Aug 10 08:46:01 PM PDT 24	Aug 10 08:55:37 PM PDT 24	6091442782 ps
T728	/workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.1337809478			Aug 10 08:50:44 PM PDT 24	Aug 10 08:56:32 PM PDT 24	3511085826 ps