Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.spi_device_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	142400	1			T79	5		T80	6		T81	28
values[2]	10298	1			T137	5		T521	1		T391	4
values[3]	3895	1			T514	1		T517	9		T524	2
values[4]	2210	1			T514	1		T517	5		T524	1
values[5]	1380	1			T514	1		T517	3		T524	2
values[6]	1037	1			T514	1		T517	11		T524	3
values[7]	769	1			T514	1		T517	5		T524	4
values[8]	681	1			T514	1		T517	13		T524	4
values[9]	513	1			T514	1		T517	3		T524	1
values[10]	462	1			T514	1		T517	7		T524	2
values[11]	423	1			T514	1		T517	8		T524	1
values[12]	363	1			T514	1		T517	5		T524	2
values[13]	384	1			T514	1		T517	5		T524	2
values[14]	365	1			T514	1		T517	10		T524	2
values[15]	369	1			T514	1		T517	7		T524	4
values[16]	366	1			T514	1		T517	8		T524	2
values[17]	354	1			T514	1		T517	12		T524	2
values[18]	302	1			T514	1		T517	4		T524	1
values[19]	305	1			T514	1		T517	4		T524	5
values[20]	306	1			T514	1		T517	8		T524	3
values[21]	325	1			T514	1		T517	2		T524	3
values[22]	390	1			T514	1		T517	22		T524	3
values[23]	355	1			T514	1		T517	12		T524	2
values[24]	310	1			T514	1		T517	8		T524	6
values[25]	304	1			T514	1		T517	6		T524	1
values[26]	336	1			T514	1		T517	5		T524	1
values[27]	348	1			T514	1		T517	6		T524	3
values[28]	342	1			T514	1		T517	4		T524	1
values[29]	358	1			T514	1		T517	16		T524	6
values[30]	364	1			T514	1		T517	10		T524	7
values[31]	355	1			T514	1		T517	8		T524	2
values[32]	338	1			T514	1		T517	7		T524	1
values[33]	320	1			T514	1		T517	9		T524	2
values[34]	287	1			T514	1		T517	5		T524	1
values[35]	305	1			T514	1		T517	13		T524	2
values[36]	261	1			T514	1		T517	3		T524	2
values[37]	290	1			T514	1		T517	5		T524	2
values[38]	323	1			T514	1		T517	8		T524	1
values[39]	352	1			T514	1		T517	8		T524	3
values[40]	262	1			T514	1		T517	5		T524	7
values[41]	250	1			T514	1		T517	3		T524	3
values[42]	362	1			T514	1		T517	5		T524	8
values[43]	306	1			T514	1		T517	7		T524	13
values[44]	312	1			T514	1		T517	18		T524	6
values[45]	262	1			T514	1		T517	6		T524	4
values[46]	291	1			T514	1		T517	7		T524	3
values[47]	353	1			T514	1		T517	14		T524	1
values[48]	310	1			T514	1		T517	4		T524	1
values[49]	332	1			T514	1		T517	10		T524	1
values[50]	292	1			T514	1		T517	2		T524	2
values[51]	309	1			T514	1		T517	4		T524	3
values[52]	308	1			T514	1		T517	4		T524	1
values[53]	260	1			T514	1		T517	22		T524	1
values[54]	270	1			T514	1		T517	3		T524	3
values[55]	248	1			T514	1		T517	14		T524	1
values[56]	274	1			T514	1		T517	5		T524	1
values[57]	276	1			T514	2		T517	3		T524	3
values[58]	249	1			T514	1		T517	6		T524	5
values[59]	217	1			T514	1		T517	4		T524	2
values[60]	244	1			T514	1		T517	6		T524	3
values[61]	239	1			T514	1		T517	4		T524	1
values[62]	191	1			T514	1		T517	4		T524	4
values[63]	163	1			T514	1		T517	9		T524	2
values[64]	168	1			T514	1		T517	3		T524	2
values[65]	159	1			T514	1		T517	7		T524	2
values[66]	147	1			T514	1		T517	4		T524	1
values[67]	170	1			T514	1		T517	3		T524	2
values[68]	151	1			T514	1		T517	7		T524	2
values[69]	195	1			T514	1		T517	20		T524	9
values[70]	185	1			T514	1		T524	5		T830	1
values[71]	159	1			T514	1		T524	2		T830	1
values[72]	123	1			T514	1		T524	2		T830	1
values[73]	117	1			T514	1		T524	5		T830	1
values[74]	131	1			T514	1		T524	13		T830	1
values[75]	117	1			T514	1		T524	7		T830	1
values[76]	92	1			T514	1		T524	2		T830	1
values[77]	101	1			T514	1		T524	2		T830	1
values[78]	96	1			T514	1		T524	2		T830	1
values[79]	89	1			T514	1		T524	1		T830	1
values[80]	100	1			T514	1		T524	1		T830	1
values[81]	102	1			T514	1		T524	3		T830	1
values[82]	97	1			T514	1		T524	7		T830	1
values[83]	96	1			T514	1		T524	6		T830	1
values[84]	108	1			T514	1		T524	5		T830	1
values[85]	104	1			T514	1		T524	1		T830	1
values[86]	97	1			T514	1		T524	1		T830	1
values[87]	142	1			T514	1		T524	2		T830	1
values[88]	162	1			T514	1		T524	1		T830	1
values[89]	129	1			T514	1		T524	3		T830	1
values[90]	98	1			T514	1		T524	2		T830	1
values[91]	118	1			T514	1		T524	11		T830	1
values[92]	127	1			T514	1		T524	5		T830	1
values[93]	113	1			T514	1		T524	2		T830	1
values[94]	104	1			T514	1		T524	5		T830	2
values[95]	96	1			T514	1		T524	2		T830	1
values[96]	117	1			T514	1		T524	5		T830	4
values[97]	128	1			T514	1		T524	2		T830	2
values[98]	114	1			T514	1		T524	4		T830	5
values[99]	108	1			T514	1		T524	6		T830	1
values[100]	139	1			T514	1		T524	4		T830	1
values[101]	113	1			T514	1		T524	6		T830	3
values[102]	98	1			T514	1		T524	1		T830	1
values[103]	99	1			T514	1		T524	5		T830	1
values[104]	105	1			T514	1		T524	3		T830	1
values[105]	122	1			T514	1		T524	7		T830	2
values[106]	133	1			T514	1		T524	17		T830	3
values[107]	122	1			T514	1		T524	5		T830	1
values[108]	106	1			T514	1		T524	4		T830	6
values[109]	97	1			T514	1		T524	3		T830	1
values[110]	98	1			T514	1		T524	1		T830	1
values[111]	86	1			T514	1		T524	3		T830	1
values[112]	99	1			T514	1		T524	4		T830	1
values[113]	106	1			T514	1		T524	5		T830	1
values[114]	78	1			T514	1		T524	3		T830	3
values[115]	104	1			T514	1		T524	2		T830	6
values[116]	81	1			T514	1		T524	4		T830	1
values[117]	104	1			T514	1		T524	7		T830	1
values[118]	94	1			T514	1		T524	8		T830	1
values[119]	96	1			T514	1		T524	5		T830	3
values[120]	77	1			T514	1		T524	1		T830	1
values[121]	66	1			T514	1		T524	2		T830	1
values[122]	91	1			T514	1		T524	5		T830	1
values[123]	95	1			T514	1		T524	1		T830	2
values[124]	79	1			T514	1		T524	1		T830	1
values[125]	100	1			T514	2		T524	2		T830	2
values[126]	176	1			T514	2		T524	5		T830	1
values[127]	995	1			T514	34		T524	11		T830	26
values[128]	6750	1			T514	313		T524	2		T830	261