Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	50	0	50	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	50	0	50	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	50	0	50	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	479	1			T137	2		T391	1		T516	1
all_values[1]	475	1			T137	1		T391	1		T515	5
all_values[2]	478	1			T137	3		T391	1		T516	3
all_values[3]	477	1			T137	1		T391	1		T426	1
all_values[4]	454	1			T137	2		T426	1		T713	1
all_values[5]	454	1			T426	1		T516	1		T517	1
all_values[6]	469	1			T137	1		T391	1		T426	2
all_values[7]	439	1			T391	2		T426	1		T514	2
all_values[8]	442	1			T391	1		T516	2		T515	2
all_values[9]	433	1			T412	2		T137	2		T391	1
all_values[10]	475	1			T426	2		T519	1		T515	5
all_values[11]	468	1			T137	1		T391	1		T426	1
all_values[12]	442	1			T137	3		T516	1		T515	4
all_values[13]	455	1			T391	2		T677	1		T515	1
all_values[14]	467	1			T137	1		T391	3		T514	1
all_values[15]	459	1			T412	1		T137	1		T514	1
all_values[16]	424	1			T137	1		T391	1		T519	1
all_values[17]	498	1			T137	1		T391	1		T426	2
all_values[18]	435	1			T137	1		T516	2		T515	5
all_values[19]	472	1			T412	1		T137	2		T391	2
all_values[20]	484	1			T426	1		T516	2		T713	1
all_values[21]	454	1			T391	1		T517	1		T713	1
all_values[22]	478	1			T412	2		T137	1		T391	1
all_values[23]	450	1			T412	1		T137	1		T391	1
all_values[24]	480	1			T137	2		T391	1		T426	1
all_values[25]	501	1			T426	1		T516	4		T517	1
all_values[26]	460	1			T137	1		T391	2		T426	2
all_values[27]	461	1			T391	1		T713	1		T515	7
all_values[28]	465	1			T137	3		T391	3		T426	2
all_values[29]	456	1			T137	2		T391	2		T516	4
all_values[30]	450	1			T391	1		T514	1		T516	2
all_values[31]	471	1			T391	1		T516	1		T828	2
all_values[32]	463	1			T412	1		T137	1		T391	2
all_values[33]	488	1			T137	2		T426	1		T514	1
all_values[34]	439	1			T137	1		T391	2		T426	1
all_values[35]	488	1			T412	1		T391	3		T426	2
all_values[36]	448	1			T412	1		T137	1		T391	1
all_values[37]	472	1			T137	1		T391	1		T519	1
all_values[38]	453	1			T412	1		T516	4		T515	3
all_values[39]	473	1			T391	1		T426	1		T519	1
all_values[40]	438	1			T426	1		T516	2		T517	1
all_values[41]	472	1			T137	2		T514	1		T517	1
all_values[42]	459	1			T137	1		T519	1		T514	1
all_values[43]	489	1			T391	1		T426	1		T516	3
all_values[44]	415	1			T391	1		T516	2		T515	1
all_values[45]	509	1			T391	2		T516	1		T517	1
all_values[46]	449	1			T412	1		T137	2		T391	1
all_values[47]	475	1			T137	2		T391	4		T426	2
all_values[48]	479	1			T137	1		T426	1		T514	1
all_values[49]	480	1			T137	1		T516	3		T713	1