Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	3480	1			T137	4		T391	6		T426	2
all_values[1]	3506	1			T137	3		T391	7		T426	2
all_values[2]	3505	1			T137	5		T391	7		T426	4
all_values[3]	3537	1			T137	9		T391	1		T426	7
all_values[4]	3508	1			T137	1		T391	4		T426	4
all_values[5]	3574	1			T137	12		T391	1		T426	4
all_values[6]	3463	1			T137	3		T391	10		T426	6
all_values[7]	3409	1			T137	1		T391	5		T426	5
all_values[8]	3508	1			T137	3		T391	5		T426	4
all_values[9]	3511	1			T137	8		T391	6		T426	8
all_values[10]	3531	1			T137	2		T391	6		T426	7
all_values[11]	3558	1			T137	7		T391	1		T426	2
all_values[12]	3397	1			T137	2		T391	5		T426	5
all_values[13]	3401	1			T137	4		T391	2		T426	7
all_values[14]	3473	1			T137	5		T391	1		T426	4
all_values[15]	3595	1			T137	3		T391	3		T426	2
all_values[16]	3506	1			T137	2		T391	3		T520	2
all_values[17]	3435	1			T137	3		T391	3		T426	3
all_values[18]	3481	1			T137	2		T391	4		T426	3
all_values[19]	3510	1			T137	6		T391	6		T426	6
all_values[20]	3606	1			T137	1		T391	4		T426	4
all_values[21]	3492	1			T137	5		T391	2		T426	4
all_values[22]	3613	1			T137	4		T391	3		T426	5
all_values[23]	3574	1			T137	6		T391	6		T426	6
all_values[24]	3437	1			T137	5		T391	1		T426	4
all_values[25]	3509	1			T137	1		T391	3		T426	3
all_values[26]	3511	1			T137	6		T391	4		T426	6
all_values[27]	3434	1			T137	6		T391	8		T426	5
all_values[28]	3500	1			T137	2		T391	4		T426	5
all_values[29]	3530	1			T137	4		T391	5		T426	6
all_values[30]	3511	1			T137	4		T391	3		T426	1
all_values[31]	3409	1			T137	5		T391	3		T426	4
all_values[32]	3548	1			T137	3		T391	1		T426	8
all_values[33]	3541	1			T137	2		T391	5		T426	5
all_values[34]	3555	1			T137	4		T391	2		T426	3
all_values[35]	3472	1			T137	4		T391	4		T426	2
all_values[36]	3378	1			T137	5		T391	1		T426	5
all_values[37]	3527	1			T137	6		T391	4		T426	4
all_values[38]	3512	1			T137	6		T391	5		T426	4
all_values[39]	3525	1			T391	2		T426	7		T520	2
all_values[40]	3538	1			T137	4		T391	3		T426	7
all_values[41]	3521	1			T137	3		T391	4		T426	5
all_values[42]	3598	1			T137	6		T391	6		T426	2
all_values[43]	3594	1			T137	6		T391	8		T426	9
all_values[44]	3390	1			T137	11		T391	6		T426	6
all_values[45]	3475	1			T137	4		T426	4		T520	8
all_values[46]	3499	1			T137	8		T391	5		T426	6
all_values[47]	3506	1			T137	5		T391	6		T426	5
all_values[48]	3434	1			T137	2		T391	10		T426	4
all_values[49]	3391	1			T137	4		T391	7		T426	12
all_values[50]	3570	1			T137	6		T391	2		T426	7
all_values[51]	3510	1			T137	4		T391	5		T426	3
all_values[52]	3538	1			T137	1		T391	3		T426	2
all_values[53]	3523	1			T137	2		T391	1		T426	2
all_values[54]	3517	1			T137	4		T391	5		T426	5
all_values[55]	3379	1			T137	5		T391	2		T426	2
all_values[56]	3605	1			T137	7		T391	2		T426	8
all_values[57]	3559	1			T137	3		T391	2		T426	5
all_values[58]	3456	1			T137	4		T391	2		T426	5
all_values[59]	3507	1			T137	6		T391	2		T426	3
all_values[60]	3426	1			T137	2		T391	6		T426	2
all_values[61]	3572	1			T137	6		T391	10		T426	9
all_values[62]	3544	1			T137	1		T391	1		T426	5
all_values[63]	3461	1			T137	4		T391	6		T426	7