Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.usbdev_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	145164	1			T70	79		T71	6		T72	3
values[2]	7701	1			T70	1		T139	3		T447	4
values[3]	3682	1			T447	1		T564	67		T679	1
values[4]	2285	1			T564	43		T742	11		T627	51
values[5]	1453	1			T564	21		T742	3		T627	35
values[6]	1084	1			T564	43		T742	18		T627	36
values[7]	855	1			T564	24		T742	9		T627	50
values[8]	762	1			T564	11		T742	4		T627	42
values[9]	734	1			T564	5		T742	14		T627	26
values[10]	717	1			T564	1		T742	5		T627	14
values[11]	643	1			T742	3		T627	21		T486	1
values[12]	713	1			T742	6		T627	17		T486	1
values[13]	616	1			T742	15		T627	17		T486	1
values[14]	691	1			T742	5		T627	17		T486	1
values[15]	737	1			T742	11		T627	21		T486	1
values[16]	699	1			T742	10		T627	19		T486	2
values[17]	734	1			T742	9		T627	38		T486	1
values[18]	619	1			T742	10		T627	16		T486	1
values[19]	650	1			T742	5		T627	21		T486	1
values[20]	589	1			T742	7		T627	30		T486	1
values[21]	566	1			T742	17		T627	22		T486	1
values[22]	598	1			T742	12		T627	19		T486	1
values[23]	517	1			T742	9		T627	12		T486	1
values[24]	541	1			T742	9		T627	22		T486	1
values[25]	514	1			T742	15		T627	18		T486	1
values[26]	538	1			T742	33		T627	13		T486	1
values[27]	503	1			T742	13		T627	11		T486	1
values[28]	463	1			T742	6		T627	22		T486	1
values[29]	448	1			T742	12		T627	17		T486	1
values[30]	453	1			T742	15		T627	21		T486	1
values[31]	458	1			T742	10		T627	12		T486	1
values[32]	424	1			T742	4		T627	16		T486	1
values[33]	407	1			T742	10		T627	37		T486	1
values[34]	399	1			T742	5		T627	45		T486	1
values[35]	412	1			T742	11		T627	21		T486	1
values[36]	430	1			T742	11		T627	17		T486	1
values[37]	394	1			T742	8		T627	21		T486	1
values[38]	383	1			T742	6		T627	17		T486	1
values[39]	369	1			T742	5		T627	12		T486	1
values[40]	385	1			T742	9		T627	10		T486	1
values[41]	348	1			T742	6		T627	36		T486	1
values[42]	365	1			T742	12		T627	15		T486	1
values[43]	331	1			T742	8		T627	26		T486	1
values[44]	329	1			T742	9		T627	19		T486	1
values[45]	276	1			T627	4		T486	1		T909	29
values[46]	277	1			T627	10		T486	1		T909	16
values[47]	254	1			T627	10		T486	1		T909	8
values[48]	211	1			T627	8		T486	1		T909	7
values[49]	207	1			T627	8		T486	1		T936	6
values[50]	191	1			T627	8		T486	1		T936	5
values[51]	175	1			T627	13		T486	1		T902	1
values[52]	152	1			T627	3		T486	1		T902	2
values[53]	91	1			T627	5		T486	1		T902	1
values[54]	90	1			T486	1		T902	1		T929	1
values[55]	85	1			T486	1		T902	1		T929	1
values[56]	100	1			T486	1		T902	1		T929	1
values[57]	99	1			T486	1		T902	1		T929	1
values[58]	88	1			T486	1		T902	1		T929	1
values[59]	87	1			T486	1		T902	1		T929	1
values[60]	82	1			T486	1		T902	1		T929	1
values[61]	70	1			T486	1		T902	1		T929	1
values[62]	101	1			T486	1		T902	1		T929	1
values[63]	106	1			T486	1		T902	1		T929	1
values[64]	106	1			T486	1		T902	1		T929	1
values[65]	98	1			T486	1		T902	1		T929	1
values[66]	91	1			T486	1		T902	1		T929	1
values[67]	102	1			T486	1		T902	1		T929	1
values[68]	114	1			T486	1		T902	1		T929	1
values[69]	112	1			T486	1		T902	1		T929	1
values[70]	108	1			T486	1		T902	1		T929	1
values[71]	120	1			T486	1		T902	1		T929	1
values[72]	115	1			T486	1		T902	1		T929	1
values[73]	129	1			T486	1		T902	1		T929	1
values[74]	121	1			T486	1		T902	1		T929	1
values[75]	142	1			T486	1		T902	1		T929	1
values[76]	160	1			T486	1		T902	1		T929	1
values[77]	128	1			T486	1		T902	1		T929	1
values[78]	129	1			T486	1		T902	1		T929	1
values[79]	118	1			T486	1		T902	1		T929	1
values[80]	102	1			T486	1		T902	1		T929	1
values[81]	131	1			T486	1		T902	2		T929	1
values[82]	157	1			T486	1		T902	1		T929	1
values[83]	144	1			T486	1		T902	1		T929	1
values[84]	136	1			T486	1		T902	1		T929	1
values[85]	120	1			T486	1		T902	1		T929	1
values[86]	101	1			T486	1		T902	1		T929	1
values[87]	75	1			T486	1		T902	1		T929	1
values[88]	64	1			T486	1		T902	1		T929	1
values[89]	67	1			T486	1		T902	1		T929	1
values[90]	52	1			T486	1		T902	1		T929	1
values[91]	44	1			T486	1		T902	1		T929	2
values[92]	45	1			T486	1		T902	1		T929	1
values[93]	44	1			T486	1		T902	1		T929	2
values[94]	32	1			T486	1		T902	1		T929	4
values[95]	32	1			T486	1		T902	1		T929	1
values[96]	32	1			T486	1		T902	1		T929	1
values[97]	34	1			T486	1		T902	1		T929	3
values[98]	26	1			T486	1		T902	1		T929	2
values[99]	32	1			T486	1		T902	1		T929	4
values[100]	23	1			T486	1		T902	1		T929	2
values[101]	29	1			T486	1		T902	1		T929	1
values[102]	26	1			T486	1		T902	1		T929	1
values[103]	40	1			T486	1		T902	2		T929	2
values[104]	40	1			T486	1		T902	3		T929	3
values[105]	59	1			T486	2		T902	1		T929	3
values[106]	36	1			T486	1		T902	2		T929	2
values[107]	35	1			T486	1		T902	2		T929	1
values[108]	20	1			T486	1		T902	1		T929	2
values[109]	24	1			T486	1		T902	1		T929	1
values[110]	22	1			T486	1		T902	3		T929	1
values[111]	28	1			T486	1		T902	1		T929	4
values[112]	32	1			T486	1		T902	2		T929	4
values[113]	33	1			T486	1		T902	1		T929	2
values[114]	26	1			T486	1		T902	2		T929	1
values[115]	25	1			T486	1		T902	2		T929	3
values[116]	19	1			T486	1		T902	1		T929	1
values[117]	22	1			T486	1		T902	2		T929	1
values[118]	29	1			T486	1		T902	2		T929	2
values[119]	28	1			T486	1		T902	4		T929	3
values[120]	24	1			T486	1		T902	1		T929	2
values[121]	23	1			T486	1		T902	2		T929	1
values[122]	24	1			T486	1		T902	1		T929	1
values[123]	31	1			T486	3		T902	4		T929	1
values[124]	22	1			T486	1		T902	1		T929	2
values[125]	33	1			T486	1		T902	1		T929	6
values[126]	70	1			T486	6		T902	7		T929	7
values[127]	759	1			T486	41		T902	50		T929	39
values[128]	3906	1			T486	299		T902	271		T929	273