Total Coverage Summary 

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.01	95.47	93.71	95.33		94.52	97.53	99.51

Total tests in report: 2938

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Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
39.46	39.46	45.70	45.70	43.93	43.93	25.04	25.04			58.70	58.70	63.29	63.29	0.13	0.13	/workspace/coverage/default/1.chip_sw_spi_device_pinmux_sleep_retention.2016531299
49.78	10.32	57.52	11.83	56.30	12.37	30.38	5.34			67.65	8.95	85.31	22.03	1.54	1.41	/workspace/coverage/cover_reg_top/17.chip_same_csr_outstanding.3679089133
56.20	6.41	70.98	13.45	65.37	9.07	33.83	3.45			80.15	12.50	85.31	0.00	1.54	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_0.1130879038
60.20	4.00	70.98	0.00	65.48	0.11	33.83	0.00			80.20	0.05	85.31	0.00	25.37	23.83	/workspace/coverage/cover_reg_top/13.xbar_access_same_device_slow_rsp.2529207858
63.64	3.45	71.00	0.02	65.50	0.02	54.26	20.43			80.23	0.02	85.49	0.17	25.38	0.01	/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.3512551934
66.93	3.29	74.24	3.24	67.40	1.90	57.68	3.42			80.39	0.16	85.49	0.00	36.39	11.01	/workspace/coverage/cover_reg_top/73.xbar_stress_all_with_reset_error.2203738123
70.11	3.18	79.55	5.31	71.27	3.87	61.25	3.57			82.15	1.76	90.03	4.55	36.39	0.00	/workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.301949197
72.99	2.89	79.55	0.00	71.56	0.30	61.25	0.00			82.28	0.13	90.03	0.00	53.28	16.90	/workspace/coverage/cover_reg_top/78.xbar_access_same_device_slow_rsp.121574984
75.07	2.08	79.55	0.00	71.58	0.01	61.25	0.00			82.28	0.00	90.03	0.00	65.73	12.44	/workspace/coverage/cover_reg_top/54.xbar_stress_all_with_reset_error.1145942235
77.10	2.03	81.79	2.25	74.22	2.64	66.35	5.10			84.11	1.83	90.38	0.35	65.73	0.00	/workspace/coverage/default/1.rom_e2e_static_critical.499291336
78.80	1.70	82.08	0.29	74.37	0.16	75.35	9.00			84.29	0.18	90.91	0.52	65.77	0.05	/workspace/coverage/default/1.chip_sw_lc_walkthrough_dev.908328186
80.40	1.60	84.99	2.91	77.72	3.35	75.69	0.34			87.30	3.01	90.91	0.00	65.77	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.3006372355
81.81	1.41	84.99	0.00	77.72	0.00	75.69	0.00			87.30	0.00	90.91	0.00	74.23	8.46	/workspace/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.811954867
83.05	1.24	86.90	1.91	78.71	0.99	79.07	3.38			88.11	0.81	91.26	0.35	74.23	0.00	/workspace/coverage/default/0.chip_sw_power_virus.4259293972
84.07	1.03	86.90	0.00	78.71	0.00	79.07	0.00			88.11	0.00	91.26	0.00	80.39	6.16	/workspace/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.3726766225
85.01	0.93	86.91	0.01	83.88	5.17	79.07	0.00			88.11	0.00	91.26	0.00	80.80	0.41	/workspace/coverage/cover_reg_top/28.chip_tl_errors.3893366837
85.87	0.86	87.73	0.82	84.10	0.22	79.08	0.01			88.38	0.27	95.10	3.85	80.80	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.2868650229
86.68	0.82	87.73	0.00	84.10	0.00	79.08	0.00			88.38	0.00	95.10	0.00	85.70	4.90	/workspace/coverage/cover_reg_top/99.xbar_access_same_device_slow_rsp.2057645992
87.48	0.79	88.50	0.77	84.92	0.81	80.31	1.23			88.96	0.58	95.10	0.00	87.06	1.36	/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.3530554488
88.22	0.75	89.23	0.73	85.62	0.71	82.37	2.05			89.75	0.80	95.28	0.17	87.10	0.04	/workspace/coverage/default/2.chip_sw_ast_clk_rst_inputs.3360732113
88.95	0.72	90.50	1.27	86.69	1.07	83.09	0.72			91.02	1.27	95.28	0.00	87.10	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_20.291310340
89.61	0.67	90.50	0.00	86.69	0.00	83.09	0.00			91.02	0.00	95.28	0.00	91.11	4.01	/workspace/coverage/cover_reg_top/81.xbar_access_same_device_slow_rsp.1077629295
90.20	0.59	90.50	0.00	86.69	0.00	86.61	3.53			91.02	0.00	95.28	0.00	91.11	0.00	/workspace/coverage/default/0.chip_sw_keymgr_sideload_kmac.3490105086
90.78	0.58	91.09	0.58	87.73	1.04	86.64	0.03			91.72	0.70	96.33	1.05	91.18	0.07	/workspace/coverage/cover_reg_top/18.chip_same_csr_outstanding.814119149
91.25	0.47	91.68	0.59	87.74	0.01	86.75	0.11			91.72	0.00	96.33	0.00	93.30	2.13	/workspace/coverage/cover_reg_top/25.xbar_stress_all_with_reset_error.4206100693
91.64	0.39	92.39	0.71	88.22	0.47	87.43	0.68			92.18	0.46	96.33	0.00	93.30	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_10.301086571
91.98	0.34	92.39	0.00	88.23	0.01	87.43	0.00			92.18	0.00	96.33	0.00	95.31	2.01	/workspace/coverage/cover_reg_top/44.xbar_stress_all.3734953883
92.29	0.31	93.00	0.62	88.67	0.44	87.85	0.42			92.58	0.40	96.33	0.00	95.31	0.00	/workspace/coverage/default/1.chip_sw_gpio_smoketest.963460397
92.54	0.26	93.47	0.46	89.15	0.49	88.21	0.36			92.80	0.22	96.33	0.00	95.31	0.00	/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3967466659
92.80	0.25	93.47	0.00	89.21	0.06	88.21	0.00			92.82	0.02	96.33	0.00	96.76	1.45	/workspace/coverage/cover_reg_top/48.xbar_random_large_delays.2047553940
93.03	0.23	93.59	0.13	89.29	0.08	89.15	0.94			92.88	0.06	96.33	0.00	96.93	0.18	/workspace/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.3093151122
93.24	0.21	93.59	0.00	89.29	0.00	90.38	1.24			92.88	0.00	96.33	0.00	96.93	0.00	/workspace/coverage/default/0.chip_sw_flash_rma_unlocked.1685483244
93.43	0.19	93.59	0.00	89.29	0.00	91.55	1.16			92.88	0.00	96.33	0.00	96.93	0.00	/workspace/coverage/default/2.chip_sw_csrng_edn_concurrency.4190704590
93.58	0.15	93.66	0.07	89.68	0.39	91.60	0.05			93.31	0.42	96.33	0.00	96.93	0.00	/workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.2836017430
93.73	0.14	93.66	0.00	90.53	0.85	91.60	0.00			93.31	0.00	96.33	0.00	96.93	0.00	/workspace/coverage/cover_reg_top/27.chip_tl_errors.1304240610
93.85	0.13	93.71	0.06	90.53	0.00	92.29	0.70			93.31	0.01	96.33	0.00	96.93	0.00	/workspace/coverage/default/2.chip_jtag_mem_access.231191208
93.97	0.12	93.71	0.00	90.53	0.00	92.29	0.00			93.31	0.00	96.33	0.00	97.64	0.70	/workspace/coverage/cover_reg_top/28.xbar_access_same_device.3402294721
94.07	0.10	93.72	0.01	90.82	0.29	92.30	0.01			93.64	0.32	96.33	0.00	97.64	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.2148404899
94.18	0.10	93.77	0.05	90.88	0.06	92.43	0.13			93.64	0.00	96.33	0.00	98.03	0.39	/workspace/coverage/default/0.chip_sw_alert_test.4106852054
94.27	0.09	93.84	0.07	90.97	0.09	92.57	0.14			93.70	0.06	96.50	0.17	98.03	0.00	/workspace/coverage/default/0.chip_sw_data_integrity_escalation.834623977
94.35	0.08	93.99	0.15	91.08	0.11	92.67	0.10			93.82	0.12	96.50	0.00	98.03	0.00	/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.1215074879
94.43	0.08	93.99	0.00	91.09	0.01	93.14	0.46			93.82	0.00	96.50	0.00	98.03	0.00	/workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.935505218
94.50	0.07	93.99	0.00	91.11	0.03	93.38	0.24			93.82	0.00	96.68	0.17	98.03	0.00	/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.1006510655
94.57	0.07	94.09	0.11	91.33	0.21	93.38	0.00			93.89	0.07	96.68	0.00	98.03	0.00	/workspace/coverage/cover_reg_top/0.chip_same_csr_outstanding.1262990194
94.63	0.07	94.21	0.12	91.43	0.10	93.44	0.06			94.00	0.11	96.68	0.00	98.03	0.00	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.3667746399
94.69	0.06	94.21	0.00	91.43	0.00	93.78	0.34			94.00	0.00	96.68	0.00	98.03	0.00	/workspace/coverage/default/2.chip_sw_lc_walkthrough_prod.595179942
94.73	0.05	94.29	0.08	91.49	0.06	93.82	0.04			94.00	0.00	96.68	0.00	98.12	0.09	/workspace/coverage/cover_reg_top/74.xbar_random.3152511859
94.78	0.04	94.32	0.03	91.52	0.02	93.82	0.01			94.03	0.03	96.85	0.17	98.12	0.00	/workspace/coverage/default/1.chip_sw_rstmgr_cpu_info.2013970091
94.82	0.04	94.33	0.01	91.53	0.01	93.84	0.02			94.05	0.02	97.03	0.17	98.13	0.01	/workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.673267825
94.86	0.04	94.33	0.00	91.79	0.25	93.84	0.00			94.05	0.00	97.03	0.00	98.13	0.00	/workspace/coverage/cover_reg_top/16.chip_tl_errors.909913195
94.90	0.04	94.35	0.02	91.95	0.17	93.86	0.02			94.10	0.05	97.03	0.00	98.13	0.00	/workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.3777155210
94.95	0.04	94.36	0.01	91.97	0.02	93.89	0.03			94.11	0.01	97.20	0.17	98.14	0.01	/workspace/coverage/default/16.chip_sw_all_escalation_resets.769196728
94.98	0.04	94.36	0.00	92.00	0.03	93.89	0.00			94.13	0.02	97.20	0.00	98.32	0.18	/workspace/coverage/cover_reg_top/82.xbar_stress_all_with_rand_reset.3157906970
95.02	0.04	94.36	0.01	92.02	0.02	93.89	0.00			94.13	0.01	97.38	0.17	98.33	0.01	/workspace/coverage/default/98.chip_sw_all_escalation_resets.339553505
95.06	0.04	94.37	0.01	92.03	0.01	93.90	0.01			94.14	0.01	97.55	0.17	98.34	0.01	/workspace/coverage/default/12.chip_sw_all_escalation_resets.310231964
95.09	0.04	94.37	0.00	92.03	0.00	94.11	0.21			94.14	0.00	97.55	0.00	98.34	0.00	/workspace/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.915996410
95.12	0.03	94.38	0.01	92.06	0.02	94.25	0.14			94.14	0.00	97.55	0.00	98.36	0.01	/workspace/coverage/default/1.chip_sw_uart_tx_rx_bootstrap.3853935611
95.15	0.03	94.45	0.07	92.09	0.03	94.27	0.02			94.19	0.05	97.55	0.00	98.36	0.00	/workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.3473786518
95.18	0.03	94.45	0.00	92.09	0.00	94.44	0.17			94.19	0.00	97.55	0.00	98.36	0.00	/workspace/coverage/default/1.chip_sw_flash_rma_unlocked.3860141255
95.21	0.03	94.45	0.00	92.20	0.11	94.44	0.00			94.22	0.03	97.55	0.00	98.38	0.02	/workspace/coverage/cover_reg_top/33.xbar_stress_all_with_rand_reset.1870645694
95.23	0.03	94.45	0.00	92.28	0.08	94.44	0.00			94.30	0.07	97.55	0.00	98.38	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_retention.3379429641
95.26	0.02	94.46	0.01	92.28	0.01	94.57	0.13			94.30	0.01	97.55	0.00	98.38	0.00	/workspace/coverage/cover_reg_top/3.chip_csr_hw_reset.1196988682
95.28	0.02	94.46	0.00	92.33	0.05	94.57	0.00			94.32	0.02	97.55	0.00	98.46	0.08	/workspace/coverage/cover_reg_top/14.xbar_stress_all_with_rand_reset.576250346
95.31	0.02	94.52	0.07	92.38	0.05	94.57	0.00			94.35	0.03	97.55	0.00	98.46	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_wake.459664778
95.33	0.02	94.59	0.07	92.43	0.05	94.57	0.00			94.39	0.03	97.55	0.00	98.46	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_wake.22260587
95.35	0.02	94.59	0.00	92.57	0.14	94.57	0.00			94.39	0.00	97.55	0.00	98.46	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_0.2562905223
95.38	0.02	94.66	0.07	92.57	0.00	94.63	0.06			94.39	0.01	97.55	0.00	98.46	0.00	/workspace/coverage/default/3.chip_tap_straps_testunlock0.2694642405
95.40	0.02	94.66	0.00	92.57	0.00	94.76	0.13			94.39	0.00	97.55	0.00	98.46	0.00	/workspace/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.883024651
95.42	0.02	94.72	0.07	92.62	0.05	94.76	0.00			94.41	0.02	97.55	0.00	98.46	0.00	/workspace/coverage/default/2.chip_sw_sleep_pin_wake.2428568183
95.44	0.02	94.72	0.00	92.74	0.12	94.76	0.00			94.41	0.00	97.55	0.00	98.46	0.00	/workspace/coverage/cover_reg_top/20.chip_tl_errors.3242559225
95.46	0.02	94.72	0.00	92.85	0.11	94.76	0.00			94.41	0.00	97.55	0.00	98.46	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_0.3189075814
95.47	0.02	94.72	0.00	92.88	0.04	94.76	0.00			94.41	0.00	97.55	0.00	98.52	0.06	/workspace/coverage/cover_reg_top/53.xbar_stress_all_with_rand_reset.1523695270
95.49	0.02	94.72	0.00	92.98	0.09	94.76	0.00			94.41	0.00	97.55	0.00	98.52	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_20.2116303805
95.50	0.02	94.75	0.03	93.01	0.04	94.76	0.00			94.43	0.02	97.55	0.00	98.52	0.00	/workspace/coverage/cover_reg_top/15.chip_csr_rw.1189808169
95.52	0.01	94.79	0.03	93.03	0.02	94.78	0.02			94.44	0.01	97.55	0.00	98.52	0.00	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.4040621421
95.53	0.01	94.79	0.00	93.07	0.04	94.78	0.00			94.44	0.00	97.55	0.00	98.57	0.05	/workspace/coverage/cover_reg_top/17.xbar_stress_all_with_rand_reset.4256504670
95.55	0.01	94.79	0.00	93.07	0.00	94.86	0.08			94.44	0.00	97.55	0.00	98.57	0.00	/workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.2140335287
95.56	0.01	94.79	0.00	93.07	0.00	94.93	0.07			94.44	0.00	97.55	0.00	98.57	0.00	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.1462977618
95.57	0.01	94.79	0.00	93.07	0.01	94.93	0.00			94.44	0.00	97.55	0.00	98.63	0.06	/workspace/coverage/cover_reg_top/72.xbar_stress_all_with_reset_error.3317449165
95.58	0.01	94.80	0.01	93.10	0.03	94.93	0.01			94.46	0.02	97.55	0.00	98.63	0.00	/workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.4186994532
95.59	0.01	94.82	0.02	93.11	0.01	94.94	0.01			94.47	0.02	97.55	0.00	98.63	0.00	/workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.123210562
95.60	0.01	94.84	0.02	93.12	0.01	94.95	0.01			94.49	0.02	97.55	0.00	98.63	0.00	/workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.1285343524
95.60	0.01	94.87	0.02	93.12	0.01	94.95	0.01			94.51	0.02	97.55	0.00	98.63	0.00	/workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.2018118176
95.61	0.01	94.87	0.00	93.17	0.05	94.95	0.00			94.51	0.00	97.55	0.00	98.63	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_10.1195766737
95.62	0.01	94.87	0.00	93.22	0.05	94.95	0.00			94.51	0.00	97.55	0.00	98.63	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_20.1847850585
95.63	0.01	94.87	0.00	93.23	0.01	94.99	0.04			94.51	0.00	97.55	0.00	98.63	0.00	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod.1606864587
95.64	0.01	94.87	0.00	93.28	0.05	94.99	0.00			94.51	0.00	97.55	0.00	98.63	0.00	/workspace/coverage/cover_reg_top/87.xbar_stress_all.3454244384
95.64	0.01	94.87	0.00	93.28	0.00	95.03	0.04			94.51	0.00	97.55	0.00	98.63	0.00	/workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.2650783300
95.65	0.01	94.87	0.00	93.30	0.03	95.03	0.00			94.51	0.00	97.55	0.00	98.64	0.01	/workspace/coverage/cover_reg_top/4.chip_tl_errors.278005626
95.66	0.01	94.87	0.00	93.30	0.00	95.07	0.04			94.51	0.00	97.55	0.00	98.64	0.00	/workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.3700231784
95.66	0.01	94.87	0.00	93.31	0.01	95.07	0.00			94.51	0.00	97.55	0.00	98.67	0.04	/workspace/coverage/cover_reg_top/55.xbar_stress_all_with_reset_error.668529584
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95.76	0.01	94.89	0.00	93.55	0.00	95.23	0.00			94.52	0.00	97.55	0.00	98.80	0.01	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.41412385
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95.76	0.01	94.89	0.00	93.55	0.00	95.23	0.00			94.52	0.00	97.55	0.00	98.83	0.01	/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.350684244
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95.76	0.01	94.89	0.00	93.55	0.00	95.23	0.00			94.52	0.00	97.55	0.00	98.85	0.01	/workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.3679198833
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95.77	0.01	94.89	0.00	93.55	0.00	95.23	0.00			94.52	0.00	97.55	0.00	98.87	0.01	/workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.965536084
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95.77	0.01	94.89	0.00	93.55	0.00	95.23	0.00			94.52	0.00	97.55	0.00	98.90	0.01	/workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.1530104545
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95.78	0.01	94.89	0.00	93.55	0.00	95.23	0.00			94.52	0.00	97.55	0.00	98.97	0.01	/workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.854048136
95.79	0.01	94.89	0.00	93.55	0.00	95.23	0.00			94.52	0.00	97.55	0.00	98.98	0.01	/workspace/coverage/default/18.chip_sw_all_escalation_resets.3134890459
95.79	0.01	94.89	0.00	93.55	0.00	95.23	0.00			94.52	0.00	97.55	0.00	98.99	0.01	/workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.1688892588
95.79	0.01	94.89	0.00	93.55	0.00	95.23	0.00			94.52	0.00	97.55	0.00	99.00	0.01	/workspace/coverage/default/19.chip_sw_all_escalation_resets.3908402520
95.79	0.01	94.89	0.00	93.55	0.00	95.23	0.00			94.52	0.00	97.55	0.00	99.01	0.01	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.2919661269
95.79	0.01	94.89	0.00	93.55	0.00	95.23	0.00			94.52	0.00	97.55	0.00	99.02	0.01	/workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.1799174684
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95.80	0.01	94.89	0.00	93.55	0.00	95.23	0.00			94.52	0.00	97.55	0.00	99.05	0.01	/workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.2958037387
95.80	0.01	94.89	0.00	93.55	0.00	95.23	0.00			94.52	0.00	97.55	0.00	99.06	0.01	/workspace/coverage/default/22.chip_sw_all_escalation_resets.1910052415
95.80	0.01	94.89	0.00	93.55	0.00	95.23	0.00			94.52	0.00	97.55	0.00	99.07	0.01	/workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.1470675847
95.80	0.01	94.89	0.00	93.55	0.00	95.23	0.00			94.52	0.00	97.55	0.00	99.08	0.01	/workspace/coverage/default/23.chip_sw_all_escalation_resets.1898424320
95.81	0.01	94.89	0.00	93.55	0.00	95.23	0.00			94.52	0.00	97.55	0.00	99.10	0.01	/workspace/coverage/default/25.chip_sw_all_escalation_resets.3296156631
95.81	0.01	94.89	0.00	93.55	0.00	95.23	0.00			94.52	0.00	97.55	0.00	99.11	0.01	/workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.4190352720
95.81	0.01	94.89	0.00	93.55	0.00	95.23	0.00			94.52	0.00	97.55	0.00	99.12	0.01	/workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.919593224
95.81	0.01	94.89	0.00	93.55	0.00	95.23	0.00			94.52	0.00	97.55	0.00	99.13	0.01	/workspace/coverage/default/27.chip_sw_all_escalation_resets.4053778822
95.81	0.01	94.89	0.00	93.55	0.00	95.23	0.00			94.52	0.00	97.55	0.00	99.14	0.01	/workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.1827439471
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95.82	0.01	94.89	0.00	93.55	0.00	95.23	0.00			94.52	0.00	97.55	0.00	99.18	0.01	/workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.487170680
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95.88	0.01	94.89	0.00	93.57	0.01	95.24	0.00			94.52	0.00	97.55	0.00	99.51	0.00	/workspace/coverage/cover_reg_top/73.xbar_access_same_device.3711984798
95.88	0.01	94.89	0.00	93.58	0.01	95.24	0.00			94.52	0.00	97.55	0.00	99.51	0.00	/workspace/coverage/cover_reg_top/95.xbar_stress_all.334542922
95.88	0.01	94.89	0.00	93.59	0.01	95.24	0.00			94.52	0.00	97.55	0.00	99.51	0.00	/workspace/coverage/default/0.chip_sw_entropy_src_csrng.2918849449
95.88	0.01	94.89	0.00	93.60	0.01	95.24	0.00			94.52	0.00	97.55	0.00	99.51	0.00	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops.3684075983
95.88	0.01	94.89	0.00	93.61	0.01	95.24	0.00			94.52	0.00	97.55	0.00	99.51	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.217583023
95.89	0.01	94.89	0.00	93.62	0.01	95.24	0.00			94.52	0.00	97.55	0.00	99.51	0.00	/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx1.1988748862
95.89	0.01	94.89	0.01	93.62	0.00	95.24	0.01			94.52	0.00	97.55	0.00	99.51	0.00	/workspace/coverage/default/1.chip_tap_straps_rma.4158208655
95.89	0.01	94.90	0.01	93.62	0.00	95.25	0.01			94.52	0.00	97.55	0.00	99.51	0.00	/workspace/coverage/default/4.chip_sw_all_escalation_resets.863759558
95.89	0.01	94.90	0.00	93.63	0.01	95.25	0.01			94.52	0.00	97.55	0.00	99.51	0.00	/workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.2328792407
95.89	0.01	94.90	0.00	93.63	0.00	95.26	0.01			94.52	0.00	97.55	0.00	99.51	0.00	/workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.510695870
95.89	0.01	94.90	0.00	93.63	0.00	95.27	0.01			94.52	0.00	97.55	0.00	99.51	0.00	/workspace/coverage/default/1.chip_sw_hmac_enc_idle.2392549901
95.90	0.01	94.90	0.00	93.63	0.00	95.27	0.00			94.52	0.01	97.55	0.00	99.51	0.00	/workspace/coverage/default/0.chip_tap_straps_dev.2102809223
95.90	0.01	94.90	0.00	93.63	0.01	95.27	0.00			94.52	0.00	97.55	0.00	99.51	0.00	/workspace/coverage/cover_reg_top/1.chip_tl_errors.416237564
95.90	0.01	94.90	0.00	93.64	0.01	95.27	0.00			94.52	0.00	97.55	0.00	99.51	0.00	/workspace/coverage/cover_reg_top/14.xbar_random_zero_delays.2128352534
95.90	0.01	94.90	0.00	93.65	0.01	95.27	0.00			94.52	0.00	97.55	0.00	99.51	0.00	/workspace/coverage/cover_reg_top/24.xbar_stress_all.2740880148
95.90	0.01	94.90	0.00	93.65	0.01	95.27	0.00			94.52	0.00	97.55	0.00	99.51	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_10.1834984370
95.90	0.01	94.90	0.00	93.66	0.01	95.27	0.00			94.52	0.00	97.55	0.00	99.51	0.00	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.2394436185
95.90	0.01	94.90	0.00	93.67	0.01	95.27	0.00			94.52	0.00	97.55	0.00	99.51	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.195777389
95.90	0.01	94.90	0.00	93.67	0.01	95.27	0.00			94.52	0.00	97.55	0.00	99.51	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.3471899325
95.91	0.01	94.90	0.00	93.67	0.00	95.28	0.01			94.52	0.00	97.55	0.00	99.51	0.00	/workspace/coverage/cover_reg_top/2.chip_csr_hw_reset.3191573107
95.91	0.01	94.90	0.00	93.67	0.00	95.29	0.01			94.52	0.00	97.55	0.00	99.51	0.00	/workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3719195912
95.91	0.01	94.90	0.00	93.67	0.00	95.29	0.01			94.52	0.00	97.55	0.00	99.51	0.00	/workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.3958002885
95.91	0.01	94.90	0.00	93.67	0.00	95.30	0.01			94.52	0.00	97.55	0.00	99.51	0.00	/workspace/coverage/default/0.chip_jtag_csr_rw.103352071
95.91	0.01	94.90	0.00	93.67	0.00	95.30	0.01			94.52	0.00	97.55	0.00	99.51	0.00	/workspace/coverage/default/0.chip_sw_exit_test_unlocked_bootstrap.2804669511
95.91	0.01	94.90	0.00	93.67	0.00	95.31	0.01			94.52	0.00	97.55	0.00	99.51	0.00	/workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.2263346990
95.91	0.01	94.90	0.00	93.67	0.00	95.31	0.01			94.52	0.00	97.55	0.00	99.51	0.00	/workspace/coverage/default/0.chip_sw_lc_ctrl_program_error.2943841641
95.91	0.01	94.90	0.00	93.67	0.00	95.32	0.01			94.52	0.00	97.55	0.00	99.51	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.400394425
95.91	0.01	94.90	0.00	93.68	0.01	95.32	0.00			94.52	0.00	97.55	0.00	99.51	0.00	/workspace/coverage/cover_reg_top/0.xbar_error_random.407683480
95.91	0.01	94.90	0.00	93.68	0.01	95.32	0.00			94.52	0.00	97.55	0.00	99.51	0.00	/workspace/coverage/cover_reg_top/12.chip_tl_errors.4057047804
95.91	0.01	94.90	0.00	93.69	0.01	95.32	0.00			94.52	0.00	97.55	0.00	99.51	0.00	/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_error.2776376231
95.91	0.01	94.90	0.00	93.69	0.01	95.32	0.00			94.52	0.00	97.55	0.00	99.51	0.00	/workspace/coverage/cover_reg_top/22.chip_tl_errors.1685208079
95.91	0.01	94.90	0.00	93.69	0.01	95.32	0.00			94.52	0.00	97.55	0.00	99.51	0.00	/workspace/coverage/cover_reg_top/3.xbar_stress_all_with_error.3576459743
95.92	0.01	94.90	0.00	93.70	0.01	95.32	0.00			94.52	0.00	97.55	0.00	99.51	0.00	/workspace/coverage/cover_reg_top/32.xbar_stress_all_with_error.328383950
95.92	0.01	94.90	0.00	93.70	0.01	95.32	0.00			94.52	0.00	97.55	0.00	99.51	0.00	/workspace/coverage/cover_reg_top/35.xbar_stress_all_with_reset_error.3397218460
95.92	0.01	94.90	0.00	93.70	0.01	95.32	0.00			94.52	0.00	97.55	0.00	99.51	0.00	/workspace/coverage/cover_reg_top/37.xbar_stress_all_with_error.4189003102
95.92	0.01	94.90	0.00	93.71	0.01	95.32	0.00			94.52	0.00	97.55	0.00	99.51	0.00	/workspace/coverage/cover_reg_top/69.xbar_error_random.3951924500
95.92	0.01	94.90	0.00	93.71	0.01	95.32	0.00			94.52	0.00	97.55	0.00	99.51	0.00	/workspace/coverage/default/0.chip_sw_pattgen_ios.2974812944
95.92	0.01	94.90	0.00	93.71	0.01	95.32	0.00			94.52	0.00	97.55	0.00	99.51	0.00	/workspace/coverage/default/0.chip_sw_rstmgr_alert_info.2738720352
95.92	0.01	94.90	0.00	93.71	0.00	95.32	0.01			94.52	0.00	97.55	0.00	99.51	0.00	/workspace/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.2830386424
95.92	0.01	94.90	0.00	93.71	0.00	95.32	0.01			94.52	0.00	97.55	0.00	99.51	0.00	/workspace/coverage/default/0.chip_sw_aon_timer_irq.413105506
95.92	0.01	94.90	0.00	93.71	0.00	95.32	0.01			94.52	0.00	97.55	0.00	99.51	0.00	/workspace/coverage/default/0.chip_sw_edn_boot_mode.320002113
95.92	0.01	94.90	0.00	93.71	0.00	95.33	0.01			94.52	0.00	97.55	0.00	99.51	0.00	/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.3730689586
95.92	0.01	94.90	0.00	93.71	0.00	95.33	0.01			94.52	0.00	97.55	0.00	99.51	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.2652527731
95.92	0.01	94.90	0.00	93.71	0.00	95.33	0.01			94.52	0.00	97.55	0.00	99.51	0.00	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.1845920488

---

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.chip_csr_aliasing.937915382
/workspace/coverage/cover_reg_top/0.chip_csr_bit_bash.2064974698
/workspace/coverage/cover_reg_top/0.chip_csr_hw_reset.2631104357
/workspace/coverage/cover_reg_top/0.chip_csr_mem_rw_with_rand_reset.921698553
/workspace/coverage/cover_reg_top/0.chip_csr_rw.1280062543
/workspace/coverage/cover_reg_top/0.chip_prim_tl_access.4098471836
/workspace/coverage/cover_reg_top/0.chip_tl_errors.1728760466
/workspace/coverage/cover_reg_top/0.xbar_access_same_device.1402360441
/workspace/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.3528116529
/workspace/coverage/cover_reg_top/0.xbar_random.4182962875
/workspace/coverage/cover_reg_top/0.xbar_random_large_delays.3828485693
/workspace/coverage/cover_reg_top/0.xbar_random_slow_rsp.198922257
/workspace/coverage/cover_reg_top/0.xbar_random_zero_delays.1734102408
/workspace/coverage/cover_reg_top/0.xbar_same_source.832872067
/workspace/coverage/cover_reg_top/0.xbar_smoke.4000952415
/workspace/coverage/cover_reg_top/0.xbar_smoke_large_delays.1383643618
/workspace/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.3287654755
/workspace/coverage/cover_reg_top/0.xbar_smoke_zero_delays.1678708449
/workspace/coverage/cover_reg_top/0.xbar_stress_all.1373835628
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_error.2592044964
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.3128454137
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.3973719213
/workspace/coverage/cover_reg_top/0.xbar_unmapped_addr.1655818903
/workspace/coverage/cover_reg_top/1.chip_csr_aliasing.1441576209
/workspace/coverage/cover_reg_top/1.chip_csr_bit_bash.2759468301
/workspace/coverage/cover_reg_top/1.chip_csr_mem_rw_with_rand_reset.3691703186
/workspace/coverage/cover_reg_top/1.chip_csr_rw.1647748254
/workspace/coverage/cover_reg_top/1.chip_prim_tl_access.293312386
/workspace/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.3227261188
/workspace/coverage/cover_reg_top/1.chip_same_csr_outstanding.3489813184
/workspace/coverage/cover_reg_top/1.xbar_access_same_device.1619242048
/workspace/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.3431451194
/workspace/coverage/cover_reg_top/1.xbar_error_random.4248949170
/workspace/coverage/cover_reg_top/1.xbar_random.475891414
/workspace/coverage/cover_reg_top/1.xbar_random_large_delays.2099153640
/workspace/coverage/cover_reg_top/1.xbar_random_slow_rsp.415070358
/workspace/coverage/cover_reg_top/1.xbar_random_zero_delays.1287406822
/workspace/coverage/cover_reg_top/1.xbar_same_source.240355958
/workspace/coverage/cover_reg_top/1.xbar_smoke.3547551801
/workspace/coverage/cover_reg_top/1.xbar_smoke_large_delays.2999807723
/workspace/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.2091299651
/workspace/coverage/cover_reg_top/1.xbar_smoke_zero_delays.89306119
/workspace/coverage/cover_reg_top/1.xbar_stress_all.1148026955
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_error.91994595
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.3206013024
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.2703620834
/workspace/coverage/cover_reg_top/1.xbar_unmapped_addr.673467839
/workspace/coverage/cover_reg_top/10.chip_csr_mem_rw_with_rand_reset.2096569894
/workspace/coverage/cover_reg_top/10.chip_csr_rw.1074220668
/workspace/coverage/cover_reg_top/10.chip_same_csr_outstanding.2003000824
/workspace/coverage/cover_reg_top/10.chip_tl_errors.3470351029
/workspace/coverage/cover_reg_top/10.xbar_access_same_device.130271712
/workspace/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.2992061267
/workspace/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.3703092668
/workspace/coverage/cover_reg_top/10.xbar_error_random.3056818117
/workspace/coverage/cover_reg_top/10.xbar_random.3049607037
/workspace/coverage/cover_reg_top/10.xbar_random_large_delays.780461220
/workspace/coverage/cover_reg_top/10.xbar_random_slow_rsp.926619038
/workspace/coverage/cover_reg_top/10.xbar_random_zero_delays.2896371925
/workspace/coverage/cover_reg_top/10.xbar_same_source.706183719
/workspace/coverage/cover_reg_top/10.xbar_smoke.1787630371
/workspace/coverage/cover_reg_top/10.xbar_smoke_large_delays.1742064138
/workspace/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.2159652281
/workspace/coverage/cover_reg_top/10.xbar_smoke_zero_delays.1023305699
/workspace/coverage/cover_reg_top/10.xbar_stress_all.3280144484
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_error.478364599
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.316465212
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.3844687403
/workspace/coverage/cover_reg_top/10.xbar_unmapped_addr.737619863
/workspace/coverage/cover_reg_top/11.chip_csr_mem_rw_with_rand_reset.2944496701
/workspace/coverage/cover_reg_top/11.chip_csr_rw.3926781102
/workspace/coverage/cover_reg_top/11.chip_same_csr_outstanding.3599994370
/workspace/coverage/cover_reg_top/11.chip_tl_errors.3723954542
/workspace/coverage/cover_reg_top/11.xbar_access_same_device.36277576
/workspace/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.3945707797
/workspace/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.3588237398
/workspace/coverage/cover_reg_top/11.xbar_error_random.536782335
/workspace/coverage/cover_reg_top/11.xbar_random.2214332579
/workspace/coverage/cover_reg_top/11.xbar_random_large_delays.506848660
/workspace/coverage/cover_reg_top/11.xbar_random_slow_rsp.2760808124
/workspace/coverage/cover_reg_top/11.xbar_random_zero_delays.2891260047
/workspace/coverage/cover_reg_top/11.xbar_same_source.3535845569
/workspace/coverage/cover_reg_top/11.xbar_smoke.1057521072
/workspace/coverage/cover_reg_top/11.xbar_smoke_large_delays.2288301142
/workspace/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.2769403544
/workspace/coverage/cover_reg_top/11.xbar_smoke_zero_delays.974725104
/workspace/coverage/cover_reg_top/11.xbar_stress_all.3090873465
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_error.4092784446
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.2392911429
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.547534337
/workspace/coverage/cover_reg_top/11.xbar_unmapped_addr.3162202191
/workspace/coverage/cover_reg_top/12.chip_csr_mem_rw_with_rand_reset.2181892473
/workspace/coverage/cover_reg_top/12.chip_csr_rw.2141108836
/workspace/coverage/cover_reg_top/12.chip_same_csr_outstanding.1477640860
/workspace/coverage/cover_reg_top/12.xbar_access_same_device.3808333717
/workspace/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.2282461888
/workspace/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.1381155009
/workspace/coverage/cover_reg_top/12.xbar_error_random.3505643646
/workspace/coverage/cover_reg_top/12.xbar_random.3370223531
/workspace/coverage/cover_reg_top/12.xbar_random_large_delays.4090146454
/workspace/coverage/cover_reg_top/12.xbar_random_slow_rsp.3512551472
/workspace/coverage/cover_reg_top/12.xbar_random_zero_delays.1198334648
/workspace/coverage/cover_reg_top/12.xbar_same_source.4020293356
/workspace/coverage/cover_reg_top/12.xbar_smoke.729055396
/workspace/coverage/cover_reg_top/12.xbar_smoke_large_delays.2900759466
/workspace/coverage/cover_reg_top/12.xbar_smoke_slow_rsp.3962136788
/workspace/coverage/cover_reg_top/12.xbar_smoke_zero_delays.1619790308
/workspace/coverage/cover_reg_top/12.xbar_stress_all.706822522
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_rand_reset.3176678784
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_reset_error.853550956
/workspace/coverage/cover_reg_top/12.xbar_unmapped_addr.2990422343
/workspace/coverage/cover_reg_top/13.chip_csr_mem_rw_with_rand_reset.4128665890
/workspace/coverage/cover_reg_top/13.chip_csr_rw.3989655801
/workspace/coverage/cover_reg_top/13.chip_same_csr_outstanding.3279996812
/workspace/coverage/cover_reg_top/13.chip_tl_errors.1344606632
/workspace/coverage/cover_reg_top/13.xbar_access_same_device.557919662
/workspace/coverage/cover_reg_top/13.xbar_error_and_unmapped_addr.385132257
/workspace/coverage/cover_reg_top/13.xbar_error_random.1443531874
/workspace/coverage/cover_reg_top/13.xbar_random.3653255451
/workspace/coverage/cover_reg_top/13.xbar_random_large_delays.2003721581
/workspace/coverage/cover_reg_top/13.xbar_random_slow_rsp.1449408935
/workspace/coverage/cover_reg_top/13.xbar_random_zero_delays.2661409149
/workspace/coverage/cover_reg_top/13.xbar_same_source.2492827332
/workspace/coverage/cover_reg_top/13.xbar_smoke.1906095304
/workspace/coverage/cover_reg_top/13.xbar_smoke_large_delays.3234118467
/workspace/coverage/cover_reg_top/13.xbar_smoke_slow_rsp.1716688182
/workspace/coverage/cover_reg_top/13.xbar_smoke_zero_delays.3603949764
/workspace/coverage/cover_reg_top/13.xbar_stress_all.992501012
/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_error.680226822
/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_rand_reset.2394395008
/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_reset_error.3202031400
/workspace/coverage/cover_reg_top/13.xbar_unmapped_addr.2761486527
/workspace/coverage/cover_reg_top/14.chip_csr_mem_rw_with_rand_reset.1138905849
/workspace/coverage/cover_reg_top/14.chip_csr_rw.3974518238
/workspace/coverage/cover_reg_top/14.chip_same_csr_outstanding.1642072010
/workspace/coverage/cover_reg_top/14.chip_tl_errors.176697226
/workspace/coverage/cover_reg_top/14.xbar_access_same_device.792828847
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/workspace/coverage/default/2.chip_sw_rv_timer_irq.3463165653
/workspace/coverage/default/2.chip_sw_rv_timer_smoketest.3831052373
/workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.1288233294
/workspace/coverage/default/2.chip_sw_sensor_ctrl_status.3088497583
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/workspace/coverage/default/2.chip_sw_sleep_pwm_pulses.1263349995
/workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.1637643514
/workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.2478449202
/workspace/coverage/default/2.chip_sw_spi_device_pass_through.3488039014
/workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.4013610565
/workspace/coverage/default/2.chip_sw_spi_device_pinmux_sleep_retention.2771469954
/workspace/coverage/default/2.chip_sw_spi_device_tpm.368090715
/workspace/coverage/default/2.chip_sw_sram_ctrl_execution_main.268206542
/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.3508590974
/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.655673102
/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.2401037583
/workspace/coverage/default/2.chip_sw_sram_ctrl_smoketest.2609143944
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.2777026575
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.129637146
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_inputs.286504800
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_outputs.4069746457
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.2766700895
/workspace/coverage/default/2.chip_sw_uart_rand_baudrate.2089785764
/workspace/coverage/default/2.chip_sw_uart_smoketest.915670305
/workspace/coverage/default/2.chip_sw_uart_tx_rx.3551483097
/workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.34366965
/workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2165508850
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/workspace/coverage/default/2.rom_e2e_shutdown_output.3656308630
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/workspace/coverage/default/26.chip_sw_all_escalation_resets.470273959
/workspace/coverage/default/28.chip_sw_all_escalation_resets.2828961711
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/workspace/coverage/default/3.chip_tap_straps_dev.2102119702
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/workspace/coverage/default/3.chip_tap_straps_rma.3620439626
/workspace/coverage/default/30.chip_sw_all_escalation_resets.2313995249
/workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.2153042430
/workspace/coverage/default/32.chip_sw_all_escalation_resets.2821608100
/workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.2448026089
/workspace/coverage/default/33.chip_sw_all_escalation_resets.3765279927
/workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.3881851921
/workspace/coverage/default/34.chip_sw_all_escalation_resets.2980665114
/workspace/coverage/default/35.chip_sw_all_escalation_resets.1175790065
/workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.2857247910
/workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.2982925490
/workspace/coverage/default/38.chip_sw_all_escalation_resets.4265387514
/workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.451145706
/workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.1770555169
/workspace/coverage/default/4.chip_sw_csrng_edn_concurrency.63317793
/workspace/coverage/default/4.chip_sw_data_integrity_escalation.3956384705
/workspace/coverage/default/4.chip_sw_lc_ctrl_transition.2074855020
/workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.1103445252
/workspace/coverage/default/4.chip_sw_uart_rand_baudrate.2444250056
/workspace/coverage/default/4.chip_sw_uart_tx_rx.3810151737
/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.298858505
/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2843035570
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.1775245837
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.3171934516
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.4187011192
/workspace/coverage/default/4.chip_tap_straps_dev.3417176034
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/workspace/coverage/default/4.chip_tap_straps_rma.1187131631
/workspace/coverage/default/4.chip_tap_straps_testunlock0.2748976094
/workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.450621870
/workspace/coverage/default/42.chip_sw_all_escalation_resets.2429644814
/workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.3321851600
/workspace/coverage/default/44.chip_sw_all_escalation_resets.1090794331
/workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.1649907163
/workspace/coverage/default/45.chip_sw_all_escalation_resets.3994390281
/workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.447611010
/workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.526662566
/workspace/coverage/default/47.chip_sw_all_escalation_resets.1511210258
/workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.301642942
/workspace/coverage/default/48.chip_sw_all_escalation_resets.1129555844
/workspace/coverage/default/49.chip_sw_all_escalation_resets.1176271964
/workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.1783211849
/workspace/coverage/default/5.chip_sw_csrng_edn_concurrency.1790066040
/workspace/coverage/default/5.chip_sw_data_integrity_escalation.1051020558
/workspace/coverage/default/5.chip_sw_lc_ctrl_transition.437905411
/workspace/coverage/default/5.chip_sw_uart_rand_baudrate.1329854347
/workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.2838033529
/workspace/coverage/default/50.chip_sw_all_escalation_resets.2528743574
/workspace/coverage/default/51.chip_sw_all_escalation_resets.2051649024
/workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.1899200364
/workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.614187572
/workspace/coverage/default/53.chip_sw_all_escalation_resets.2878131151
/workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.3080878536
/workspace/coverage/default/54.chip_sw_all_escalation_resets.1243340930
/workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.2574910298
/workspace/coverage/default/55.chip_sw_all_escalation_resets.483719444
/workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.3895508021
/workspace/coverage/default/56.chip_sw_all_escalation_resets.2422121053
/workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.1938649761
/workspace/coverage/default/57.chip_sw_all_escalation_resets.1851600503
/workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.24921180
/workspace/coverage/default/58.chip_sw_all_escalation_resets.2470518950
/workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.809627118
/workspace/coverage/default/59.chip_sw_all_escalation_resets.2556650179
/workspace/coverage/default/6.chip_sw_all_escalation_resets.1323832788
/workspace/coverage/default/6.chip_sw_csrng_edn_concurrency.2200475346
/workspace/coverage/default/6.chip_sw_lc_ctrl_transition.169488635
/workspace/coverage/default/6.chip_sw_uart_rand_baudrate.4064309453
/workspace/coverage/default/60.chip_sw_all_escalation_resets.1552390322
/workspace/coverage/default/61.chip_sw_all_escalation_resets.570161009
/workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.1107526846
/workspace/coverage/default/62.chip_sw_all_escalation_resets.251597434
/workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.3468316404
/workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.1220066427
/workspace/coverage/default/64.chip_sw_all_escalation_resets.3591883244
/workspace/coverage/default/67.chip_sw_all_escalation_resets.3849233139
/workspace/coverage/default/68.chip_sw_all_escalation_resets.39213437
/workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.1893469993
/workspace/coverage/default/7.chip_sw_all_escalation_resets.3351577389
/workspace/coverage/default/7.chip_sw_csrng_edn_concurrency.1862296198
/workspace/coverage/default/7.chip_sw_lc_ctrl_transition.1455949749
/workspace/coverage/default/7.chip_sw_uart_rand_baudrate.4110708460
/workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.1309872814
/workspace/coverage/default/70.chip_sw_all_escalation_resets.3814343077
/workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.2330509367
/workspace/coverage/default/72.chip_sw_all_escalation_resets.3862120906
/workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.1543275838
/workspace/coverage/default/73.chip_sw_all_escalation_resets.1875899181
/workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.65649719
/workspace/coverage/default/74.chip_sw_all_escalation_resets.2947172378
/workspace/coverage/default/75.chip_sw_all_escalation_resets.1926789803
/workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.177895235
/workspace/coverage/default/76.chip_sw_all_escalation_resets.763806001
/workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.2873068101
/workspace/coverage/default/77.chip_sw_all_escalation_resets.2784514718
/workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.741268646
/workspace/coverage/default/79.chip_sw_all_escalation_resets.1455185334
/workspace/coverage/default/8.chip_sw_all_escalation_resets.3246294264
/workspace/coverage/default/8.chip_sw_csrng_edn_concurrency.1998575228
/workspace/coverage/default/8.chip_sw_lc_ctrl_transition.1909707690
/workspace/coverage/default/8.chip_sw_uart_rand_baudrate.1094902458
/workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.3882841727
/workspace/coverage/default/80.chip_sw_all_escalation_resets.1308195420
/workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.343674133
/workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.3801432600
/workspace/coverage/default/82.chip_sw_all_escalation_resets.4121805506
/workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.3110503091
/workspace/coverage/default/83.chip_sw_all_escalation_resets.705947558
/workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.1669292680
/workspace/coverage/default/84.chip_sw_all_escalation_resets.3382112558
/workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.3407007777
/workspace/coverage/default/85.chip_sw_all_escalation_resets.3722320553
/workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.2076931569
/workspace/coverage/default/86.chip_sw_all_escalation_resets.1355713808
/workspace/coverage/default/87.chip_sw_all_escalation_resets.370468786
/workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.1558025252
/workspace/coverage/default/88.chip_sw_all_escalation_resets.521128346
/workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.1381417298
/workspace/coverage/default/89.chip_sw_all_escalation_resets.1234709699
/workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.3198592190
/workspace/coverage/default/9.chip_sw_all_escalation_resets.1359375808
/workspace/coverage/default/9.chip_sw_csrng_edn_concurrency.4101764941
/workspace/coverage/default/9.chip_sw_lc_ctrl_transition.3633705204
/workspace/coverage/default/9.chip_sw_uart_rand_baudrate.3939641924
/workspace/coverage/default/90.chip_sw_all_escalation_resets.2961784705
/workspace/coverage/default/92.chip_sw_all_escalation_resets.3955013866
/workspace/coverage/default/93.chip_sw_all_escalation_resets.1425856539
/workspace/coverage/default/94.chip_sw_all_escalation_resets.2767596366
/workspace/coverage/default/95.chip_sw_all_escalation_resets.406823494
/workspace/coverage/default/96.chip_sw_all_escalation_resets.387743234
/workspace/coverage/default/97.chip_sw_all_escalation_resets.2231178303
/workspace/coverage/default/99.chip_sw_all_escalation_resets.601350091
/workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.2756146220
/workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.3962616219
/workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.607033186
/workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.3571547168
/workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.1691058056
/workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.2156777621
/workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.3468930201

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Total test records in report: 2938

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TEST NO	TEST LOCATION	TEST NAME	STATUS	STARTED	FINISHED	SIMULATION TIME
T1	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.2028234847			Aug 11 07:52:11 PM PDT 24	Aug 11 09:04:33 PM PDT 24	14587830694 ps
T2	/workspace/coverage/default/2.chip_sw_lc_ctrl_program_error.134105198			Aug 11 08:11:39 PM PDT 24	Aug 11 08:21:20 PM PDT 24	5381538762 ps
T3	/workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.673267825			Aug 11 08:21:11 PM PDT 24	Aug 11 08:28:46 PM PDT 24	3726140696 ps
T32	/workspace/coverage/default/2.chip_sw_csrng_kat_test.1386031828			Aug 11 08:07:43 PM PDT 24	Aug 11 08:11:02 PM PDT 24	2244600472 ps
T31	/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.3512551934			Aug 11 07:52:10 PM PDT 24	Aug 11 08:17:48 PM PDT 24	8288211386 ps
T4	/workspace/coverage/default/0.chip_sw_uart_rand_baudrate.3938691349			Aug 11 07:36:54 PM PDT 24	Aug 11 07:46:04 PM PDT 24	3454559960 ps
T36	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.4040621421			Aug 11 07:53:39 PM PDT 24	Aug 11 08:03:09 PM PDT 24	6511398814 ps
T6	/workspace/coverage/default/1.chip_sw_lc_walkthrough_dev.908328186			Aug 11 07:51:29 PM PDT 24	Aug 11 09:21:20 PM PDT 24	45987844002 ps
T5	/workspace/coverage/default/1.chip_sw_spi_device_pinmux_sleep_retention.2016531299			Aug 11 07:51:16 PM PDT 24	Aug 11 07:57:56 PM PDT 24	4050224638 ps
T47	/workspace/coverage/default/3.chip_tap_straps_testunlock0.2694642405			Aug 11 08:13:04 PM PDT 24	Aug 11 08:22:11 PM PDT 24	5523346389 ps
T45	/workspace/coverage/default/1.rom_e2e_static_critical.499291336			Aug 11 08:07:13 PM PDT 24	Aug 11 09:18:04 PM PDT 24	17147831584 ps
T91	/workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.3407007777			Aug 11 08:25:09 PM PDT 24	Aug 11 08:31:42 PM PDT 24	3501460284 ps
T7	/workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.3038919085			Aug 11 07:44:19 PM PDT 24	Aug 11 08:16:44 PM PDT 24	22226914639 ps
T92	/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.3229717013			Aug 11 07:52:52 PM PDT 24	Aug 11 08:12:39 PM PDT 24	7299219072 ps
T16	/workspace/coverage/default/0.chip_sw_usbdev_config_host.549312531			Aug 11 07:34:12 PM PDT 24	Aug 11 08:05:00 PM PDT 24	8353648156 ps
T93	/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_por_reset.132351843			Aug 11 07:55:20 PM PDT 24	Aug 11 08:08:30 PM PDT 24	6922759796 ps
T94	/workspace/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.1019898227			Aug 11 07:56:12 PM PDT 24	Aug 11 08:27:41 PM PDT 24	25729899174 ps
T95	/workspace/coverage/default/1.chip_sw_entropy_src_ast_rng_req.3664615140			Aug 11 07:54:50 PM PDT 24	Aug 11 07:57:51 PM PDT 24	2738406748 ps
T778	/workspace/coverage/default/1.chip_sw_hmac_enc_idle.2392549901			Aug 11 07:55:22 PM PDT 24	Aug 11 08:00:53 PM PDT 24	3015796160 ps
T14	/workspace/coverage/default/1.chip_sw_gpio_smoketest.963460397			Aug 11 08:05:31 PM PDT 24	Aug 11 08:09:26 PM PDT 24	2386415441 ps
T46	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.944255252			Aug 11 07:51:59 PM PDT 24	Aug 11 09:47:02 PM PDT 24	23643847108 ps
T15	/workspace/coverage/default/1.chip_sw_uart_tx_rx_bootstrap.3853935611			Aug 11 07:50:21 PM PDT 24	Aug 11 11:41:59 PM PDT 24	78541429887 ps
T114	/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3967466659			Aug 11 08:10:02 PM PDT 24	Aug 11 08:17:51 PM PDT 24	5348631840 ps
T48	/workspace/coverage/default/0.chip_sw_flash_rma_unlocked.1685483244			Aug 11 07:34:18 PM PDT 24	Aug 11 09:13:38 PM PDT 24	44158845738 ps
T965	/workspace/coverage/default/1.chip_sw_flash_scrambling_smoketest.1177708002			Aug 11 08:03:46 PM PDT 24	Aug 11 08:06:45 PM PDT 24	3128098306 ps
T111	/workspace/coverage/default/2.chip_sw_entropy_src_ast_rng_req.3998479976			Aug 11 08:10:41 PM PDT 24	Aug 11 08:14:31 PM PDT 24	2951353680 ps
T140	/workspace/coverage/default/1.chip_plic_all_irqs_10.301086571			Aug 11 07:57:05 PM PDT 24	Aug 11 08:06:04 PM PDT 24	3491969914 ps
T59	/workspace/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.3093151122			Aug 11 07:52:20 PM PDT 24	Aug 11 08:22:12 PM PDT 24	11215574449 ps
T229	/workspace/coverage/default/0.chip_sw_otbn_mem_scramble.3091557781			Aug 11 07:36:54 PM PDT 24	Aug 11 07:43:05 PM PDT 24	3778871788 ps
T242	/workspace/coverage/default/0.chip_sw_rv_timer_irq.1627979916			Aug 11 07:36:00 PM PDT 24	Aug 11 07:38:54 PM PDT 24	2408581046 ps
T234	/workspace/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.2652527731			Aug 11 07:43:44 PM PDT 24	Aug 11 07:48:46 PM PDT 24	3417692076 ps
T43	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod.1606864587			Aug 11 07:52:18 PM PDT 24	Aug 11 09:36:54 PM PDT 24	23456306296 ps
T275	/workspace/coverage/default/0.chip_sw_kmac_entropy.3114497990			Aug 11 07:34:40 PM PDT 24	Aug 11 07:38:28 PM PDT 24	3216730760 ps
T112	/workspace/coverage/default/2.chip_sw_csrng_edn_concurrency.4190704590			Aug 11 08:11:22 PM PDT 24	Aug 11 10:32:42 PM PDT 24	42408004288 ps
T276	/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.582492991			Aug 11 07:52:34 PM PDT 24	Aug 11 07:56:30 PM PDT 24	2872742632 ps
T277	/workspace/coverage/default/0.chip_sw_otp_ctrl_dai_lock.3123674081			Aug 11 07:35:55 PM PDT 24	Aug 11 09:23:37 PM PDT 24	27093224608 ps
T278	/workspace/coverage/default/0.chip_sw_rv_plic_smoketest.2805486550			Aug 11 07:49:43 PM PDT 24	Aug 11 07:53:44 PM PDT 24	2973206950 ps
T198	/workspace/coverage/default/2.chip_sw_uart_tx_rx.3551483097			Aug 11 08:02:39 PM PDT 24	Aug 11 08:13:11 PM PDT 24	4777036090 ps
T387	/workspace/coverage/default/2.chip_sw_pwrmgr_usb_clk_disabled_when_active.1014819738			Aug 11 08:06:04 PM PDT 24	Aug 11 08:14:24 PM PDT 24	4268081500 ps
T66	/workspace/coverage/default/0.chip_tap_straps_rma.3221656601			Aug 11 07:43:00 PM PDT 24	Aug 11 07:45:45 PM PDT 24	3194453521 ps
T197	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.3818814553			Aug 11 07:34:32 PM PDT 24	Aug 11 07:45:37 PM PDT 24	5251115050 ps
T392	/workspace/coverage/default/2.rom_e2e_smoke.2446401507			Aug 11 08:16:21 PM PDT 24	Aug 11 09:17:20 PM PDT 24	14436324904 ps
T244	/workspace/coverage/default/2.chip_sw_aon_timer_wdog_bite_reset.1927517940			Aug 11 08:06:09 PM PDT 24	Aug 11 08:18:35 PM PDT 24	7867467480 ps
T103	/workspace/coverage/default/0.chip_sw_aes_enc_jitter_en.3398285345			Aug 11 07:38:09 PM PDT 24	Aug 11 07:41:33 PM PDT 24	3217063399 ps
T393	/workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_invalid_meas.730757029			Aug 11 08:04:35 PM PDT 24	Aug 11 09:06:48 PM PDT 24	14885888264 ps
T23	/workspace/coverage/default/1.chip_sw_sleep_pin_retention.1851466228			Aug 11 07:49:45 PM PDT 24	Aug 11 07:55:43 PM PDT 24	5123540970 ps
T64	/workspace/coverage/default/1.chip_sw_exit_test_unlocked_bootstrap.3100110514			Aug 11 07:50:56 PM PDT 24	Aug 11 11:09:06 PM PDT 24	58494026840 ps
T159	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.860027154			Aug 11 07:51:32 PM PDT 24	Aug 11 09:06:14 PM PDT 24	15307622510 ps
T966	/workspace/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.3930499618			Aug 11 07:37:23 PM PDT 24	Aug 11 07:44:51 PM PDT 24	6820834450 ps
T60	/workspace/coverage/default/87.chip_sw_all_escalation_resets.370468786			Aug 11 08:25:49 PM PDT 24	Aug 11 08:38:28 PM PDT 24	5595235868 ps
T78	/workspace/coverage/default/16.chip_sw_all_escalation_resets.769196728			Aug 11 08:18:12 PM PDT 24	Aug 11 08:32:10 PM PDT 24	5957344224 ps
T79	/workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.2448026089			Aug 11 08:19:45 PM PDT 24	Aug 11 08:27:56 PM PDT 24	4086755674 ps
T84	/workspace/coverage/default/0.chip_sw_data_integrity_escalation.834623977			Aug 11 07:37:46 PM PDT 24	Aug 11 07:52:09 PM PDT 24	5908265876 ps
T65	/workspace/coverage/default/0.chip_sw_exit_test_unlocked_bootstrap.2804669511			Aug 11 07:33:47 PM PDT 24	Aug 11 10:30:36 PM PDT 24	60354263334 ps
T85	/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3796647715			Aug 11 08:12:03 PM PDT 24	Aug 11 09:30:43 PM PDT 24	24486045513 ps
T86	/workspace/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.3828243023			Aug 11 07:58:39 PM PDT 24	Aug 11 08:01:47 PM PDT 24	2527485487 ps
T87	/workspace/coverage/default/74.chip_sw_all_escalation_resets.2947172378			Aug 11 08:31:18 PM PDT 24	Aug 11 08:40:33 PM PDT 24	3919551480 ps
T88	/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_prod.736054520			Aug 11 07:56:19 PM PDT 24	Aug 11 08:28:12 PM PDT 24	9681635910 ps
T89	/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.2460243559			Aug 11 08:13:00 PM PDT 24	Aug 11 08:46:58 PM PDT 24	12273901701 ps
T34	/workspace/coverage/default/2.chip_sw_spi_host_tx_rx.1979438514			Aug 11 08:02:33 PM PDT 24	Aug 11 08:07:30 PM PDT 24	2857694524 ps
T268	/workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.2930361892			Aug 11 08:17:44 PM PDT 24	Aug 11 08:24:35 PM PDT 24	7239370298 ps
T249	/workspace/coverage/default/4.chip_sw_csrng_edn_concurrency.63317793			Aug 11 08:14:48 PM PDT 24	Aug 11 09:51:08 PM PDT 24	26180912168 ps
T205	/workspace/coverage/default/0.chip_sw_keymgr_sideload_kmac.3490105086			Aug 11 07:38:49 PM PDT 24	Aug 11 08:18:35 PM PDT 24	11720193272 ps
T779	/workspace/coverage/default/1.chip_sw_hmac_oneshot.4243827025			Aug 11 07:57:17 PM PDT 24	Aug 11 08:04:39 PM PDT 24	2978860184 ps
T239	/workspace/coverage/default/0.chip_sw_plic_sw_irq.2393174727			Aug 11 07:40:07 PM PDT 24	Aug 11 07:44:23 PM PDT 24	2140519946 ps
T17	/workspace/coverage/default/0.chip_sw_usbdev_dpi.87394785			Aug 11 07:34:21 PM PDT 24	Aug 11 08:19:15 PM PDT 24	11828059854 ps
T382	/workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.1543275838			Aug 11 08:24:19 PM PDT 24	Aug 11 08:31:28 PM PDT 24	3620404584 ps
T967	/workspace/coverage/default/1.chip_sw_csrng_smoketest.4272363537			Aug 11 08:00:56 PM PDT 24	Aug 11 08:04:32 PM PDT 24	2646133750 ps
T203	/workspace/coverage/default/91.chip_sw_all_escalation_resets.2947896784			Aug 11 08:25:08 PM PDT 24	Aug 11 08:36:43 PM PDT 24	5609155714 ps
T115	/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_wake_5_bug.3356297554			Aug 11 08:11:54 PM PDT 24	Aug 11 08:19:29 PM PDT 24	5868602450 ps
T250	/workspace/coverage/default/0.chip_sw_edn_entropy_reqs.3320965488			Aug 11 07:40:16 PM PDT 24	Aug 11 07:59:49 PM PDT 24	6120368384 ps
T245	/workspace/coverage/default/0.chip_plic_all_irqs_0.1130879038			Aug 11 07:44:22 PM PDT 24	Aug 11 08:01:09 PM PDT 24	6106470164 ps
T968	/workspace/coverage/default/1.chip_sw_flash_ctrl_clock_freqs.2942655849			Aug 11 07:50:32 PM PDT 24	Aug 11 08:08:14 PM PDT 24	5579483794 ps
T204	/workspace/coverage/default/2.chip_sw_flash_crash_alert.404114232			Aug 11 08:12:10 PM PDT 24	Aug 11 08:28:16 PM PDT 24	5218473144 ps
T170	/workspace/coverage/default/1.chip_sw_rv_dm_access_after_wakeup.4140010487			Aug 11 07:58:11 PM PDT 24	Aug 11 08:10:19 PM PDT 24	6503786080 ps
T444	/workspace/coverage/default/2.chip_sw_kmac_idle.3378626042			Aug 11 08:10:26 PM PDT 24	Aug 11 08:15:41 PM PDT 24	2897457432 ps
T790	/workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.65649719			Aug 11 08:31:48 PM PDT 24	Aug 11 08:39:14 PM PDT 24	4147943082 ps
T744	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_power_glitch_reset.518377325			Aug 11 07:37:32 PM PDT 24	Aug 11 07:44:41 PM PDT 24	6654730320 ps
T144	/workspace/coverage/default/62.chip_sw_all_escalation_resets.251597434			Aug 11 08:25:32 PM PDT 24	Aug 11 08:34:30 PM PDT 24	5782426384 ps
T191	/workspace/coverage/default/54.chip_sw_all_escalation_resets.1243340930			Aug 11 08:22:00 PM PDT 24	Aug 11 08:31:20 PM PDT 24	4911287596 ps
T240	/workspace/coverage/default/1.chip_sw_plic_sw_irq.449129815			Aug 11 07:57:52 PM PDT 24	Aug 11 08:02:05 PM PDT 24	2641912296 ps
T969	/workspace/coverage/default/0.chip_sw_clkmgr_jitter_frequency.3516663296			Aug 11 07:41:58 PM PDT 24	Aug 11 07:48:29 PM PDT 24	2911998400 ps
T73	/workspace/coverage/default/1.rom_raw_unlock.3951900423			Aug 11 08:01:45 PM PDT 24	Aug 11 08:05:46 PM PDT 24	3911357965 ps
T315	/workspace/coverage/default/14.chip_sw_uart_rand_baudrate.226473244			Aug 11 08:16:40 PM PDT 24	Aug 11 08:24:27 PM PDT 24	3595198592 ps
T230	/workspace/coverage/default/2.chip_sw_data_integrity_escalation.1240984383			Aug 11 08:02:11 PM PDT 24	Aug 11 08:19:04 PM PDT 24	5811038420 ps
T8	/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.3006372355			Aug 11 07:49:45 PM PDT 24	Aug 11 07:54:41 PM PDT 24	3155256235 ps
T351	/workspace/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.3523346059			Aug 11 07:50:21 PM PDT 24	Aug 11 08:01:09 PM PDT 24	5448618200 ps
T136	/workspace/coverage/default/0.chip_sw_otbn_smoketest.3777883165			Aug 11 07:49:47 PM PDT 24	Aug 11 08:14:15 PM PDT 24	7334836824 ps
T146	/workspace/coverage/default/15.chip_sw_all_escalation_resets.2515218276			Aug 11 08:18:15 PM PDT 24	Aug 11 08:30:57 PM PDT 24	5365829104 ps
T107	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.1881520432			Aug 11 08:11:10 PM PDT 24	Aug 11 08:22:48 PM PDT 24	4350219610 ps
T105	/workspace/coverage/default/1.rom_volatile_raw_unlock.539556328			Aug 11 08:00:41 PM PDT 24	Aug 11 08:02:29 PM PDT 24	2050938066 ps
T780	/workspace/coverage/default/1.chip_sw_hmac_smoketest.3505216569			Aug 11 08:04:55 PM PDT 24	Aug 11 08:11:54 PM PDT 24	3259941996 ps
T134	/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.2892874408			Aug 11 08:15:19 PM PDT 24	Aug 11 08:24:53 PM PDT 24	4776327924 ps
T19	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.3667746399			Aug 11 08:06:23 PM PDT 24	Aug 11 08:31:49 PM PDT 24	24365050188 ps
T970	/workspace/coverage/default/1.chip_sw_aon_timer_wdog_lc_escalate.1057242459			Aug 11 07:53:44 PM PDT 24	Aug 11 08:06:20 PM PDT 24	5797573588 ps
T116	/workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.1288233294			Aug 11 08:10:13 PM PDT 24	Aug 11 08:25:45 PM PDT 24	8272572600 ps
T363	/workspace/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.3398922267			Aug 11 07:35:19 PM PDT 24	Aug 11 07:40:34 PM PDT 24	3539205320 ps
T206	/workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.2263346990			Aug 11 07:38:43 PM PDT 24	Aug 11 08:47:53 PM PDT 24	15419637040 ps
T971	/workspace/coverage/default/2.chip_sw_flash_ctrl_clock_freqs.3734970680			Aug 11 08:03:24 PM PDT 24	Aug 11 08:21:41 PM PDT 24	5438693129 ps
T80	/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.3530554488			Aug 11 07:54:52 PM PDT 24	Aug 11 08:14:55 PM PDT 24	11019546040 ps
T548	/workspace/coverage/default/0.chip_sw_otp_ctrl_smoketest.1588115708			Aug 11 07:49:26 PM PDT 24	Aug 11 07:54:04 PM PDT 24	2389171120 ps
T972	/workspace/coverage/default/0.rom_e2e_asm_init_rma.2505895539			Aug 11 07:54:27 PM PDT 24	Aug 11 09:03:14 PM PDT 24	14404430779 ps
T104	/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.888080410			Aug 11 07:59:23 PM PDT 24	Aug 11 08:09:15 PM PDT 24	5260634800 ps
T202	/workspace/coverage/default/2.chip_tap_straps_dev.2262488144			Aug 11 08:10:27 PM PDT 24	Aug 11 08:12:47 PM PDT 24	2115093013 ps
T359	/workspace/coverage/default/68.chip_sw_all_escalation_resets.39213437			Aug 11 08:23:24 PM PDT 24	Aug 11 08:33:38 PM PDT 24	5347027138 ps
T118	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1094906095			Aug 11 07:41:52 PM PDT 24	Aug 11 07:49:04 PM PDT 24	5480834120 ps
T145	/workspace/coverage/default/75.chip_sw_all_escalation_resets.1926789803			Aug 11 08:24:03 PM PDT 24	Aug 11 08:36:51 PM PDT 24	4547926208 ps
T100	/workspace/coverage/default/2.chip_sw_ast_clk_rst_inputs.3360732113			Aug 11 08:13:07 PM PDT 24	Aug 11 09:04:36 PM PDT 24	21141991878 ps
T171	/workspace/coverage/default/2.chip_sw_rv_dm_access_after_wakeup.1284277850			Aug 11 08:11:13 PM PDT 24	Aug 11 08:22:08 PM PDT 24	6051960108 ps
T101	/workspace/coverage/default/1.chip_sw_ast_clk_rst_inputs.2794382242			Aug 11 07:59:13 PM PDT 24	Aug 11 08:33:13 PM PDT 24	14859528940 ps
T192	/workspace/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.1749746053			Aug 11 07:55:42 PM PDT 24	Aug 11 08:28:51 PM PDT 24	8801083364 ps
T129	/workspace/coverage/default/2.chip_sw_sensor_ctrl_status.3088497583			Aug 11 08:09:17 PM PDT 24	Aug 11 08:14:39 PM PDT 24	3155342267 ps
T195	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.1143573843			Aug 11 07:34:39 PM PDT 24	Aug 11 07:49:52 PM PDT 24	4974904902 ps
T187	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.129637146			Aug 11 08:05:20 PM PDT 24	Aug 11 08:15:06 PM PDT 24	5070191800 ps
T720	/workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.3497356051			Aug 11 07:58:28 PM PDT 24	Aug 11 08:11:03 PM PDT 24	8564048336 ps
T821	/workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.487170680			Aug 11 08:20:27 PM PDT 24	Aug 11 08:26:41 PM PDT 24	3125331636 ps
T11	/workspace/coverage/default/1.chip_sw_spi_device_pass_through.2774859679			Aug 11 07:51:38 PM PDT 24	Aug 11 08:02:21 PM PDT 24	6257105716 ps
T732	/workspace/coverage/default/79.chip_sw_all_escalation_resets.1455185334			Aug 11 08:23:33 PM PDT 24	Aug 11 08:31:10 PM PDT 24	3988010232 ps
T108	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.3230868793			Aug 11 07:57:15 PM PDT 24	Aug 11 08:07:39 PM PDT 24	4131904754 ps
T318	/workspace/coverage/default/2.chip_sw_hmac_enc.2612073054			Aug 11 08:11:52 PM PDT 24	Aug 11 08:16:03 PM PDT 24	2925674412 ps
T147	/workspace/coverage/default/59.chip_sw_all_escalation_resets.2556650179			Aug 11 08:22:25 PM PDT 24	Aug 11 08:30:44 PM PDT 24	4681952500 ps
T18	/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.1215074879			Aug 11 07:58:31 PM PDT 24	Aug 11 08:24:54 PM PDT 24	21246927496 ps
T201	/workspace/coverage/default/3.chip_tap_straps_prod.1750020095			Aug 11 08:13:45 PM PDT 24	Aug 11 08:16:23 PM PDT 24	2737855548 ps
T415	/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1478234511			Aug 11 08:04:58 PM PDT 24	Aug 11 08:15:43 PM PDT 24	8144155368 ps
T74	/workspace/coverage/default/0.chip_jtag_mem_access.3375252918			Aug 11 07:35:44 PM PDT 24	Aug 11 08:02:19 PM PDT 24	13608840626 ps
T83	/workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.2600522011			Aug 11 08:20:45 PM PDT 24	Aug 11 08:28:27 PM PDT 24	3982904504 ps
T416	/workspace/coverage/default/3.chip_sw_csrng_edn_concurrency.2734205886			Aug 11 08:17:59 PM PDT 24	Aug 11 09:09:28 PM PDT 24	11623987872 ps
T342	/workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en.1782488582			Aug 11 07:39:11 PM PDT 24	Aug 11 07:42:14 PM PDT 24	2089185102 ps
T75	/workspace/coverage/default/2.chip_jtag_mem_access.231191208			Aug 11 08:03:30 PM PDT 24	Aug 11 08:29:05 PM PDT 24	13145104396 ps
T12	/workspace/coverage/default/1.chip_sw_spi_device_pass_through_collision.2446512287			Aug 11 07:53:20 PM PDT 24	Aug 11 08:03:29 PM PDT 24	4539674622 ps
T417	/workspace/coverage/default/0.chip_sw_pwrmgr_smoketest.2752673608			Aug 11 07:49:37 PM PDT 24	Aug 11 07:57:51 PM PDT 24	5319423090 ps
T973	/workspace/coverage/default/2.chip_sw_kmac_mode_cshake.2146566019			Aug 11 08:08:05 PM PDT 24	Aug 11 08:11:13 PM PDT 24	2325785128 ps
T137	/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.492862637			Aug 11 07:44:40 PM PDT 24	Aug 11 08:54:59 PM PDT 24	24905244148 ps
T209	/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.1284230876			Aug 11 07:44:49 PM PDT 24	Aug 11 08:06:35 PM PDT 24	8701183729 ps
T785	/workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.640567483			Aug 11 08:17:15 PM PDT 24	Aug 11 08:24:31 PM PDT 24	3629114720 ps
T381	/workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.2320418993			Aug 11 08:22:04 PM PDT 24	Aug 11 08:27:59 PM PDT 24	3076336244 ps
T20	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.1633185428			Aug 11 07:55:04 PM PDT 24	Aug 11 08:25:53 PM PDT 24	24988156708 ps
T329	/workspace/coverage/default/1.chip_sw_rv_plic_smoketest.2707471251			Aug 11 08:01:12 PM PDT 24	Aug 11 08:05:19 PM PDT 24	3001852060 ps
T303	/workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.4117554490			Aug 11 07:51:14 PM PDT 24	Aug 11 08:02:25 PM PDT 24	4700004794 ps
T304	/workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.2076931569			Aug 11 08:25:42 PM PDT 24	Aug 11 08:32:04 PM PDT 24	4324592970 ps
T308	/workspace/coverage/default/1.chip_sw_alert_handler_ping_timeout.3329790735			Aug 11 07:54:33 PM PDT 24	Aug 11 07:59:04 PM PDT 24	3714126314 ps
T309	/workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en_reduced_freq.3828850740			Aug 11 08:01:18 PM PDT 24	Aug 11 08:05:23 PM PDT 24	2975053511 ps
T217	/workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.2922335397			Aug 11 08:10:52 PM PDT 24	Aug 11 08:49:18 PM PDT 24	19909716461 ps
T110	/workspace/coverage/default/1.chip_sw_edn_boot_mode.3374386949			Aug 11 07:54:14 PM PDT 24	Aug 11 08:04:26 PM PDT 24	3101427696 ps
T310	/workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.1799174684			Aug 11 08:18:04 PM PDT 24	Aug 11 08:24:35 PM PDT 24	3529350080 ps
T311	/workspace/coverage/default/2.chip_sw_hmac_multistream.3653132037			Aug 11 08:08:55 PM PDT 24	Aug 11 08:37:50 PM PDT 24	8489647780 ps
T312	/workspace/coverage/default/2.rom_keymgr_functest.3423017019			Aug 11 08:15:08 PM PDT 24	Aug 11 08:23:07 PM PDT 24	4735151760 ps
T185	/workspace/coverage/default/2.chip_sw_inject_scramble_seed.1668864222			Aug 11 08:04:22 PM PDT 24	Aug 11 11:20:07 PM PDT 24	65873899813 ps
T161	/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.2505593240			Aug 11 07:46:16 PM PDT 24	Aug 11 07:56:54 PM PDT 24	4445164518 ps
T231	/workspace/coverage/default/1.chip_sw_rstmgr_cpu_info.2013970091			Aug 11 07:53:39 PM PDT 24	Aug 11 08:08:54 PM PDT 24	7012030420 ps
T257	/workspace/coverage/default/2.chip_sw_rstmgr_smoketest.1980108964			Aug 11 08:14:26 PM PDT 24	Aug 11 08:18:11 PM PDT 24	2820041324 ps
T258	/workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.1119308284			Aug 11 08:16:38 PM PDT 24	Aug 11 08:22:54 PM PDT 24	3312002342 ps
T117	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_wake_5_bug.2729883125			Aug 11 07:42:33 PM PDT 24	Aug 11 07:50:37 PM PDT 24	6418146660 ps
T106	/workspace/coverage/default/1.chip_sw_lc_ctrl_transition.1729271140			Aug 11 07:50:59 PM PDT 24	Aug 11 08:01:20 PM PDT 24	12428279170 ps
T259	/workspace/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.2030981326			Aug 11 07:46:30 PM PDT 24	Aug 11 07:50:51 PM PDT 24	3450871260 ps
T260	/workspace/coverage/default/1.chip_sw_clkmgr_sleep_frequency.2026095087			Aug 11 08:00:26 PM PDT 24	Aug 11 08:12:35 PM PDT 24	5353295904 ps
T61	/workspace/coverage/default/1.chip_tap_straps_rma.4158208655			Aug 11 07:57:38 PM PDT 24	Aug 11 08:03:07 PM PDT 24	4202093918 ps
T44	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_dev.3773512413			Aug 11 07:52:23 PM PDT 24	Aug 11 09:40:07 PM PDT 24	23448791260 ps
T261	/workspace/coverage/default/7.chip_sw_lc_ctrl_transition.1455949749			Aug 11 08:16:13 PM PDT 24	Aug 11 08:24:51 PM PDT 24	7773091288 ps
T795	/workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.2982925490			Aug 11 08:20:53 PM PDT 24	Aug 11 08:28:18 PM PDT 24	3444212312 ps
T974	/workspace/coverage/default/1.chip_sw_aon_timer_smoketest.380568236			Aug 11 08:01:29 PM PDT 24	Aug 11 08:06:13 PM PDT 24	3049625222 ps
T39	/workspace/coverage/default/1.chip_sw_spi_device_tpm.17775971			Aug 11 07:51:44 PM PDT 24	Aug 11 07:57:40 PM PDT 24	3715065853 ps
T786	/workspace/coverage/default/2.chip_sw_clkmgr_reset_frequency.577443832			Aug 11 08:10:08 PM PDT 24	Aug 11 08:15:33 PM PDT 24	3194055240 ps
T153	/workspace/coverage/default/0.chip_sw_lc_ctrl_program_error.2943841641			Aug 11 07:42:29 PM PDT 24	Aug 11 07:49:42 PM PDT 24	4301327460 ps
T446	/workspace/coverage/default/1.chip_sw_edn_entropy_reqs.3113299657			Aug 11 07:58:00 PM PDT 24	Aug 11 08:14:57 PM PDT 24	5807491504 ps
T367	/workspace/coverage/default/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.1247199570			Aug 11 08:11:26 PM PDT 24	Aug 11 08:19:27 PM PDT 24	6653738684 ps
T102	/workspace/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.3036223843			Aug 11 08:00:09 PM PDT 24	Aug 11 09:27:32 PM PDT 24	28443610348 ps
T109	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.1462977618			Aug 11 07:57:30 PM PDT 24	Aug 11 08:08:32 PM PDT 24	3550705300 ps
T814	/workspace/coverage/default/44.chip_sw_all_escalation_resets.1090794331			Aug 11 08:27:08 PM PDT 24	Aug 11 08:40:08 PM PDT 24	4527498856 ps
T218	/workspace/coverage/default/2.chip_sw_flash_init.2797992892			Aug 11 08:06:03 PM PDT 24	Aug 11 08:39:27 PM PDT 24	16357057440 ps
T151	/workspace/coverage/default/2.chip_sw_lc_walkthrough_prod.595179942			Aug 11 08:10:30 PM PDT 24	Aug 11 09:41:01 PM PDT 24	50251186469 ps
T160	/workspace/coverage/default/0.rom_e2e_asm_init_prod_end.538940287			Aug 11 07:54:29 PM PDT 24	Aug 11 09:12:02 PM PDT 24	15527414437 ps
T975	/workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.3778027411			Aug 11 07:41:20 PM PDT 24	Aug 11 07:52:21 PM PDT 24	7644819064 ps
T243	/workspace/coverage/default/0.chip_sw_rv_timer_smoketest.4201736568			Aug 11 07:51:42 PM PDT 24	Aug 11 07:55:38 PM PDT 24	3312577744 ps
T210	/workspace/coverage/default/20.chip_sw_all_escalation_resets.352950333			Aug 11 08:20:04 PM PDT 24	Aug 11 08:31:26 PM PDT 24	4464398910 ps
T194	/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx1.4200333330			Aug 11 08:02:38 PM PDT 24	Aug 11 08:15:41 PM PDT 24	4042260020 ps
T976	/workspace/coverage/default/2.rom_e2e_asm_init_prod.3404424200			Aug 11 08:17:07 PM PDT 24	Aug 11 09:35:02 PM PDT 24	15783656968 ps
T977	/workspace/coverage/default/1.chip_sw_clkmgr_jitter.3096976366			Aug 11 07:57:10 PM PDT 24	Aug 11 07:59:50 PM PDT 24	2927795110 ps
T343	/workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.2666745396			Aug 11 07:51:02 PM PDT 24	Aug 11 08:01:49 PM PDT 24	4938501553 ps
T978	/workspace/coverage/default/1.chip_sw_clkmgr_smoketest.3620589956			Aug 11 08:01:04 PM PDT 24	Aug 11 08:05:22 PM PDT 24	2592483984 ps
T979	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.1584363201			Aug 11 07:43:24 PM PDT 24	Aug 11 07:55:09 PM PDT 24	3988493452 ps
T207	/workspace/coverage/default/2.chip_sw_alert_handler_escalation.2299158616			Aug 11 08:07:29 PM PDT 24	Aug 11 08:14:19 PM PDT 24	5521826042 ps
T748	/workspace/coverage/default/0.chip_tap_straps_dev.2102809223			Aug 11 07:43:04 PM PDT 24	Aug 11 07:55:54 PM PDT 24	7163759202 ps
T796	/workspace/coverage/default/61.chip_sw_all_escalation_resets.570161009			Aug 11 08:23:41 PM PDT 24	Aug 11 08:32:11 PM PDT 24	5027636964 ps
T56	/workspace/coverage/default/0.chip_sw_sleep_pin_wake.459664778			Aug 11 07:33:56 PM PDT 24	Aug 11 07:39:34 PM PDT 24	3121604442 ps
T409	/workspace/coverage/default/1.chip_sw_flash_ctrl_access.2476324856			Aug 11 07:52:14 PM PDT 24	Aug 11 08:12:09 PM PDT 24	6025371040 ps
T410	/workspace/coverage/default/2.chip_sw_kmac_entropy.895236367			Aug 11 08:04:15 PM PDT 24	Aug 11 08:08:25 PM PDT 24	2513541654 ps
T411	/workspace/coverage/default/96.chip_sw_all_escalation_resets.387743234			Aug 11 08:25:44 PM PDT 24	Aug 11 08:35:47 PM PDT 24	5840440322 ps
T188	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_inputs.286504800			Aug 11 08:06:47 PM PDT 24	Aug 11 08:13:05 PM PDT 24	3221743557 ps
T324	/workspace/coverage/default/2.chip_sw_entropy_src_csrng.3226597227			Aug 11 08:08:28 PM PDT 24	Aug 11 08:28:30 PM PDT 24	5588551250 ps
T262	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.3153673304			Aug 11 07:52:52 PM PDT 24	Aug 11 09:04:24 PM PDT 24	14135867000 ps
T162	/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.1006510655			Aug 11 07:39:18 PM PDT 24	Aug 11 07:47:58 PM PDT 24	4627151742 ps
T246	/workspace/coverage/default/0.rom_e2e_jtag_inject_rma.3513277787			Aug 11 07:49:43 PM PDT 24	Aug 11 08:25:04 PM PDT 24	25052597957 ps
T155	/workspace/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.915996410			Aug 11 07:35:03 PM PDT 24	Aug 11 07:39:16 PM PDT 24	3792584916 ps
T980	/workspace/coverage/default/0.chip_sw_sram_ctrl_smoketest.722298417			Aug 11 07:49:11 PM PDT 24	Aug 11 07:53:56 PM PDT 24	2281716846 ps
T799	/workspace/coverage/default/2.chip_sw_rv_timer_smoketest.3831052373			Aug 11 08:15:15 PM PDT 24	Aug 11 08:19:35 PM PDT 24	2379113636 ps
T301	/workspace/coverage/default/48.chip_sw_all_escalation_resets.1129555844			Aug 11 08:21:04 PM PDT 24	Aug 11 08:28:12 PM PDT 24	5771724656 ps
T981	/workspace/coverage/default/0.chip_sw_kmac_mode_kmac.1501806895			Aug 11 07:40:32 PM PDT 24	Aug 11 07:45:57 PM PDT 24	2736945864 ps
T384	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.3398729125			Aug 11 07:52:08 PM PDT 24	Aug 11 09:39:19 PM PDT 24	24780297358 ps
T356	/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx3.3313689343			Aug 11 08:14:25 PM PDT 24	Aug 11 08:26:14 PM PDT 24	4201926284 ps
T982	/workspace/coverage/default/0.chip_sw_aon_timer_smoketest.2974585486			Aug 11 07:48:36 PM PDT 24	Aug 11 07:52:57 PM PDT 24	3005226652 ps
T983	/workspace/coverage/default/0.rom_e2e_asm_init_prod.1475382310			Aug 11 07:51:21 PM PDT 24	Aug 11 09:11:34 PM PDT 24	15787901080 ps
T797	/workspace/coverage/default/83.chip_sw_all_escalation_resets.705947558			Aug 11 08:24:40 PM PDT 24	Aug 11 08:36:19 PM PDT 24	6109235624 ps
T984	/workspace/coverage/default/2.chip_sw_hmac_oneshot.3855861632			Aug 11 08:11:35 PM PDT 24	Aug 11 08:16:23 PM PDT 24	2930210700 ps
T362	/workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3719195912			Aug 11 07:37:26 PM PDT 24	Aug 11 07:48:20 PM PDT 24	18728161986 ps
T130	/workspace/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.3158710215			Aug 11 08:03:56 PM PDT 24	Aug 11 08:12:47 PM PDT 24	7931890664 ps
T57	/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.1710061345			Aug 11 08:00:49 PM PDT 24	Aug 11 08:08:03 PM PDT 24	7328475650 ps
T985	/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.3744927329			Aug 11 07:58:53 PM PDT 24	Aug 11 08:07:04 PM PDT 24	5399642586 ps
T986	/workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.1637643514			Aug 11 08:08:53 PM PDT 24	Aug 11 08:20:43 PM PDT 24	7646500616 ps
T135	/workspace/coverage/default/2.chip_sw_power_idle_load.3441529574			Aug 11 08:11:13 PM PDT 24	Aug 11 08:23:23 PM PDT 24	4170024878 ps
T987	/workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.2364685262			Aug 11 07:44:06 PM PDT 24	Aug 11 08:00:05 PM PDT 24	7578660995 ps
T53	/workspace/coverage/default/0.chip_sw_spi_device_pinmux_sleep_retention.3256987778			Aug 11 07:34:18 PM PDT 24	Aug 11 07:38:14 PM PDT 24	2813641107 ps
T235	/workspace/coverage/default/1.chip_sw_rstmgr_alert_info.442712637			Aug 11 07:53:38 PM PDT 24	Aug 11 08:15:49 PM PDT 24	11677379658 ps
T988	/workspace/coverage/default/0.chip_sw_hmac_smoketest.1241979771			Aug 11 07:49:31 PM PDT 24	Aug 11 07:54:43 PM PDT 24	3418815252 ps
T989	/workspace/coverage/default/0.chip_sw_rv_dm_access_after_wakeup.3262943220			Aug 11 07:44:08 PM PDT 24	Aug 11 07:51:11 PM PDT 24	5711688760 ps
T777	/workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.3913266051			Aug 11 08:21:40 PM PDT 24	Aug 11 08:28:08 PM PDT 24	3596561976 ps
T990	/workspace/coverage/default/2.chip_sw_kmac_mode_kmac.1077549912			Aug 11 08:09:13 PM PDT 24	Aug 11 08:15:06 PM PDT 24	3129904080 ps
T991	/workspace/coverage/default/1.rom_e2e_asm_init_test_unlocked0.724807086			Aug 11 08:04:52 PM PDT 24	Aug 11 08:57:33 PM PDT 24	10806945232 ps
T992	/workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_no_meas.216876236			Aug 11 08:18:02 PM PDT 24	Aug 11 09:21:41 PM PDT 24	14414004862 ps
T383	/workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.3080878536			Aug 11 08:22:27 PM PDT 24	Aug 11 08:30:30 PM PDT 24	4571434104 ps
T263	/workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.227272357			Aug 11 07:52:42 PM PDT 24	Aug 11 07:54:39 PM PDT 24	1913985541 ps
T993	/workspace/coverage/default/1.chip_sw_flash_ctrl_idle_low_power.2496913683			Aug 11 07:51:32 PM PDT 24	Aug 11 07:56:40 PM PDT 24	3356891142 ps
T994	/workspace/coverage/default/0.chip_sw_aes_entropy.3390113731			Aug 11 07:39:35 PM PDT 24	Aug 11 07:43:40 PM PDT 24	2213089208 ps
T995	/workspace/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.3982424322			Aug 11 07:43:53 PM PDT 24	Aug 11 07:48:11 PM PDT 24	2596799529 ps
T339	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops.3684075983			Aug 11 07:34:19 PM PDT 24	Aug 11 07:45:05 PM PDT 24	3958456632 ps
T838	/workspace/coverage/default/29.chip_sw_all_escalation_resets.3068979427			Aug 11 08:20:02 PM PDT 24	Aug 11 08:29:21 PM PDT 24	4635959800 ps
T996	/workspace/coverage/default/2.chip_sw_rv_plic_smoketest.894183819			Aug 11 08:14:48 PM PDT 24	Aug 11 08:17:49 PM PDT 24	2376338314 ps
T997	/workspace/coverage/default/1.rom_e2e_smoke.1944920165			Aug 11 08:04:31 PM PDT 24	Aug 11 09:23:07 PM PDT 24	15209175778 ps
T802	/workspace/coverage/default/25.chip_sw_all_escalation_resets.3296156631			Aug 11 08:20:31 PM PDT 24	Aug 11 08:29:17 PM PDT 24	5751312800 ps
T998	/workspace/coverage/default/2.chip_sw_clkmgr_jitter.2129806343			Aug 11 08:10:58 PM PDT 24	Aug 11 08:14:08 PM PDT 24	2526867047 ps
T999	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.390374626			Aug 11 08:09:41 PM PDT 24	Aug 11 08:18:36 PM PDT 24	4141894620 ps
T208	/workspace/coverage/default/35.chip_sw_all_escalation_resets.1175790065			Aug 11 08:22:02 PM PDT 24	Aug 11 08:32:29 PM PDT 24	4698093040 ps
T1000	/workspace/coverage/default/0.chip_sw_example_rom.283365607			Aug 11 07:32:44 PM PDT 24	Aug 11 07:34:31 PM PDT 24	2910742580 ps
T794	/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.1880728146			Aug 11 07:53:31 PM PDT 24	Aug 11 08:14:36 PM PDT 24	13415268934 ps
T163	/workspace/coverage/default/1.chip_sw_rv_core_ibex_address_translation.446617099			Aug 11 07:58:29 PM PDT 24	Aug 11 08:03:41 PM PDT 24	3172773600 ps
T211	/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.2585140336			Aug 11 08:01:28 PM PDT 24	Aug 11 08:40:17 PM PDT 24	12992025679 ps
T292	/workspace/coverage/default/1.chip_sw_uart_tx_rx.1257878388			Aug 11 07:50:49 PM PDT 24	Aug 11 08:03:33 PM PDT 24	4264956896 ps
T293	/workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.3082052125			Aug 11 07:40:26 PM PDT 24	Aug 11 07:44:48 PM PDT 24	2702018851 ps
T294	/workspace/coverage/default/2.chip_sw_pwrmgr_wdog_reset.3942703108			Aug 11 08:07:32 PM PDT 24	Aug 11 08:20:34 PM PDT 24	4795104816 ps
T295	/workspace/coverage/default/2.chip_sw_rstmgr_sw_req.1644328636			Aug 11 08:04:48 PM PDT 24	Aug 11 08:13:55 PM PDT 24	5536448462 ps
T296	/workspace/coverage/default/1.chip_sw_flash_ctrl_mem_protection.3107477129			Aug 11 08:02:03 PM PDT 24	Aug 11 08:23:07 PM PDT 24	5929664838 ps
T297	/workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.2682116317			Aug 11 08:22:37 PM PDT 24	Aug 11 08:31:29 PM PDT 24	4070876200 ps
T219	/workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.3700231784			Aug 11 07:36:17 PM PDT 24	Aug 11 09:22:09 PM PDT 24	50405334491 ps
T13	/workspace/coverage/default/1.chip_sw_spi_host_tx_rx.2092234696			Aug 11 07:53:19 PM PDT 24	Aug 11 07:58:13 PM PDT 24	3004309656 ps
T775	/workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.809627118			Aug 11 08:23:00 PM PDT 24	Aug 11 08:29:24 PM PDT 24	3850525888 ps
T791	/workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.1938649761			Aug 11 08:23:15 PM PDT 24	Aug 11 08:29:21 PM PDT 24	3324583346 ps
T813	/workspace/coverage/default/55.chip_sw_all_escalation_resets.483719444			Aug 11 08:22:42 PM PDT 24	Aug 11 08:34:18 PM PDT 24	4056931178 ps
T1001	/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_por_reset.4249532201			Aug 11 08:05:27 PM PDT 24	Aug 11 08:15:30 PM PDT 24	6169077290 ps
T355	/workspace/coverage/default/0.chip_sival_flash_info_access.3002085175			Aug 11 07:33:32 PM PDT 24	Aug 11 07:37:38 PM PDT 24	2652106680 ps
T212	/workspace/coverage/default/1.chip_sw_keymgr_sideload_aes.3234260991			Aug 11 07:58:04 PM PDT 24	Aug 11 08:17:30 PM PDT 24	6955266042 ps