Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	50	0	50	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	50	0	50	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	50	0	50	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	448	1			T447	1		T448	1		T464	1
all_values[1]	452	1			T71	1		T553	1		T436	1
all_values[2]	432	1			T549	1		T517	1		T661	1
all_values[3]	437	1			T553	3		T901	1		T426	1
all_values[4]	434	1			T553	1		T506	1		T564	1
all_values[5]	432	1			T71	2		T553	1		T549	1
all_values[6]	455	1			T564	2		T464	2		T740	2
all_values[7]	413	1			T447	1		T553	2		T436	1
all_values[8]	450	1			T447	1		T553	1		T549	1
all_values[9]	431	1			T71	1		T447	1		T553	1
all_values[10]	404	1			T71	1		T506	1		T912	1
all_values[11]	468	1			T436	1		T822	1		T506	2
all_values[12]	447	1			T553	3		T448	1		T549	1
all_values[13]	421	1			T447	2		T551	1		T519	1
all_values[14]	506	1			T549	1		T506	1		T517	1
all_values[15]	466	1			T447	1		T506	2		T517	2
all_values[16]	434	1			T553	1		T519	1		T517	1
all_values[17]	411	1			T71	1		T553	1		T506	1
all_values[18]	425	1			T553	1		T549	1		T519	1
all_values[19]	428	1			T71	2		T447	3		T553	2
all_values[20]	450	1			T553	1		T549	1		T506	1
all_values[21]	447	1			T553	1		T459	1		T564	1
all_values[22]	465	1			T447	1		T549	1		T464	1
all_values[23]	443	1			T447	1		T549	1		T901	1
all_values[24]	429	1			T71	1		T506	1		T661	1
all_values[25]	485	1			T71	1		T519	1		T506	1
all_values[26]	503	1			T506	1		T426	1		T912	1
all_values[27]	443	1			T448	1		T464	1		T738	1
all_values[28]	429	1			T549	1		T464	5		T740	2
all_values[29]	465	1			T71	1		T549	1		T506	1
all_values[30]	439	1			T447	1		T436	2		T448	1
all_values[31]	433	1			T447	1		T551	1		T459	1
all_values[32]	446	1			T71	1		T553	2		T549	2
all_values[33]	438	1			T71	1		T447	1		T549	1
all_values[34]	434	1			T506	2		T517	1		T912	1
all_values[35]	421	1			T553	1		T464	2		T738	1
all_values[36]	454	1			T447	1		T553	2		T448	1
all_values[37]	445	1			T822	1		T519	1		T506	3
all_values[38]	442	1			T553	1		T436	1		T549	1
all_values[39]	415	1			T71	1		T553	1		T448	1
all_values[40]	481	1			T436	1		T551	1		T549	1
all_values[41]	449	1			T553	1		T549	1		T519	1
all_values[42]	422	1			T553	1		T549	1		T822	1
all_values[43]	458	1			T447	2		T553	1		T551	1
all_values[44]	450	1			T447	1		T822	1		T519	1
all_values[45]	437	1			T447	1		T553	1		T549	1
all_values[46]	466	1			T553	1		T549	1		T517	1
all_values[47]	450	1			T553	2		T436	1		T549	2
all_values[48]	479	1			T71	1		T506	1		T517	2
all_values[49]	428	1			T553	1		T549	1		T519	1