Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	3542	1			T71	4		T138	2		T553	11
all_values[1]	3503	1			T71	2		T449	1		T553	7
all_values[2]	3464	1			T71	5		T138	3		T553	7
all_values[3]	3445	1			T71	3		T138	1		T553	7
all_values[4]	3563	1			T71	7		T138	1		T449	1
all_values[5]	3409	1			T71	5		T138	2		T553	8
all_values[6]	3595	1			T138	3		T553	4		T448	4
all_values[7]	3486	1			T71	3		T138	1		T553	8
all_values[8]	3392	1			T71	4		T138	1		T553	10
all_values[9]	3561	1			T71	5		T138	1		T553	5
all_values[10]	3462	1			T71	4		T138	3		T449	1
all_values[11]	3437	1			T71	7		T138	2		T553	12
all_values[12]	3483	1			T71	6		T138	2		T553	8
all_values[13]	3562	1			T71	6		T138	4		T553	7
all_values[14]	3425	1			T71	7		T138	2		T449	1
all_values[15]	3547	1			T71	2		T553	9		T448	5
all_values[16]	3424	1			T71	2		T138	4		T553	12
all_values[17]	3473	1			T71	4		T138	3		T553	7
all_values[18]	3570	1			T71	9		T138	5		T553	5
all_values[19]	3436	1			T71	3		T138	2		T553	3
all_values[20]	3534	1			T71	4		T138	2		T553	5
all_values[21]	3587	1			T71	2		T138	4		T553	4
all_values[22]	3432	1			T71	4		T138	2		T553	6
all_values[23]	3416	1			T71	3		T138	1		T449	1
all_values[24]	3518	1			T71	4		T138	4		T553	7
all_values[25]	3456	1			T71	6		T138	3		T553	1
all_values[26]	3566	1			T71	3		T138	2		T553	4
all_values[27]	3430	1			T71	10		T138	2		T553	7
all_values[28]	3441	1			T71	3		T553	6		T448	5
all_values[29]	3543	1			T71	4		T138	1		T449	1
all_values[30]	3520	1			T71	4		T138	2		T553	1
all_values[31]	3602	1			T71	3		T553	9		T448	6
all_values[32]	3570	1			T71	6		T138	4		T553	7
all_values[33]	3511	1			T71	4		T138	1		T553	6
all_values[34]	3436	1			T71	3		T138	7		T449	1
all_values[35]	3484	1			T71	6		T138	1		T553	8
all_values[36]	3544	1			T71	7		T138	1		T553	7
all_values[37]	3508	1			T71	5		T138	1		T553	6
all_values[38]	3479	1			T71	2		T138	2		T553	6
all_values[39]	3486	1			T71	3		T553	7		T448	5
all_values[40]	3499	1			T71	5		T138	7		T449	1
all_values[41]	3495	1			T71	6		T138	1		T553	9
all_values[42]	3385	1			T71	3		T138	3		T553	6
all_values[43]	3570	1			T71	6		T138	1		T553	13
all_values[44]	3462	1			T71	6		T138	3		T553	11
all_values[45]	3539	1			T71	4		T138	4		T553	7
all_values[46]	3567	1			T71	7		T138	3		T553	13
all_values[47]	3491	1			T71	7		T138	3		T553	2
all_values[48]	3527	1			T71	4		T553	8		T448	10
all_values[49]	3476	1			T71	6		T138	1		T553	8
all_values[50]	3486	1			T71	2		T553	6		T448	8
all_values[51]	3547	1			T71	3		T138	3		T553	8
all_values[52]	3576	1			T71	3		T138	1		T449	1
all_values[53]	3554	1			T71	4		T138	2		T553	9
all_values[54]	3555	1			T71	2		T138	3		T449	1
all_values[55]	3479	1			T71	5		T138	2		T553	7
all_values[56]	3434	1			T71	6		T138	4		T553	5
all_values[57]	3480	1			T71	1		T553	7		T448	4
all_values[58]	3511	1			T71	7		T138	3		T553	12
all_values[59]	3509	1			T71	5		T138	4		T553	6
all_values[60]	3455	1			T71	5		T138	1		T553	7
all_values[61]	3547	1			T71	3		T138	3		T449	1
all_values[62]	3472	1			T71	5		T138	1		T553	6
all_values[63]	3570	1			T71	4		T138	3		T449	1