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LINE 18002
EXPRESSION (addr_hit[199] & reg_we & ((!reg_error)))
------1------ ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T3,T4,T5 |
| 1 | 0 | 1 | Covered | T3,T4,T5 |
| 1 | 1 | 0 | Covered | T550,T575,T567 |
| 1 | 1 | 1 | Covered | T3,T4,T5 |
LINE 18005
EXPRESSION (addr_hit[200] & reg_we & ((!reg_error)))
------1------ ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T3,T4,T5 |
| 1 | 0 | 1 | Covered | T773,T774,T113 |
| 1 | 1 | 0 | Covered | T575,T573,T561 |
| 1 | 1 | 1 | Covered | T239,T240,T241 |
LINE 18008
EXPRESSION (addr_hit[201] & reg_we & ((!reg_error)))
------1------ ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T3,T4,T5 |
| 1 | 0 | 1 | Covered | T113,T375,T550 |
| 1 | 1 | 0 | Covered | T575,T559,T569 |
| 1 | 1 | 1 | Covered | T49,T50,T51 |