Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.flash_ctrl__prim_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	151294	1			T79	46		T80	107		T81	1
values[2]	4314	1			T251	5		T462	1		T421	8
values[3]	1955	1			T556	55		T554	3		T454	1
values[4]	1393	1			T556	29		T554	5		T696	42
values[5]	1199	1			T556	40		T554	3		T696	12
values[6]	971	1			T556	57		T554	6		T696	3
values[7]	860	1			T556	59		T554	1		T466	11
values[8]	681	1			T556	57		T554	2		T466	6
values[9]	591	1			T556	28		T554	3		T466	10
values[10]	572	1			T556	14		T554	1		T466	1
values[11]	499	1			T556	12		T554	1		T477	1
values[12]	454	1			T556	11		T554	2		T477	1
values[13]	401	1			T556	6		T554	2		T477	1
values[14]	338	1			T554	1		T477	1		T918	5
values[15]	298	1			T554	2		T477	1		T918	12
values[16]	241	1			T554	5		T477	1		T918	12
values[17]	262	1			T554	3		T477	1		T918	20
values[18]	228	1			T554	4		T477	1		T918	26
values[19]	184	1			T554	3		T477	1		T918	13
values[20]	181	1			T554	4		T477	1		T918	6
values[21]	159	1			T554	2		T477	1		T918	2
values[22]	138	1			T554	2		T477	1		T474	7
values[23]	140	1			T554	1		T477	1		T474	9
values[24]	132	1			T554	2		T477	1		T474	19
values[25]	121	1			T554	1		T477	1		T474	16
values[26]	130	1			T554	2		T477	1		T474	18
values[27]	131	1			T554	9		T477	1		T474	34
values[28]	95	1			T554	2		T477	1		T474	25
values[29]	95	1			T554	4		T477	1		T474	29
values[30]	93	1			T554	3		T477	1		T474	23
values[31]	78	1			T554	8		T477	1		T474	25
values[32]	76	1			T554	3		T477	1		T474	10
values[33]	89	1			T554	2		T477	1		T474	9
values[34]	99	1			T554	5		T477	1		T474	11
values[35]	120	1			T554	7		T477	1		T474	2
values[36]	113	1			T554	5		T477	1		T496	1
values[37]	88	1			T554	1		T477	1		T496	1
values[38]	71	1			T554	1		T477	1		T496	1
values[39]	66	1			T554	5		T477	1		T496	1
values[40]	48	1			T554	2		T477	1		T496	1
values[41]	48	1			T554	1		T477	1		T496	1
values[42]	44	1			T554	2		T477	1		T496	1
values[43]	44	1			T554	5		T477	1		T496	1
values[44]	41	1			T554	3		T477	1		T496	1
values[45]	46	1			T554	7		T477	1		T496	1
values[46]	37	1			T554	2		T477	1		T496	1
values[47]	40	1			T554	1		T477	1		T496	1
values[48]	43	1			T554	3		T477	1		T496	1
values[49]	40	1			T554	2		T477	1		T496	1
values[50]	38	1			T554	2		T477	1		T496	1
values[51]	38	1			T554	1		T477	1		T496	1
values[52]	46	1			T554	4		T477	1		T496	1
values[53]	39	1			T554	1		T477	1		T496	1
values[54]	47	1			T554	2		T477	1		T496	1
values[55]	45	1			T554	3		T477	1		T496	1
values[56]	42	1			T554	1		T477	1		T496	1
values[57]	48	1			T554	3		T477	1		T496	1
values[58]	46	1			T554	4		T477	1		T496	1
values[59]	39	1			T554	1		T477	1		T496	1
values[60]	41	1			T554	1		T477	1		T496	1
values[61]	44	1			T554	2		T477	1		T496	1
values[62]	46	1			T554	4		T477	1		T496	1
values[63]	41	1			T554	1		T477	1		T496	1
values[64]	43	1			T554	4		T477	1		T496	1
values[65]	45	1			T554	3		T477	1		T496	1
values[66]	43	1			T554	2		T477	1		T496	1
values[67]	42	1			T554	1		T477	1		T496	1
values[68]	39	1			T554	2		T477	1		T496	1
values[69]	43	1			T554	2		T477	1		T496	1
values[70]	50	1			T554	2		T477	1		T496	1
values[71]	51	1			T554	2		T477	1		T496	1
values[72]	44	1			T554	2		T477	1		T496	1
values[73]	47	1			T554	5		T477	1		T496	1
values[74]	41	1			T554	2		T477	1		T496	1
values[75]	47	1			T554	1		T477	1		T496	1
values[76]	61	1			T554	2		T477	1		T496	1
values[77]	56	1			T554	1		T477	2		T496	1
values[78]	54	1			T554	2		T477	1		T496	1
values[79]	65	1			T554	1		T477	5		T496	1
values[80]	53	1			T554	2		T477	2		T496	1
values[81]	54	1			T554	2		T477	4		T496	1
values[82]	54	1			T554	1		T477	2		T496	1
values[83]	54	1			T554	2		T477	2		T496	1
values[84]	60	1			T554	3		T477	3		T496	1
values[85]	62	1			T554	1		T477	2		T496	1
values[86]	58	1			T554	3		T477	3		T496	1
values[87]	60	1			T554	7		T477	3		T496	1
values[88]	75	1			T554	4		T477	3		T496	1
values[89]	73	1			T554	1		T477	4		T496	1
values[90]	57	1			T554	4		T477	1		T496	1
values[91]	77	1			T554	1		T477	4		T496	1
values[92]	71	1			T554	2		T477	4		T496	1
values[93]	78	1			T554	2		T477	5		T496	1
values[94]	79	1			T554	1		T477	3		T496	1
values[95]	60	1			T554	2		T477	2		T496	1
values[96]	53	1			T554	1		T477	1		T496	1
values[97]	71	1			T554	2		T477	4		T496	1
values[98]	61	1			T554	1		T477	3		T496	1
values[99]	57	1			T554	1		T477	2		T496	1
values[100]	73	1			T554	3		T477	2		T496	1
values[101]	64	1			T554	7		T477	2		T496	1
values[102]	85	1			T554	9		T477	1		T496	1
values[103]	79	1			T554	1		T477	1		T496	1
values[104]	83	1			T554	3		T477	3		T496	1
values[105]	80	1			T554	1		T477	2		T496	1
values[106]	72	1			T554	2		T477	1		T496	1
values[107]	73	1			T554	1		T477	1		T496	1
values[108]	70	1			T554	1		T477	1		T496	1
values[109]	78	1			T554	4		T477	2		T496	1
values[110]	91	1			T554	1		T477	1		T496	1
values[111]	81	1			T554	3		T477	1		T496	1
values[112]	90	1			T554	2		T477	1		T496	1
values[113]	79	1			T554	4		T477	1		T496	2
values[114]	97	1			T554	6		T477	1		T496	3
values[115]	80	1			T554	3		T477	2		T496	2
values[116]	89	1			T554	2		T477	5		T496	2
values[117]	83	1			T554	4		T477	3		T496	2
values[118]	60	1			T554	1		T477	2		T496	1
values[119]	77	1			T554	2		T477	3		T496	1
values[120]	93	1			T554	2		T477	3		T496	1
values[121]	98	1			T554	2		T477	3		T496	2
values[122]	88	1			T554	3		T477	3		T496	1
values[123]	83	1			T554	2		T477	1		T496	2
values[124]	139	1			T554	15		T477	1		T496	1
values[125]	164	1			T554	30		T477	1		T496	2
values[126]	586	1			T554	50		T477	13		T496	9
values[127]	3269	1			T554	34		T477	104		T496	138
values[128]	6301	1			T554	3		T477	174		T496	306