Total Coverage Summary 

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.03	95.47	93.71	95.35		94.54	97.53	99.57

Total tests in report: 2943

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Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
39.44	39.44	44.58	44.58	42.93	42.93	31.46	31.46			57.83	57.83	59.44	59.44	0.39	0.39	/workspace/coverage/default/56.chip_sw_all_escalation_resets.3048952077
49.00	9.56	50.37	5.80	57.07	14.13	31.83	0.37			68.31	10.48	84.62	25.17	1.79	1.40	/workspace/coverage/cover_reg_top/16.chip_csr_mem_rw_with_rand_reset.272406096
56.86	7.86	61.97	11.60	62.48	5.42	39.35	7.52			69.72	1.41	84.62	0.00	23.01	21.22	/workspace/coverage/cover_reg_top/90.xbar_stress_all_with_error.3781919921
61.96	5.11	72.90	10.93	69.92	7.43	41.77	2.41			79.58	9.86	84.62	0.00	23.01	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_0.1100387318
65.51	3.55	72.90	0.00	70.14	0.23	41.77	0.00			79.59	0.02	84.62	0.00	44.04	21.03	/workspace/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.1364371976
68.99	3.48	77.05	4.14	72.33	2.19	50.53	8.77			81.36	1.77	88.64	4.02	44.04	0.00	/workspace/coverage/default/0.chip_sw_power_virus.648383791
71.51	2.52	81.96	4.91	76.06	3.73	53.84	3.30			82.99	1.62	90.21	1.57	44.04	0.00	/workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.411000603
73.99	2.47	81.96	0.01	76.08	0.02	68.63	14.79			83.00	0.02	90.21	0.00	44.04	0.00	/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.1361308886
76.37	2.38	81.96	0.00	76.34	0.25	68.63	0.00			83.10	0.10	90.21	0.00	57.96	13.92	/workspace/coverage/cover_reg_top/14.xbar_access_same_device_slow_rsp.1440019027
78.25	1.88	82.23	0.26	76.49	0.16	78.97	10.34			83.29	0.19	90.56	0.35	57.96	0.00	/workspace/coverage/default/2.chip_sw_lc_walkthrough_dev.2347032120
80.01	1.76	83.60	1.38	78.97	2.48	81.63	2.66			85.00	1.71	90.73	0.17	60.10	2.14	/workspace/coverage/default/0.chip_sw_alert_test.817986919
81.51	1.50	83.60	0.00	79.07	0.10	81.63	0.00			85.00	0.00	90.73	0.00	68.99	8.89	/workspace/coverage/cover_reg_top/46.xbar_access_same_device_slow_rsp.569705881
82.61	1.11	85.49	1.88	80.40	1.33	81.84	0.21			86.65	1.66	92.31	1.57	68.99	0.00	/workspace/coverage/default/2.chip_sw_sleep_pin_retention.2434055836
83.71	1.09	85.49	0.00	80.51	0.10	81.84	0.00			86.65	0.00	92.31	0.00	75.44	6.45	/workspace/coverage/cover_reg_top/77.xbar_access_same_device_slow_rsp.3921499833
84.58	0.88	86.72	1.23	81.47	0.96	83.78	1.94			87.59	0.94	92.48	0.17	75.46	0.01	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.1086933448
85.45	0.87	86.74	0.01	81.73	0.26	83.78	0.00			87.63	0.03	92.48	0.00	80.35	4.90	/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_reset_error.4216856424
86.27	0.81	87.45	0.71	81.89	0.16	83.79	0.01			87.78	0.15	96.33	3.85	80.35	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.1143902151
86.98	0.71	87.45	0.00	81.89	0.00	83.79	0.00			87.78	0.00	96.33	0.00	84.64	4.29	/workspace/coverage/cover_reg_top/9.xbar_access_same_device_slow_rsp.1648094554
87.69	0.71	88.27	0.82	83.63	1.74	83.85	0.06			89.43	1.65	96.33	0.00	84.64	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.3900741618
88.37	0.67	89.59	1.32	84.63	1.00	84.36	0.51			90.65	1.22	96.33	0.00	84.64	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_20.149321458
88.91	0.54	89.59	0.00	84.63	0.00	84.36	0.00			90.65	0.00	96.33	0.00	87.89	3.24	/workspace/coverage/cover_reg_top/59.xbar_access_same_device_slow_rsp.1275000939
89.42	0.51	89.59	0.00	84.63	0.00	87.42	3.06			90.65	0.00	96.33	0.00	87.89	0.00	/workspace/coverage/default/2.chip_sw_keymgr_sideload_otbn.235925421
89.91	0.50	89.59	0.00	84.76	0.13	87.42	0.00			90.68	0.03	96.33	0.00	90.71	2.82	/workspace/coverage/cover_reg_top/93.xbar_access_same_device_slow_rsp.1509575297
90.37	0.46	89.59	0.00	84.87	0.11	87.42	0.00			90.69	0.02	96.33	0.00	93.35	2.64	/workspace/coverage/cover_reg_top/96.xbar_access_same_device_slow_rsp.3917742669
90.77	0.39	90.42	0.84	85.40	0.53	87.58	0.16			91.53	0.84	96.33	0.00	93.35	0.00	/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.230923510
91.11	0.34	90.98	0.56	86.06	0.65	87.98	0.40			91.98	0.45	96.33	0.00	93.35	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2436710733
91.40	0.28	91.52	0.53	86.54	0.48	88.20	0.22			92.44	0.46	96.33	0.00	93.35	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_10.3462509024
91.68	0.28	92.39	0.88	86.91	0.37	88.22	0.02			92.67	0.23	96.50	0.17	93.36	0.01	/workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.4133447245
91.95	0.27	92.39	0.00	86.92	0.01	88.22	0.00			92.67	0.00	96.50	0.00	94.99	1.63	/workspace/coverage/cover_reg_top/80.xbar_stress_all_with_error.1975454725
92.21	0.27	92.40	0.01	88.42	1.51	88.22	0.00			92.67	0.00	96.50	0.00	95.08	0.08	/workspace/coverage/cover_reg_top/25.chip_tl_errors.1212622487
92.45	0.24	92.61	0.22	88.53	0.10	88.41	0.19			92.68	0.02	96.50	0.00	95.98	0.90	/workspace/coverage/cover_reg_top/24.xbar_stress_all_with_rand_reset.3440255885
92.68	0.23	92.82	0.21	89.63	1.10	88.47	0.07			92.70	0.02	96.50	0.00	95.98	0.00	/workspace/coverage/cover_reg_top/2.chip_same_csr_outstanding.2111468357
92.88	0.19	92.87	0.06	89.64	0.01	89.56	1.09			92.71	0.01	96.50	0.00	95.98	0.00	/workspace/coverage/default/0.rom_e2e_jtag_debug_rma.930340520
93.04	0.17	93.30	0.42	89.86	0.22	89.73	0.17			92.89	0.19	96.50	0.00	95.98	0.00	/workspace/coverage/default/0.chip_sw_gpio_smoketest.2221955034
93.19	0.14	93.55	0.26	90.02	0.16	90.02	0.29			93.05	0.15	96.50	0.00	95.98	0.00	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.2697831925
93.33	0.14	93.61	0.06	90.40	0.37	90.03	0.01			93.44	0.40	96.50	0.00	95.98	0.00	/workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.4000630215
93.47	0.14	93.61	0.00	90.40	0.00	90.87	0.84			93.44	0.00	96.50	0.00	95.98	0.00	/workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.34977123
93.60	0.14	93.77	0.17	90.57	0.17	90.98	0.11			93.63	0.19	96.68	0.17	95.99	0.01	/workspace/coverage/default/5.chip_sw_all_escalation_resets.371539482
93.74	0.14	93.77	0.00	90.57	0.00	90.98	0.00			93.63	0.00	96.68	0.00	96.82	0.82	/workspace/coverage/cover_reg_top/60.xbar_stress_all_with_error.611692123
93.87	0.13	93.77	0.00	90.60	0.03	90.98	0.00			93.63	0.00	96.68	0.00	97.56	0.74	/workspace/coverage/cover_reg_top/0.xbar_random_large_delays.89703228
93.99	0.12	93.77	0.00	90.60	0.00	91.65	0.66			93.63	0.00	96.68	0.00	97.60	0.05	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.3703738840
94.10	0.11	93.79	0.01	90.61	0.01	92.32	0.67			93.63	0.00	96.68	0.00	97.60	0.00	/workspace/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.3288012626
94.20	0.10	93.85	0.07	90.64	0.03	92.79	0.47			93.66	0.03	96.68	0.00	97.60	0.00	/workspace/coverage/default/49.chip_sw_all_escalation_resets.925708580
94.30	0.10	94.02	0.17	90.78	0.14	92.95	0.17			93.78	0.11	96.68	0.00	97.60	0.00	/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.768881432
94.40	0.09	94.02	0.00	91.35	0.57	92.95	0.00			93.78	0.00	96.68	0.00	97.60	0.00	/workspace/coverage/cover_reg_top/0.chip_tl_errors.34518311
94.48	0.08	94.02	0.00	91.35	0.00	93.43	0.48			93.78	0.00	96.68	0.00	97.60	0.00	/workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.3819247359
94.55	0.07	94.03	0.01	91.55	0.20	93.45	0.01			94.00	0.23	96.68	0.00	97.60	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.2396307412
94.62	0.07	94.03	0.00	91.55	0.01	93.45	0.00			94.00	0.00	96.68	0.00	98.00	0.40	/workspace/coverage/cover_reg_top/6.xbar_stress_all_with_reset_error.3492353001
94.68	0.06	94.04	0.01	91.61	0.06	93.56	0.11			94.03	0.02	96.85	0.17	98.00	0.00	/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.3595531224
94.73	0.05	94.15	0.11	91.70	0.08	93.59	0.03			94.11	0.08	96.85	0.00	98.00	0.00	/workspace/coverage/default/0.chip_jtag_csr_rw.2142854021
94.78	0.05	94.15	0.00	91.98	0.28	93.59	0.00			94.11	0.00	96.85	0.00	98.00	0.00	/workspace/coverage/cover_reg_top/21.chip_tl_errors.307479263
94.83	0.05	94.15	0.00	91.98	0.00	93.87	0.28			94.11	0.00	96.85	0.00	98.00	0.00	/workspace/coverage/default/0.chip_sw_flash_rma_unlocked.260983231
94.87	0.04	94.26	0.11	91.99	0.01	93.89	0.03			94.11	0.00	96.85	0.00	98.11	0.11	/workspace/coverage/cover_reg_top/97.xbar_error_random.2084009528
94.91	0.04	94.30	0.04	92.04	0.05	94.01	0.12			94.14	0.03	96.85	0.00	98.11	0.00	/workspace/coverage/cover_reg_top/2.chip_csr_hw_reset.3561818070
94.95	0.04	94.35	0.05	92.05	0.01	94.01	0.01			94.15	0.01	97.03	0.17	98.11	0.00	/workspace/coverage/default/2.chip_sw_data_integrity_escalation.3709700437
94.99	0.04	94.38	0.03	92.06	0.01	94.01	0.01			94.16	0.01	97.20	0.17	98.12	0.01	/workspace/coverage/default/70.chip_sw_all_escalation_resets.2430176476
95.03	0.04	94.38	0.00	92.06	0.00	94.24	0.23			94.16	0.00	97.20	0.00	98.12	0.00	/workspace/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.928275648
95.06	0.04	94.38	0.01	92.07	0.01	94.25	0.01			94.17	0.01	97.38	0.17	98.13	0.01	/workspace/coverage/default/81.chip_sw_all_escalation_resets.3407019566
95.10	0.04	94.38	0.00	92.12	0.05	94.25	0.00			94.17	0.00	97.38	0.00	98.30	0.16	/workspace/coverage/cover_reg_top/78.xbar_stress_all_with_rand_reset.2269842072
95.14	0.04	94.39	0.01	92.14	0.01	94.26	0.01			94.17	0.01	97.55	0.17	98.31	0.01	/workspace/coverage/default/15.chip_sw_all_escalation_resets.1403818054
95.17	0.03	94.42	0.03	92.15	0.01	94.38	0.12			94.19	0.02	97.55	0.00	98.31	0.00	/workspace/coverage/default/1.chip_sw_power_sleep_load.2402310674
95.19	0.03	94.49	0.07	92.18	0.03	94.45	0.07			94.19	0.00	97.55	0.00	98.31	0.00	/workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.1590110399
95.22	0.03	94.49	0.00	92.34	0.16	94.45	0.00			94.19	0.00	97.55	0.00	98.31	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_0.1052720482
95.25	0.03	94.50	0.01	92.41	0.07	94.45	0.00			94.27	0.08	97.55	0.00	98.31	0.00	/workspace/coverage/default/0.chip_sw_spi_device_pinmux_sleep_retention.2094100465
95.27	0.03	94.57	0.07	92.44	0.03	94.45	0.01			94.32	0.05	97.55	0.00	98.31	0.00	/workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.1694923820
95.30	0.02	94.57	0.00	92.44	0.00	94.60	0.15			94.32	0.00	97.55	0.00	98.31	0.00	/workspace/coverage/default/2.chip_sw_exit_test_unlocked_bootstrap.2009272961
95.32	0.02	94.61	0.04	92.49	0.05	94.62	0.02			94.36	0.04	97.55	0.00	98.31	0.00	/workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.3287732479
95.35	0.02	94.61	0.00	92.58	0.10	94.62	0.00			94.38	0.02	97.55	0.00	98.34	0.04	/workspace/coverage/cover_reg_top/6.xbar_stress_all_with_rand_reset.3447266348
95.37	0.02	94.68	0.07	92.58	0.00	94.67	0.05			94.39	0.01	97.55	0.00	98.34	0.00	/workspace/coverage/default/2.chip_tap_straps_testunlock0.2423142823
95.39	0.02	94.75	0.07	92.63	0.05	94.67	0.00			94.40	0.02	97.55	0.00	98.34	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_wake.603300908
95.41	0.02	94.81	0.07	92.68	0.05	94.67	0.00			94.42	0.02	97.55	0.00	98.34	0.00	/workspace/coverage/default/2.chip_sw_sleep_pin_wake.94415958
95.43	0.02	94.81	0.00	92.68	0.00	94.79	0.12			94.42	0.00	97.55	0.00	98.34	0.00	/workspace/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.2006898987
95.45	0.02	94.81	0.00	92.77	0.10	94.79	0.00			94.44	0.02	97.55	0.00	98.34	0.00	/workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.1635198973
95.47	0.02	94.81	0.00	92.77	0.00	94.79	0.00			94.44	0.00	97.55	0.00	98.46	0.12	/workspace/coverage/cover_reg_top/48.xbar_access_same_device.1371276171
95.49	0.02	94.81	0.00	92.83	0.06	94.79	0.00			94.44	0.00	97.55	0.00	98.51	0.05	/workspace/coverage/cover_reg_top/38.xbar_stress_all_with_rand_reset.3995613207
95.51	0.02	94.81	0.00	92.83	0.00	94.90	0.10			94.44	0.00	97.55	0.00	98.51	0.00	/workspace/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.1794724277
95.52	0.02	94.84	0.03	92.88	0.05	94.90	0.00			94.47	0.02	97.55	0.00	98.51	0.00	/workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.4076752151
95.54	0.02	94.84	0.00	92.98	0.10	94.90	0.00			94.47	0.00	97.55	0.00	98.51	0.00	/workspace/coverage/cover_reg_top/24.chip_tl_errors.1558100847
95.56	0.02	94.84	0.00	93.07	0.09	94.90	0.00			94.47	0.00	97.55	0.00	98.51	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_0.2659487159
95.57	0.01	94.84	0.00	93.16	0.09	94.90	0.00			94.47	0.00	97.55	0.00	98.51	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_20.1778274820
95.58	0.01	94.84	0.00	93.20	0.04	94.90	0.00			94.48	0.02	97.55	0.00	98.53	0.02	/workspace/coverage/cover_reg_top/71.xbar_stress_all_with_rand_reset.3545355728
95.59	0.01	94.84	0.00	93.21	0.01	94.90	0.00			94.48	0.00	97.55	0.00	98.59	0.06	/workspace/coverage/cover_reg_top/76.xbar_stress_all_with_rand_reset.3165557239
95.60	0.01	94.84	0.00	93.21	0.00	94.95	0.06			94.48	0.00	97.55	0.00	98.59	0.00	/workspace/coverage/default/1.chip_sw_flash_rma_unlocked.417541845
95.61	0.01	94.84	0.00	93.26	0.05	94.95	0.00			94.48	0.00	97.55	0.00	98.59	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_20.4042733154
95.62	0.01	94.86	0.02	93.27	0.01	94.96	0.01			94.50	0.02	97.55	0.00	98.59	0.00	/workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.1248138942
95.63	0.01	94.88	0.02	93.27	0.01	94.96	0.01			94.52	0.02	97.55	0.00	98.59	0.00	/workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.3779340327
95.64	0.01	94.89	0.01	93.32	0.05	94.96	0.00			94.52	0.00	97.55	0.00	98.59	0.00	/workspace/coverage/cover_reg_top/7.chip_same_csr_outstanding.2603425545
95.65	0.01	94.89	0.00	93.32	0.00	95.00	0.04			94.52	0.00	97.55	0.00	98.60	0.01	/workspace/coverage/default/22.chip_sw_all_escalation_resets.2922496536
95.65	0.01	94.89	0.00	93.34	0.02	95.00	0.00			94.52	0.00	97.55	0.00	98.63	0.02	/workspace/coverage/cover_reg_top/29.xbar_stress_all.3857654086
95.66	0.01	94.89	0.00	93.34	0.00	95.04	0.04			94.52	0.00	97.55	0.00	98.63	0.00	/workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.3718660824
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95.67	0.01	94.89	0.00	93.42	0.04	95.04	0.00			94.52	0.00	97.55	0.00	98.63	0.00	/workspace/coverage/cover_reg_top/62.xbar_stress_all_with_rand_reset.2765525986
95.68	0.01	94.89	0.00	93.42	0.00	95.04	0.00			94.52	0.00	97.55	0.00	98.66	0.04	/workspace/coverage/cover_reg_top/35.xbar_stress_all_with_reset_error.3959959227
95.68	0.01	94.89	0.00	93.43	0.01	95.04	0.00			94.52	0.00	97.55	0.00	98.68	0.02	/workspace/coverage/cover_reg_top/84.xbar_stress_all.950651003
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95.71	0.01	94.89	0.00	93.46	0.00	95.16	0.03			94.52	0.00	97.55	0.00	98.68	0.00	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.1239300172
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95.72	0.01	94.89	0.00	93.47	0.00	95.16	0.00			94.52	0.00	97.55	0.00	98.74	0.02	/workspace/coverage/cover_reg_top/33.xbar_stress_all_with_reset_error.1654874010
95.73	0.01	94.89	0.00	93.47	0.00	95.16	0.00			94.52	0.00	97.55	0.00	98.77	0.02	/workspace/coverage/cover_reg_top/54.xbar_stress_all_with_reset_error.3772438966
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95.74	0.01	94.89	0.01	93.50	0.01	95.20	0.01			94.52	0.00	97.55	0.00	98.78	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.1685716668
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95.78	0.01	94.89	0.00	93.57	0.00	95.26	0.00			94.52	0.00	97.55	0.00	98.91	0.01	/workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.3702617695
95.79	0.01	94.89	0.00	93.57	0.00	95.26	0.00			94.52	0.00	97.55	0.00	98.92	0.01	/workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.2654781414
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95.79	0.01	94.89	0.00	93.57	0.00	95.26	0.00			94.52	0.00	97.55	0.00	98.95	0.01	/workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.3864259607
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95.79	0.01	94.89	0.00	93.57	0.00	95.26	0.00			94.52	0.00	97.55	0.00	98.98	0.01	/workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.2968199804
95.80	0.01	94.89	0.00	93.57	0.00	95.26	0.00			94.52	0.00	97.55	0.00	98.99	0.01	/workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.3142047968
95.80	0.01	94.89	0.00	93.57	0.00	95.26	0.00			94.52	0.00	97.55	0.00	99.00	0.01	/workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.1005902276
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95.80	0.01	94.89	0.00	93.57	0.00	95.26	0.00			94.52	0.00	97.55	0.00	99.02	0.01	/workspace/coverage/default/19.chip_sw_all_escalation_resets.515255893
95.80	0.01	94.89	0.00	93.57	0.00	95.26	0.00			94.52	0.00	97.55	0.00	99.04	0.01	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.3585752486
95.81	0.01	94.89	0.00	93.57	0.00	95.26	0.00			94.52	0.00	97.55	0.00	99.05	0.01	/workspace/coverage/default/2.chip_sw_all_escalation_resets.32525141
95.81	0.01	94.89	0.00	93.57	0.00	95.26	0.00			94.52	0.00	97.55	0.00	99.06	0.01	/workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.2122907687
95.81	0.01	94.89	0.00	93.57	0.00	95.26	0.00			94.52	0.00	97.55	0.00	99.07	0.01	/workspace/coverage/default/20.chip_sw_all_escalation_resets.4177882647
95.81	0.01	94.89	0.00	93.57	0.00	95.26	0.00			94.52	0.00	97.55	0.00	99.08	0.01	/workspace/coverage/default/21.chip_sw_all_escalation_resets.135166798
95.81	0.01	94.89	0.00	93.57	0.00	95.26	0.00			94.52	0.00	97.55	0.00	99.10	0.01	/workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.3504371874
95.82	0.01	94.89	0.00	93.57	0.00	95.26	0.00			94.52	0.00	97.55	0.00	99.11	0.01	/workspace/coverage/default/23.chip_sw_all_escalation_resets.2171993644
95.82	0.01	94.89	0.00	93.57	0.00	95.26	0.00			94.52	0.00	97.55	0.00	99.12	0.01	/workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.1120945283
95.82	0.01	94.89	0.00	93.57	0.00	95.26	0.00			94.52	0.00	97.55	0.00	99.13	0.01	/workspace/coverage/default/25.chip_sw_all_escalation_resets.442927021
95.82	0.01	94.89	0.00	93.57	0.00	95.26	0.00			94.52	0.00	97.55	0.00	99.14	0.01	/workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.3483109965
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95.83	0.01	94.89	0.00	93.57	0.00	95.26	0.00			94.52	0.00	97.55	0.00	99.17	0.01	/workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.2621965159
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95.83	0.01	94.89	0.00	93.57	0.00	95.26	0.00			94.52	0.00	97.55	0.00	99.20	0.01	/workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.2277940008
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95.89	0.01	94.89	0.00	93.57	0.00	95.26	0.00			94.52	0.00	97.55	0.00	99.53	0.01	/workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.448550249
95.89	0.01	94.89	0.00	93.57	0.00	95.26	0.00			94.52	0.00	97.55	0.00	99.54	0.01	/workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.1753938398
95.89	0.01	94.89	0.00	93.57	0.00	95.26	0.00			94.52	0.00	97.55	0.00	99.55	0.01	/workspace/coverage/default/94.chip_sw_all_escalation_resets.2606893093
95.89	0.01	94.89	0.00	93.57	0.00	95.26	0.00			94.52	0.00	97.55	0.00	99.57	0.01	/workspace/coverage/default/97.chip_sw_all_escalation_resets.2858990519
95.89	0.01	94.89	0.00	93.57	0.00	95.27	0.01			94.52	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.2937206047
95.90	0.01	94.89	0.00	93.58	0.01	95.27	0.00			94.52	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.476747321
95.90	0.01	94.89	0.00	93.59	0.01	95.27	0.00			94.52	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/1.chip_sw_entropy_src_csrng.1510656853
95.90	0.01	94.89	0.00	93.60	0.01	95.27	0.00			94.52	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/2.chip_sw_gpio.248991510
95.90	0.01	94.89	0.00	93.61	0.01	95.27	0.00			94.52	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx1.1379436445
95.90	0.01	94.90	0.01	93.61	0.00	95.28	0.01			94.52	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/69.chip_sw_all_escalation_resets.2082742005
95.91	0.01	94.90	0.00	93.61	0.00	95.29	0.01			94.52	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.2241487549
95.91	0.01	94.90	0.00	93.61	0.00	95.30	0.01			94.52	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.1255233022
95.91	0.01	94.90	0.00	93.61	0.00	95.30	0.00			94.52	0.01	97.55	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.1939954335
95.91	0.01	94.90	0.00	93.61	0.00	95.30	0.00			94.53	0.01	97.55	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.2116726828
95.91	0.01	94.90	0.00	93.61	0.00	95.30	0.00			94.54	0.01	97.55	0.00	99.57	0.00	/workspace/coverage/default/0.chip_tap_straps_dev.3630241644
95.91	0.01	94.90	0.00	93.62	0.01	95.30	0.00			94.54	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/cover_reg_top/20.chip_tl_errors.2651411594
95.91	0.01	94.90	0.00	93.63	0.01	95.30	0.00			94.54	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/cover_reg_top/31.xbar_stress_all.220061936
95.91	0.01	94.90	0.00	93.64	0.01	95.30	0.00			94.54	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/cover_reg_top/36.xbar_stress_all_with_error.338264386
95.92	0.01	94.90	0.00	93.64	0.01	95.30	0.00			94.54	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.3502339360
95.92	0.01	94.90	0.00	93.65	0.01	95.30	0.00			94.54	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.2675949168
95.92	0.01	94.90	0.00	93.66	0.01	95.30	0.00			94.54	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_rstmgr_alert_info.113056957
95.92	0.01	94.90	0.00	93.66	0.01	95.30	0.00			94.54	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_10.1800568370
95.92	0.01	94.90	0.00	93.67	0.01	95.30	0.00			94.54	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2613839305
95.92	0.01	94.90	0.00	93.67	0.00	95.30	0.01			94.54	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/cover_reg_top/0.chip_csr_hw_reset.3987871097
95.92	0.01	94.90	0.00	93.67	0.00	95.31	0.01			94.54	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_ast_clk_rst_inputs.3591641829
95.92	0.01	94.90	0.00	93.67	0.00	95.32	0.01			94.54	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_lc_ctrl_program_error.2960740308
95.92	0.01	94.90	0.00	93.67	0.00	95.32	0.01			94.54	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_ast_clk_outputs.1155177692
95.93	0.01	94.90	0.00	93.67	0.00	95.33	0.01			94.54	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock.3970378740
95.93	0.01	94.90	0.00	93.67	0.00	95.33	0.01			94.54	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.691697036
95.93	0.01	94.90	0.00	93.67	0.00	95.34	0.01			94.54	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.3624023200
95.93	0.01	94.90	0.00	93.67	0.01	95.34	0.00			94.54	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/cover_reg_top/16.xbar_stress_all_with_error.1889482017
95.93	0.01	94.90	0.00	93.68	0.01	95.34	0.00			94.54	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/cover_reg_top/29.xbar_stress_all_with_error.3213630186
95.93	0.01	94.90	0.00	93.68	0.01	95.34	0.00			94.54	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/cover_reg_top/34.xbar_stress_all_with_error.1916886570
95.93	0.01	94.90	0.00	93.69	0.01	95.34	0.00			94.54	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/cover_reg_top/39.xbar_stress_all_with_error.2309857366
95.93	0.01	94.90	0.00	93.69	0.01	95.34	0.00			94.54	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/cover_reg_top/44.xbar_stress_all_with_error.1645850932
95.93	0.01	94.90	0.00	93.69	0.01	95.34	0.00			94.54	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/cover_reg_top/82.xbar_stress_all_with_error.3774668704
95.93	0.01	94.90	0.00	93.70	0.01	95.34	0.00			94.54	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en.3975955660
95.93	0.01	94.90	0.00	93.70	0.01	95.34	0.00			94.54	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.9738947
95.93	0.01	94.90	0.00	93.70	0.01	95.34	0.00			94.54	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.1403456902
95.93	0.01	94.90	0.00	93.71	0.01	95.34	0.00			94.54	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/1.chip_jtag_csr_rw.2410091547
95.93	0.01	94.90	0.00	93.71	0.00	95.34	0.01			94.54	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_aes_enc.2871129485
95.93	0.01	94.90	0.00	93.71	0.00	95.34	0.01			94.54	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_edn_boot_mode.2540244259
95.93	0.01	94.90	0.00	93.71	0.00	95.34	0.01			94.54	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.3086000044
95.93	0.01	94.90	0.00	93.71	0.00	95.34	0.01			94.54	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.1336616618
95.93	0.01	94.90	0.00	93.71	0.00	95.35	0.01			94.54	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.4148341712

---

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.chip_csr_bit_bash.1097396250
/workspace/coverage/cover_reg_top/0.chip_csr_mem_rw_with_rand_reset.1833842151
/workspace/coverage/cover_reg_top/0.chip_csr_rw.368902999
/workspace/coverage/cover_reg_top/0.chip_prim_tl_access.4259977524
/workspace/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.714873135
/workspace/coverage/cover_reg_top/0.chip_same_csr_outstanding.1525479194
/workspace/coverage/cover_reg_top/0.xbar_access_same_device.3012920891
/workspace/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.4244034559
/workspace/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.3103967342
/workspace/coverage/cover_reg_top/0.xbar_error_random.3218386126
/workspace/coverage/cover_reg_top/0.xbar_random.3400508601
/workspace/coverage/cover_reg_top/0.xbar_random_slow_rsp.3392241573
/workspace/coverage/cover_reg_top/0.xbar_random_zero_delays.2089204670
/workspace/coverage/cover_reg_top/0.xbar_same_source.673341883
/workspace/coverage/cover_reg_top/0.xbar_smoke.2128166061
/workspace/coverage/cover_reg_top/0.xbar_smoke_large_delays.2743698319
/workspace/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.3869880112
/workspace/coverage/cover_reg_top/0.xbar_smoke_zero_delays.1095699956
/workspace/coverage/cover_reg_top/0.xbar_stress_all.2934031870
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_error.2597837580
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.3217459473
/workspace/coverage/cover_reg_top/0.xbar_unmapped_addr.2675971258
/workspace/coverage/cover_reg_top/1.chip_csr_aliasing.2472027517
/workspace/coverage/cover_reg_top/1.chip_csr_bit_bash.1371946297
/workspace/coverage/cover_reg_top/1.chip_csr_hw_reset.730960496
/workspace/coverage/cover_reg_top/1.chip_csr_mem_rw_with_rand_reset.3003544370
/workspace/coverage/cover_reg_top/1.chip_csr_rw.2502851806
/workspace/coverage/cover_reg_top/1.chip_prim_tl_access.339868495
/workspace/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.195489942
/workspace/coverage/cover_reg_top/1.chip_same_csr_outstanding.1625910311
/workspace/coverage/cover_reg_top/1.chip_tl_errors.943516352
/workspace/coverage/cover_reg_top/1.xbar_access_same_device.4147300742
/workspace/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.2757760918
/workspace/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.4199260794
/workspace/coverage/cover_reg_top/1.xbar_error_random.149510998
/workspace/coverage/cover_reg_top/1.xbar_random.1653964415
/workspace/coverage/cover_reg_top/1.xbar_random_large_delays.2024006898
/workspace/coverage/cover_reg_top/1.xbar_random_slow_rsp.98629034
/workspace/coverage/cover_reg_top/1.xbar_random_zero_delays.2170888912
/workspace/coverage/cover_reg_top/1.xbar_same_source.762672361
/workspace/coverage/cover_reg_top/1.xbar_smoke.1901009952
/workspace/coverage/cover_reg_top/1.xbar_smoke_large_delays.3493551946
/workspace/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.112619770
/workspace/coverage/cover_reg_top/1.xbar_smoke_zero_delays.403751168
/workspace/coverage/cover_reg_top/1.xbar_stress_all.4038669837
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_error.1614373751
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.3181767116
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.2866393430
/workspace/coverage/cover_reg_top/1.xbar_unmapped_addr.289850954
/workspace/coverage/cover_reg_top/10.chip_csr_mem_rw_with_rand_reset.3816824592
/workspace/coverage/cover_reg_top/10.chip_csr_rw.3889975188
/workspace/coverage/cover_reg_top/10.chip_same_csr_outstanding.1379903023
/workspace/coverage/cover_reg_top/10.chip_tl_errors.2508305289
/workspace/coverage/cover_reg_top/10.xbar_access_same_device.2675367389
/workspace/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.2808061577
/workspace/coverage/cover_reg_top/10.xbar_error_random.2052277932
/workspace/coverage/cover_reg_top/10.xbar_random.2939179866
/workspace/coverage/cover_reg_top/10.xbar_random_large_delays.3669915918
/workspace/coverage/cover_reg_top/10.xbar_random_slow_rsp.752659909
/workspace/coverage/cover_reg_top/10.xbar_random_zero_delays.633210435
/workspace/coverage/cover_reg_top/10.xbar_same_source.2963863443
/workspace/coverage/cover_reg_top/10.xbar_smoke.1532330106
/workspace/coverage/cover_reg_top/10.xbar_smoke_large_delays.3765187644
/workspace/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.3428622456
/workspace/coverage/cover_reg_top/10.xbar_smoke_zero_delays.1177595374
/workspace/coverage/cover_reg_top/10.xbar_stress_all.1526389720
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_error.3940929365
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.88136936
/workspace/coverage/cover_reg_top/10.xbar_unmapped_addr.1751423779
/workspace/coverage/cover_reg_top/11.chip_csr_mem_rw_with_rand_reset.499144850
/workspace/coverage/cover_reg_top/11.chip_csr_rw.1956604329
/workspace/coverage/cover_reg_top/11.chip_same_csr_outstanding.256832967
/workspace/coverage/cover_reg_top/11.chip_tl_errors.903288801
/workspace/coverage/cover_reg_top/11.xbar_access_same_device.3049039991
/workspace/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.3513463566
/workspace/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.577355229
/workspace/coverage/cover_reg_top/11.xbar_error_random.4001144790
/workspace/coverage/cover_reg_top/11.xbar_random.1135617427
/workspace/coverage/cover_reg_top/11.xbar_random_large_delays.1967682424
/workspace/coverage/cover_reg_top/11.xbar_random_slow_rsp.1367588335
/workspace/coverage/cover_reg_top/11.xbar_random_zero_delays.395419956
/workspace/coverage/cover_reg_top/11.xbar_same_source.1448754201
/workspace/coverage/cover_reg_top/11.xbar_smoke.139535498
/workspace/coverage/cover_reg_top/11.xbar_smoke_large_delays.809997675
/workspace/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.49099737
/workspace/coverage/cover_reg_top/11.xbar_smoke_zero_delays.3627506125
/workspace/coverage/cover_reg_top/11.xbar_stress_all.146609726
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_error.3451102619
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.2844487931
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.2404294566
/workspace/coverage/cover_reg_top/11.xbar_unmapped_addr.1417339776
/workspace/coverage/cover_reg_top/12.chip_csr_mem_rw_with_rand_reset.340908496
/workspace/coverage/cover_reg_top/12.chip_csr_rw.459446538
/workspace/coverage/cover_reg_top/12.chip_same_csr_outstanding.569050366
/workspace/coverage/cover_reg_top/12.chip_tl_errors.1352635862
/workspace/coverage/cover_reg_top/12.xbar_access_same_device.2300597192
/workspace/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.3523788437
/workspace/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.2296611409
/workspace/coverage/cover_reg_top/12.xbar_error_random.1328602922
/workspace/coverage/cover_reg_top/12.xbar_random.1986207279
/workspace/coverage/cover_reg_top/12.xbar_random_large_delays.1888059680
/workspace/coverage/cover_reg_top/12.xbar_random_slow_rsp.2707192773
/workspace/coverage/cover_reg_top/12.xbar_random_zero_delays.699764995
/workspace/coverage/cover_reg_top/12.xbar_same_source.1106997097
/workspace/coverage/cover_reg_top/12.xbar_smoke.3725481665
/workspace/coverage/cover_reg_top/12.xbar_smoke_large_delays.1266979325
/workspace/coverage/cover_reg_top/12.xbar_smoke_slow_rsp.1164026098
/workspace/coverage/cover_reg_top/12.xbar_smoke_zero_delays.4234940088
/workspace/coverage/cover_reg_top/12.xbar_stress_all.1739704476
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_error.2876264626
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_rand_reset.2806241413
/workspace/coverage/cover_reg_top/12.xbar_unmapped_addr.3043110172
/workspace/coverage/cover_reg_top/13.chip_csr_mem_rw_with_rand_reset.603594421
/workspace/coverage/cover_reg_top/13.chip_csr_rw.3389791313
/workspace/coverage/cover_reg_top/13.chip_same_csr_outstanding.3035247511
/workspace/coverage/cover_reg_top/13.chip_tl_errors.1277049791
/workspace/coverage/cover_reg_top/13.xbar_access_same_device.3898018633
/workspace/coverage/cover_reg_top/13.xbar_access_same_device_slow_rsp.4014546451
/workspace/coverage/cover_reg_top/13.xbar_error_and_unmapped_addr.1054923652
/workspace/coverage/cover_reg_top/13.xbar_error_random.37340868
/workspace/coverage/cover_reg_top/13.xbar_random.3999296735
/workspace/coverage/cover_reg_top/13.xbar_random_large_delays.2157040393
/workspace/coverage/cover_reg_top/13.xbar_random_slow_rsp.422004697
/workspace/coverage/cover_reg_top/13.xbar_random_zero_delays.1594585495
/workspace/coverage/cover_reg_top/13.xbar_same_source.3567794892
/workspace/coverage/cover_reg_top/13.xbar_smoke.243857282
/workspace/coverage/cover_reg_top/13.xbar_smoke_large_delays.881355589
/workspace/coverage/cover_reg_top/13.xbar_smoke_slow_rsp.879023943
/workspace/coverage/cover_reg_top/13.xbar_smoke_zero_delays.2145384054
/workspace/coverage/cover_reg_top/13.xbar_stress_all.1792497385
/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_error.696195586
/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_rand_reset.3505681939
/workspace/coverage/cover_reg_top/13.xbar_unmapped_addr.4091908114
/workspace/coverage/cover_reg_top/14.chip_csr_mem_rw_with_rand_reset.2456255350
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/workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.2747639470
/workspace/coverage/default/2.chip_sw_spi_device_pass_through.1045353298
/workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.1851248821
/workspace/coverage/default/2.chip_sw_spi_device_pinmux_sleep_retention.2805861394
/workspace/coverage/default/2.chip_sw_spi_device_tpm.3190843974
/workspace/coverage/default/2.chip_sw_spi_host_tx_rx.2353492646
/workspace/coverage/default/2.chip_sw_sram_ctrl_execution_main.1164213170
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/workspace/coverage/default/2.chip_sw_sram_ctrl_smoketest.3181177689
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.2655533005
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.2981641008
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/workspace/coverage/default/2.rom_e2e_shutdown_output.2616269940
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/workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.2229556862
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/workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.1524824876
/workspace/coverage/default/27.chip_sw_all_escalation_resets.2997510202
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/workspace/coverage/default/3.chip_tap_straps_rma.1871504551
/workspace/coverage/default/3.chip_tap_straps_testunlock0.954078130
/workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.2745953265
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/workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.2858635684
/workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.4183460945
/workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.4146005305
/workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.811728927
/workspace/coverage/default/34.chip_sw_all_escalation_resets.2529960778
/workspace/coverage/default/35.chip_sw_all_escalation_resets.1226000310
/workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.2282723834
/workspace/coverage/default/36.chip_sw_all_escalation_resets.1842101890
/workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.4174016308
/workspace/coverage/default/37.chip_sw_all_escalation_resets.3991587903
/workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.6471484
/workspace/coverage/default/39.chip_sw_all_escalation_resets.603797301
/workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.1955557391
/workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.4010866943
/workspace/coverage/default/4.chip_sw_csrng_edn_concurrency.2262058337
/workspace/coverage/default/4.chip_sw_data_integrity_escalation.2354040587
/workspace/coverage/default/4.chip_sw_lc_ctrl_transition.4223299371
/workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.2007770229
/workspace/coverage/default/4.chip_sw_uart_rand_baudrate.2410375505
/workspace/coverage/default/4.chip_sw_uart_tx_rx.3937014701
/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.2119089157
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.2130977729
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.2880394355
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.1997734197
/workspace/coverage/default/4.chip_tap_straps_dev.3495878347
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/workspace/coverage/default/4.chip_tap_straps_rma.3863144760
/workspace/coverage/default/4.chip_tap_straps_testunlock0.854705117
/workspace/coverage/default/40.chip_sw_all_escalation_resets.845231593
/workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.148653854
/workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.970408908
/workspace/coverage/default/42.chip_sw_all_escalation_resets.3160583877
/workspace/coverage/default/43.chip_sw_all_escalation_resets.1668787169
/workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.1689214310
/workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.3786207802
/workspace/coverage/default/45.chip_sw_all_escalation_resets.1015115262
/workspace/coverage/default/46.chip_sw_all_escalation_resets.3417087114
/workspace/coverage/default/47.chip_sw_all_escalation_resets.3347325678
/workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.3388502403
/workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.2824085505
/workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.2657127944
/workspace/coverage/default/5.chip_sw_csrng_edn_concurrency.1283328091
/workspace/coverage/default/5.chip_sw_data_integrity_escalation.1228422071
/workspace/coverage/default/5.chip_sw_lc_ctrl_transition.2553192451
/workspace/coverage/default/5.chip_sw_uart_rand_baudrate.905322076
/workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.2381461323
/workspace/coverage/default/51.chip_sw_all_escalation_resets.3542737375
/workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.436485277
/workspace/coverage/default/53.chip_sw_all_escalation_resets.3682488570
/workspace/coverage/default/54.chip_sw_all_escalation_resets.2103716251
/workspace/coverage/default/55.chip_sw_all_escalation_resets.972484850
/workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.86749870
/workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.3579721183
/workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.1151946945
/workspace/coverage/default/58.chip_sw_all_escalation_resets.1365585513
/workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.1989467146
/workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.2179113094
/workspace/coverage/default/6.chip_sw_all_escalation_resets.742716021
/workspace/coverage/default/6.chip_sw_csrng_edn_concurrency.3699952303
/workspace/coverage/default/6.chip_sw_lc_ctrl_transition.2122054096
/workspace/coverage/default/6.chip_sw_uart_rand_baudrate.305000919
/workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.589726590
/workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.3453560569
/workspace/coverage/default/61.chip_sw_all_escalation_resets.1523376435
/workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.3558396586
/workspace/coverage/default/62.chip_sw_all_escalation_resets.778575803
/workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.1241591598
/workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.3647156169
/workspace/coverage/default/64.chip_sw_all_escalation_resets.3070655534
/workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.1930972957
/workspace/coverage/default/65.chip_sw_all_escalation_resets.2101857472
/workspace/coverage/default/66.chip_sw_all_escalation_resets.1023343551
/workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.3546386535
/workspace/coverage/default/67.chip_sw_all_escalation_resets.1825387949
/workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.1502136899
/workspace/coverage/default/68.chip_sw_all_escalation_resets.629618272
/workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.2043998652
/workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.2818163815
/workspace/coverage/default/7.chip_sw_csrng_edn_concurrency.2247244093
/workspace/coverage/default/7.chip_sw_lc_ctrl_transition.3464655684
/workspace/coverage/default/7.chip_sw_uart_rand_baudrate.1930066054
/workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.2911403708
/workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.1962433762
/workspace/coverage/default/71.chip_sw_all_escalation_resets.4096047670
/workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.1696037911
/workspace/coverage/default/72.chip_sw_all_escalation_resets.1972239953
/workspace/coverage/default/73.chip_sw_all_escalation_resets.1497976255
/workspace/coverage/default/74.chip_sw_all_escalation_resets.889968404
/workspace/coverage/default/75.chip_sw_all_escalation_resets.3850410967
/workspace/coverage/default/76.chip_sw_all_escalation_resets.3093623095
/workspace/coverage/default/77.chip_sw_all_escalation_resets.567575223
/workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.687527536
/workspace/coverage/default/78.chip_sw_all_escalation_resets.1999088114
/workspace/coverage/default/79.chip_sw_all_escalation_resets.2307977528
/workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.631434779
/workspace/coverage/default/8.chip_sw_all_escalation_resets.2768277144
/workspace/coverage/default/8.chip_sw_csrng_edn_concurrency.162840415
/workspace/coverage/default/8.chip_sw_lc_ctrl_transition.2241364220
/workspace/coverage/default/8.chip_sw_uart_rand_baudrate.2047912864
/workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.2080295033
/workspace/coverage/default/80.chip_sw_all_escalation_resets.832547445
/workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.3399784460
/workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.815370230
/workspace/coverage/default/82.chip_sw_all_escalation_resets.3629286366
/workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.1885022241
/workspace/coverage/default/83.chip_sw_all_escalation_resets.435848577
/workspace/coverage/default/84.chip_sw_all_escalation_resets.664175777
/workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.3078001705
/workspace/coverage/default/85.chip_sw_all_escalation_resets.17382969
/workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.649576836
/workspace/coverage/default/86.chip_sw_all_escalation_resets.3017381427
/workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.805806031
/workspace/coverage/default/87.chip_sw_all_escalation_resets.3925774675
/workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.2657336068
/workspace/coverage/default/88.chip_sw_all_escalation_resets.2444831063
/workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.978987234
/workspace/coverage/default/89.chip_sw_all_escalation_resets.558950381
/workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.2381756138
/workspace/coverage/default/9.chip_sw_all_escalation_resets.4229040617
/workspace/coverage/default/9.chip_sw_csrng_edn_concurrency.1515135179
/workspace/coverage/default/9.chip_sw_lc_ctrl_transition.473117019
/workspace/coverage/default/9.chip_sw_uart_rand_baudrate.2866487791
/workspace/coverage/default/90.chip_sw_all_escalation_resets.3137992217
/workspace/coverage/default/91.chip_sw_all_escalation_resets.1506525926
/workspace/coverage/default/92.chip_sw_all_escalation_resets.435109366
/workspace/coverage/default/93.chip_sw_all_escalation_resets.4003833228
/workspace/coverage/default/95.chip_sw_all_escalation_resets.2319281353
/workspace/coverage/default/96.chip_sw_all_escalation_resets.1890108360
/workspace/coverage/default/98.chip_sw_all_escalation_resets.1253977176
/workspace/coverage/default/99.chip_sw_all_escalation_resets.2616100611
/workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.1013253395
/workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.4134806719
/workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.2746960665
/workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.2828813347
/workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.1817662295
/workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.4212134968
/workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.68185628
/workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.3468217769

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Total test records in report: 2943

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TEST NO	TEST LOCATION	TEST NAME	STATUS	STARTED	FINISHED	SIMULATION TIME
T1	/workspace/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.3197868937			Aug 12 07:13:32 PM PDT 24	Aug 12 07:20:24 PM PDT 24	7558833600 ps
T2	/workspace/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.1970885329			Aug 12 07:20:09 PM PDT 24	Aug 12 07:24:01 PM PDT 24	2610208920 ps
T3	/workspace/coverage/default/0.chip_sw_aes_enc_jitter_en.2053924547			Aug 12 07:10:00 PM PDT 24	Aug 12 07:14:22 PM PDT 24	2750680071 ps
T4	/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.230923510			Aug 12 07:30:49 PM PDT 24	Aug 12 07:41:12 PM PDT 24	3867568244 ps
T87	/workspace/coverage/default/2.chip_sw_otp_ctrl_ecc_error_vendor_test.4265813544			Aug 12 07:26:23 PM PDT 24	Aug 12 07:32:02 PM PDT 24	3793719547 ps
T5	/workspace/coverage/default/1.chip_sw_rv_plic_smoketest.2480644654			Aug 12 07:20:57 PM PDT 24	Aug 12 07:26:29 PM PDT 24	2985041996 ps
T6	/workspace/coverage/default/56.chip_sw_all_escalation_resets.3048952077			Aug 12 07:38:48 PM PDT 24	Aug 12 07:50:10 PM PDT 24	5624586738 ps
T35	/workspace/coverage/default/0.chip_sw_lc_ctrl_program_error.2960740308			Aug 12 07:09:15 PM PDT 24	Aug 12 07:17:15 PM PDT 24	5825634264 ps
T7	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.1086933448			Aug 12 07:18:27 PM PDT 24	Aug 12 08:38:00 PM PDT 24	14041283570 ps
T8	/workspace/coverage/default/0.chip_sw_rom_ctrl_integrity_check.3965742097			Aug 12 07:10:51 PM PDT 24	Aug 12 07:22:08 PM PDT 24	9784400582 ps
T122	/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.1361308886			Aug 12 07:19:53 PM PDT 24	Aug 12 07:46:59 PM PDT 24	10148874774 ps
T66	/workspace/coverage/default/22.chip_sw_all_escalation_resets.2922496536			Aug 12 07:35:15 PM PDT 24	Aug 12 07:45:47 PM PDT 24	5048858888 ps
T52	/workspace/coverage/default/2.chip_sw_lc_walkthrough_dev.2347032120			Aug 12 07:24:25 PM PDT 24	Aug 12 08:53:00 PM PDT 24	50107357311 ps
T391	/workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en.2019507822			Aug 12 07:27:23 PM PDT 24	Aug 12 07:34:08 PM PDT 24	2923923387 ps
T50	/workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_invalid_meas.3055824496			Aug 12 07:16:47 PM PDT 24	Aug 12 08:19:18 PM PDT 24	14620311904 ps
T51	/workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_no_meas.3335447663			Aug 12 07:25:20 PM PDT 24	Aug 12 08:19:33 PM PDT 24	15172664224 ps
T203	/workspace/coverage/default/13.chip_sw_all_escalation_resets.777605001			Aug 12 07:34:38 PM PDT 24	Aug 12 07:45:01 PM PDT 24	4746030114 ps
T392	/workspace/coverage/default/2.chip_sw_example_rom.122092941			Aug 12 07:21:24 PM PDT 24	Aug 12 07:23:22 PM PDT 24	2624892260 ps
T55	/workspace/coverage/default/0.rom_e2e_jtag_debug_rma.930340520			Aug 12 07:10:38 PM PDT 24	Aug 12 07:44:06 PM PDT 24	11774372862 ps
T318	/workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.308435949			Aug 12 07:41:29 PM PDT 24	Aug 12 07:47:42 PM PDT 24	3509396280 ps
T53	/workspace/coverage/default/2.chip_sw_lc_ctrl_transition.766345329			Aug 12 07:24:28 PM PDT 24	Aug 12 07:43:30 PM PDT 24	12379662813 ps
T409	/workspace/coverage/default/1.chip_sw_flash_ctrl_clock_freqs.1592582770			Aug 12 07:13:54 PM PDT 24	Aug 12 07:36:32 PM PDT 24	6282863184 ps
T257	/workspace/coverage/default/1.chip_sw_aon_timer_smoketest.1529236412			Aug 12 07:21:14 PM PDT 24	Aug 12 07:28:15 PM PDT 24	3397769154 ps
T123	/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en.3827079192			Aug 12 07:16:12 PM PDT 24	Aug 12 07:35:38 PM PDT 24	8081958725 ps
T130	/workspace/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.350462923			Aug 12 07:17:49 PM PDT 24	Aug 12 07:48:40 PM PDT 24	18825810818 ps
T319	/workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.2161768624			Aug 12 07:34:56 PM PDT 24	Aug 12 07:41:42 PM PDT 24	4183672236 ps
T160	/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx2.2011661971			Aug 12 07:22:12 PM PDT 24	Aug 12 07:32:37 PM PDT 24	4484440334 ps
T966	/workspace/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.2217965861			Aug 12 07:11:59 PM PDT 24	Aug 12 07:15:10 PM PDT 24	2958486000 ps
T57	/workspace/coverage/default/0.chip_sw_alert_test.817986919			Aug 12 07:11:00 PM PDT 24	Aug 12 07:15:20 PM PDT 24	2474408648 ps
T362	/workspace/coverage/default/38.chip_sw_all_escalation_resets.1238408252			Aug 12 07:36:41 PM PDT 24	Aug 12 07:49:07 PM PDT 24	4849935196 ps
T967	/workspace/coverage/default/0.chip_sw_otp_ctrl_ecc_error_vendor_test.120616556			Aug 12 07:08:22 PM PDT 24	Aug 12 07:12:47 PM PDT 24	2809026410 ps
T136	/workspace/coverage/default/1.chip_sw_otbn_randomness.1405131709			Aug 12 07:14:16 PM PDT 24	Aug 12 07:34:25 PM PDT 24	5955286584 ps
T161	/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.2880394355			Aug 12 07:31:03 PM PDT 24	Aug 12 07:40:53 PM PDT 24	4077409304 ps
T337	/workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.3453560569			Aug 12 07:39:41 PM PDT 24	Aug 12 07:46:06 PM PDT 24	3884418494 ps
T54	/workspace/coverage/default/1.chip_sw_alert_handler_escalation.2758272694			Aug 12 07:16:29 PM PDT 24	Aug 12 07:25:06 PM PDT 24	5336921188 ps
T458	/workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.434507338			Aug 12 07:20:41 PM PDT 24	Aug 12 07:24:40 PM PDT 24	2929972633 ps
T778	/workspace/coverage/default/0.chip_sw_aes_entropy.164634008			Aug 12 07:08:42 PM PDT 24	Aug 12 07:12:45 PM PDT 24	2885495784 ps
T126	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.3141755129			Aug 12 07:18:31 PM PDT 24	Aug 12 07:30:05 PM PDT 24	4325041732 ps
T182	/workspace/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.2006898987			Aug 12 07:12:48 PM PDT 24	Aug 12 07:22:05 PM PDT 24	5609609372 ps
T779	/workspace/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.2181804990			Aug 12 07:08:41 PM PDT 24	Aug 12 07:18:09 PM PDT 24	6062023448 ps
T131	/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_wake_5_bug.2072706517			Aug 12 07:28:59 PM PDT 24	Aug 12 07:38:06 PM PDT 24	5939863640 ps
T791	/workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.1495654525			Aug 12 07:40:23 PM PDT 24	Aug 12 07:46:15 PM PDT 24	3193855560 ps
T132	/workspace/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.973310958			Aug 12 07:15:20 PM PDT 24	Aug 12 07:23:41 PM PDT 24	7433983818 ps
T248	/workspace/coverage/default/5.chip_sw_all_escalation_resets.371539482			Aug 12 07:32:50 PM PDT 24	Aug 12 07:44:10 PM PDT 24	5091010040 ps
T223	/workspace/coverage/default/4.chip_sw_uart_tx_rx.3937014701			Aug 12 07:31:19 PM PDT 24	Aug 12 07:41:07 PM PDT 24	4571484132 ps
T15	/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.1997734197			Aug 12 07:32:09 PM PDT 24	Aug 12 07:43:53 PM PDT 24	4413693088 ps
T16	/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2613839305			Aug 12 07:31:57 PM PDT 24	Aug 12 07:41:44 PM PDT 24	4687862474 ps
T75	/workspace/coverage/default/0.chip_tap_straps_dev.3630241644			Aug 12 07:09:10 PM PDT 24	Aug 12 07:28:52 PM PDT 24	9663103826 ps
T300	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops.753821682			Aug 12 07:10:32 PM PDT 24	Aug 12 07:20:50 PM PDT 24	4203402976 ps
T301	/workspace/coverage/default/0.chip_sw_rstmgr_smoketest.1563691468			Aug 12 07:10:17 PM PDT 24	Aug 12 07:12:54 PM PDT 24	2603724088 ps
T302	/workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.4133447245			Aug 12 07:40:36 PM PDT 24	Aug 12 07:47:32 PM PDT 24	3330669918 ps
T303	/workspace/coverage/default/67.chip_sw_all_escalation_resets.1825387949			Aug 12 07:39:14 PM PDT 24	Aug 12 07:49:48 PM PDT 24	4901621208 ps
T125	/workspace/coverage/default/1.chip_sw_lc_ctrl_transition.2776616678			Aug 12 07:12:06 PM PDT 24	Aug 12 07:22:23 PM PDT 24	6581982210 ps
T388	/workspace/coverage/default/0.chip_sw_rstmgr_sw_req.1443957314			Aug 12 07:06:42 PM PDT 24	Aug 12 07:11:24 PM PDT 24	4106355140 ps
T389	/workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.1502136899			Aug 12 07:40:24 PM PDT 24	Aug 12 07:45:11 PM PDT 24	3932670680 ps
T17	/workspace/coverage/default/2.chip_sw_sleep_pin_retention.2434055836			Aug 12 07:22:49 PM PDT 24	Aug 12 07:30:48 PM PDT 24	4198609960 ps
T107	/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_por_reset.2166860071			Aug 12 07:13:12 PM PDT 24	Aug 12 07:25:10 PM PDT 24	8838537256 ps
T108	/workspace/coverage/default/2.chip_sw_pwrmgr_main_power_glitch_reset.3247415251			Aug 12 07:24:26 PM PDT 24	Aug 12 07:31:04 PM PDT 24	3877929356 ps
T109	/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.3595531224			Aug 12 07:28:07 PM PDT 24	Aug 12 07:40:16 PM PDT 24	4982894888 ps
T70	/workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2026282903			Aug 12 07:09:35 PM PDT 24	Aug 12 07:18:33 PM PDT 24	4370804294 ps
T110	/workspace/coverage/default/1.chip_sw_i2c_device_tx_rx.3418849864			Aug 12 07:16:18 PM PDT 24	Aug 12 07:24:12 PM PDT 24	3391615008 ps
T76	/workspace/coverage/default/2.chip_tap_straps_dev.3604668698			Aug 12 07:28:04 PM PDT 24	Aug 12 07:40:01 PM PDT 24	6973548372 ps
T111	/workspace/coverage/default/0.rom_e2e_asm_init_test_unlocked0.2167197556			Aug 12 07:14:27 PM PDT 24	Aug 12 08:05:35 PM PDT 24	11172984280 ps
T112	/workspace/coverage/default/2.chip_sw_pwrmgr_smoketest.4032911624			Aug 12 07:30:40 PM PDT 24	Aug 12 07:38:36 PM PDT 24	4929293402 ps
T113	/workspace/coverage/default/1.chip_sw_clkmgr_smoketest.2524513234			Aug 12 07:24:24 PM PDT 24	Aug 12 07:28:12 PM PDT 24	3080670668 ps
T294	/workspace/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.796559473			Aug 12 07:11:19 PM PDT 24	Aug 12 07:16:24 PM PDT 24	3592812003 ps
T295	/workspace/coverage/default/1.chip_sw_example_rom.472450649			Aug 12 07:12:15 PM PDT 24	Aug 12 07:14:20 PM PDT 24	2540776536 ps
T296	/workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.3579721183			Aug 12 07:38:36 PM PDT 24	Aug 12 07:45:11 PM PDT 24	3203982492 ps
T175	/workspace/coverage/default/0.chip_sw_lc_walkthrough_testunlocks.2082297654			Aug 12 07:10:17 PM PDT 24	Aug 12 07:48:15 PM PDT 24	23496515576 ps
T320	/workspace/coverage/default/0.chip_sw_flash_crash_alert.1095047403			Aug 12 07:10:56 PM PDT 24	Aug 12 07:22:04 PM PDT 24	5311691952 ps
T317	/workspace/coverage/default/81.chip_sw_all_escalation_resets.3407019566			Aug 12 07:42:22 PM PDT 24	Aug 12 07:51:38 PM PDT 24	4542659766 ps
T328	/workspace/coverage/default/51.chip_sw_all_escalation_resets.3542737375			Aug 12 07:37:37 PM PDT 24	Aug 12 07:44:42 PM PDT 24	3923108456 ps
T222	/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx1.1379436445			Aug 12 07:24:26 PM PDT 24	Aug 12 07:35:51 PM PDT 24	4848437076 ps
T329	/workspace/coverage/default/2.chip_sw_alert_handler_ping_ok.2687912303			Aug 12 07:27:05 PM PDT 24	Aug 12 07:55:20 PM PDT 24	7937848732 ps
T330	/workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.4076752151			Aug 12 07:20:29 PM PDT 24	Aug 12 07:35:13 PM PDT 24	4769487608 ps
T244	/workspace/coverage/default/2.chip_sw_data_integrity_escalation.3709700437			Aug 12 07:21:57 PM PDT 24	Aug 12 07:38:26 PM PDT 24	5687484132 ps
T197	/workspace/coverage/default/5.chip_sw_lc_ctrl_transition.2553192451			Aug 12 07:33:13 PM PDT 24	Aug 12 07:48:31 PM PDT 24	8718454904 ps
T124	/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en.4095452610			Aug 12 07:08:34 PM PDT 24	Aug 12 07:36:57 PM PDT 24	9249323464 ps
T258	/workspace/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.3663757886			Aug 12 07:24:25 PM PDT 24	Aug 12 07:41:06 PM PDT 24	6282078634 ps
T284	/workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.3786207802			Aug 12 07:38:59 PM PDT 24	Aug 12 07:44:10 PM PDT 24	3740250356 ps
T245	/workspace/coverage/default/4.chip_sw_data_integrity_escalation.2354040587			Aug 12 07:33:06 PM PDT 24	Aug 12 07:45:44 PM PDT 24	4729569896 ps
T262	/workspace/coverage/default/6.chip_sw_csrng_edn_concurrency.3699952303			Aug 12 07:32:54 PM PDT 24	Aug 12 08:27:40 PM PDT 24	16771717440 ps
T285	/workspace/coverage/default/0.chip_sw_aes_idle.3694634135			Aug 12 07:09:53 PM PDT 24	Aug 12 07:15:18 PM PDT 24	2427257342 ps
T286	/workspace/coverage/default/1.chip_sw_kmac_idle.2498738666			Aug 12 07:17:22 PM PDT 24	Aug 12 07:20:50 PM PDT 24	3140148840 ps
T287	/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_por_reset.349385909			Aug 12 07:25:32 PM PDT 24	Aug 12 07:34:49 PM PDT 24	5393210808 ps
T414	/workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.811728927			Aug 12 07:36:39 PM PDT 24	Aug 12 07:42:51 PM PDT 24	4347719304 ps
T133	/workspace/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.1794724277			Aug 12 07:27:24 PM PDT 24	Aug 12 07:39:43 PM PDT 24	5304194824 ps
T386	/workspace/coverage/default/2.rom_e2e_asm_init_prod.227441496			Aug 12 07:36:27 PM PDT 24	Aug 12 08:31:04 PM PDT 24	15727392880 ps
T224	/workspace/coverage/default/19.chip_sw_uart_rand_baudrate.1636502530			Aug 12 07:36:05 PM PDT 24	Aug 12 07:45:52 PM PDT 24	3402524788 ps
T968	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_por_reset.2820784666			Aug 12 07:10:41 PM PDT 24	Aug 12 07:23:03 PM PDT 24	7410302700 ps
T259	/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.1685716668			Aug 12 07:09:04 PM PDT 24	Aug 12 07:49:11 PM PDT 24	27103198609 ps
T22	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.2697831925			Aug 12 07:15:57 PM PDT 24	Aug 12 07:42:55 PM PDT 24	23021540480 ps
T176	/workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.3819247359			Aug 12 07:07:06 PM PDT 24	Aug 12 08:49:43 PM PDT 24	51250152220 ps
T288	/workspace/coverage/default/0.chip_sw_otbn_mem_scramble.1134808666			Aug 12 07:09:55 PM PDT 24	Aug 12 07:17:45 PM PDT 24	3201292942 ps
T12	/workspace/coverage/default/0.chip_sw_power_virus.648383791			Aug 12 07:15:58 PM PDT 24	Aug 12 07:40:37 PM PDT 24	5577220692 ps
T969	/workspace/coverage/default/2.chip_sw_rv_plic_smoketest.2249331755			Aug 12 07:31:45 PM PDT 24	Aug 12 07:35:54 PM PDT 24	2802883548 ps
T219	/workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.1241591598			Aug 12 07:38:49 PM PDT 24	Aug 12 07:45:52 PM PDT 24	3490573806 ps
T792	/workspace/coverage/default/1.chip_sw_alert_handler_ping_ok.1777756254			Aug 12 07:17:34 PM PDT 24	Aug 12 07:42:22 PM PDT 24	8411111920 ps
T970	/workspace/coverage/default/1.chip_sw_entropy_src_kat_test.998533221			Aug 12 07:14:50 PM PDT 24	Aug 12 07:18:53 PM PDT 24	2815113480 ps
T264	/workspace/coverage/default/69.chip_sw_all_escalation_resets.2082742005			Aug 12 07:39:39 PM PDT 24	Aug 12 07:49:03 PM PDT 24	5226845884 ps
T86	/workspace/coverage/default/1.chip_sw_uart_tx_rx_bootstrap.3047678905			Aug 12 07:12:58 PM PDT 24	Aug 12 11:01:55 PM PDT 24	78183866664 ps
T225	/workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.3078001705			Aug 12 07:41:20 PM PDT 24	Aug 12 07:47:23 PM PDT 24	4332683606 ps
T198	/workspace/coverage/default/0.chip_sw_lc_walkthrough_rma.3840607708			Aug 12 07:07:36 PM PDT 24	Aug 12 08:44:35 PM PDT 24	46764858668 ps
T263	/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency.2431169829			Aug 12 07:11:35 PM PDT 24	Aug 12 08:49:07 PM PDT 24	25148011100 ps
T971	/workspace/coverage/default/1.chip_sw_aes_enc.2806440976			Aug 12 07:15:34 PM PDT 24	Aug 12 07:19:21 PM PDT 24	2721202216 ps
T138	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_wake_5_bug.2950226641			Aug 12 07:12:50 PM PDT 24	Aug 12 07:19:56 PM PDT 24	6792423344 ps
T71	/workspace/coverage/default/2.chip_sw_exit_test_unlocked_bootstrap.2009272961			Aug 12 07:22:44 PM PDT 24	Aug 12 10:19:22 PM PDT 24	59656232162 ps
T139	/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.1399024468			Aug 12 07:20:15 PM PDT 24	Aug 12 07:28:55 PM PDT 24	5472099092 ps
T187	/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.4291235230			Aug 12 07:29:03 PM PDT 24	Aug 12 07:38:11 PM PDT 24	4246886373 ps
T349	/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.4054487054			Aug 12 07:16:52 PM PDT 24	Aug 12 07:55:35 PM PDT 24	23405718571 ps
T188	/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.214944745			Aug 12 07:17:55 PM PDT 24	Aug 12 07:27:05 PM PDT 24	5343936245 ps
T117	/workspace/coverage/default/1.chip_sw_power_sleep_load.2402310674			Aug 12 07:21:48 PM PDT 24	Aug 12 07:28:55 PM PDT 24	5039243024 ps
T171	/workspace/coverage/default/10.chip_sw_all_escalation_resets.4121623735			Aug 12 07:34:11 PM PDT 24	Aug 12 07:47:14 PM PDT 24	5050181474 ps
T177	/workspace/coverage/default/49.chip_sw_all_escalation_resets.925708580			Aug 12 07:38:04 PM PDT 24	Aug 12 07:49:39 PM PDT 24	4532524352 ps
T18	/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.4141379058			Aug 12 07:23:39 PM PDT 24	Aug 12 07:30:17 PM PDT 24	7134833992 ps
T210	/workspace/coverage/default/2.chip_sw_uart_tx_rx_bootstrap.3497668146			Aug 12 07:21:58 PM PDT 24	Aug 12 11:10:39 PM PDT 24	78946463924 ps
T26	/workspace/coverage/default/0.chip_sw_gpio_smoketest.2221955034			Aug 12 07:11:44 PM PDT 24	Aug 12 07:17:34 PM PDT 24	3507796944 ps
T249	/workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.436485277			Aug 12 07:39:01 PM PDT 24	Aug 12 07:44:25 PM PDT 24	3540541752 ps
T183	/workspace/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.2524304174			Aug 12 07:12:57 PM PDT 24	Aug 12 07:45:28 PM PDT 24	25964250970 ps
T426	/workspace/coverage/default/5.chip_sw_uart_rand_baudrate.905322076			Aug 12 07:32:03 PM PDT 24	Aug 12 07:56:13 PM PDT 24	8555210820 ps
T350	/workspace/coverage/default/1.chip_sw_pwrmgr_lowpower_cancel.2714264217			Aug 12 07:19:42 PM PDT 24	Aug 12 07:25:57 PM PDT 24	3626230226 ps
T13	/workspace/coverage/default/0.chip_sw_spi_device_pass_through.3760234492			Aug 12 07:07:14 PM PDT 24	Aug 12 07:20:26 PM PDT 24	6316448835 ps
T390	/workspace/coverage/default/1.rom_e2e_asm_init_prod_end.4286398565			Aug 12 07:25:49 PM PDT 24	Aug 12 08:23:18 PM PDT 24	15786077227 ps
T427	/workspace/coverage/default/2.chip_sw_example_manufacturer.2228251153			Aug 12 07:24:06 PM PDT 24	Aug 12 07:28:18 PM PDT 24	2832319500 ps
T972	/workspace/coverage/default/2.chip_sw_flash_scrambling_smoketest.2628388612			Aug 12 07:33:07 PM PDT 24	Aug 12 07:36:37 PM PDT 24	3153456044 ps
T226	/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_prod.3020428175			Aug 12 07:17:57 PM PDT 24	Aug 12 07:41:31 PM PDT 24	7116143380 ps
T72	/workspace/coverage/default/2.chip_tap_straps_rma.3194581830			Aug 12 07:29:07 PM PDT 24	Aug 12 07:40:30 PM PDT 24	8104988702 ps
T83	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.3703738840			Aug 12 07:09:40 PM PDT 24	Aug 12 07:35:17 PM PDT 24	11120730712 ps
T973	/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_por_reset.4081076777			Aug 12 07:12:41 PM PDT 24	Aug 12 07:22:30 PM PDT 24	6829440164 ps
T974	/workspace/coverage/default/1.chip_sw_clkmgr_off_aes_trans.2788800394			Aug 12 07:18:53 PM PDT 24	Aug 12 07:30:01 PM PDT 24	5829908000 ps
T975	/workspace/coverage/default/1.chip_sw_lc_ctrl_otp_hw_cfg0.2411517993			Aug 12 07:12:33 PM PDT 24	Aug 12 07:17:28 PM PDT 24	2773648840 ps
T364	/workspace/coverage/default/45.chip_sw_all_escalation_resets.1015115262			Aug 12 07:37:47 PM PDT 24	Aug 12 07:46:55 PM PDT 24	4165590540 ps
T782	/workspace/coverage/default/3.chip_sw_all_escalation_resets.880900866			Aug 12 07:30:57 PM PDT 24	Aug 12 07:39:43 PM PDT 24	4828100316 ps
T401	/workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.6471484			Aug 12 07:36:16 PM PDT 24	Aug 12 07:42:12 PM PDT 24	3867477120 ps
T976	/workspace/coverage/default/1.chip_sw_aon_timer_wdog_lc_escalate.1824421498			Aug 12 07:14:04 PM PDT 24	Aug 12 07:29:38 PM PDT 24	4863583026 ps
T355	/workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en_reduced_freq.319245894			Aug 12 07:20:43 PM PDT 24	Aug 12 07:26:33 PM PDT 24	2870871586 ps
T58	/workspace/coverage/default/1.chip_sw_alert_test.589237073			Aug 12 07:16:49 PM PDT 24	Aug 12 07:22:51 PM PDT 24	3914628732 ps
T241	/workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.34977123			Aug 12 07:08:15 PM PDT 24	Aug 12 07:41:21 PM PDT 24	19688524611 ps
T853	/workspace/coverage/default/65.chip_sw_all_escalation_resets.2101857472			Aug 12 07:40:34 PM PDT 24	Aug 12 07:50:06 PM PDT 24	5324573680 ps
T977	/workspace/coverage/default/1.chip_sw_sram_ctrl_smoketest.2008495923			Aug 12 07:23:02 PM PDT 24	Aug 12 07:26:44 PM PDT 24	2981871832 ps
T844	/workspace/coverage/default/27.chip_sw_all_escalation_resets.2997510202			Aug 12 07:36:01 PM PDT 24	Aug 12 07:46:37 PM PDT 24	5883341960 ps
T978	/workspace/coverage/default/2.chip_sw_aon_timer_wdog_bite_reset.2182690068			Aug 12 07:25:01 PM PDT 24	Aug 12 07:42:47 PM PDT 24	10001093864 ps
T356	/workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.868255484			Aug 12 07:11:05 PM PDT 24	Aug 12 07:15:54 PM PDT 24	3441277286 ps
T321	/workspace/coverage/default/64.chip_sw_all_escalation_resets.3070655534			Aug 12 07:38:44 PM PDT 24	Aug 12 07:46:43 PM PDT 24	4048327228 ps
T808	/workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.2282723834			Aug 12 07:36:49 PM PDT 24	Aug 12 07:43:22 PM PDT 24	3996311720 ps
T759	/workspace/coverage/default/0.chip_tap_straps_prod.1257126762			Aug 12 07:08:41 PM PDT 24	Aug 12 07:30:16 PM PDT 24	10218171497 ps
T885	/workspace/coverage/default/82.chip_sw_all_escalation_resets.3629286366			Aug 12 07:44:12 PM PDT 24	Aug 12 07:53:01 PM PDT 24	5819155382 ps
T260	/workspace/coverage/default/0.rom_e2e_jtag_debug_test_unlocked0.1114231620			Aug 12 07:09:48 PM PDT 24	Aug 12 07:45:46 PM PDT 24	11508872026 ps
T979	/workspace/coverage/default/1.chip_sw_clkmgr_jitter.151182692			Aug 12 07:19:23 PM PDT 24	Aug 12 07:24:57 PM PDT 24	3208114119 ps
T344	/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.2488336853			Aug 12 07:12:50 PM PDT 24	Aug 12 07:25:18 PM PDT 24	4869333792 ps
T980	/workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.3918816262			Aug 12 07:09:15 PM PDT 24	Aug 12 07:23:00 PM PDT 24	7290845736 ps
T27	/workspace/coverage/default/2.chip_sw_gpio_smoketest.42484736			Aug 12 07:30:21 PM PDT 24	Aug 12 07:36:17 PM PDT 24	3096588674 ps
T127	/workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.1590110399			Aug 12 07:33:19 PM PDT 24	Aug 12 08:09:23 PM PDT 24	13068707673 ps
T981	/workspace/coverage/default/0.chip_sw_csrng_smoketest.952990817			Aug 12 07:13:39 PM PDT 24	Aug 12 07:18:13 PM PDT 24	2707233090 ps
T982	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2729314802			Aug 12 07:11:58 PM PDT 24	Aug 12 07:44:05 PM PDT 24	18810539236 ps
T278	/workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock.3970378740			Aug 12 07:08:44 PM PDT 24	Aug 12 07:11:07 PM PDT 24	2321782403 ps
T360	/workspace/coverage/default/2.chip_sw_pattgen_ios.427500558			Aug 12 07:22:43 PM PDT 24	Aug 12 07:28:40 PM PDT 24	3730258502 ps
T983	/workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.4064707536			Aug 12 07:10:53 PM PDT 24	Aug 12 07:22:14 PM PDT 24	9118427182 ps
T830	/workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.1689214310			Aug 12 07:37:36 PM PDT 24	Aug 12 07:44:17 PM PDT 24	4306031284 ps
T221	/workspace/coverage/default/16.chip_sw_uart_rand_baudrate.2736652860			Aug 12 07:35:03 PM PDT 24	Aug 12 07:57:12 PM PDT 24	8169574676 ps
T984	/workspace/coverage/default/0.chip_sw_coremark.2654440069			Aug 12 07:11:45 PM PDT 24	Aug 12 10:54:41 PM PDT 24	71732611344 ps
T227	/workspace/coverage/default/2.chip_sw_keymgr_sideload_otbn.235925421			Aug 12 07:27:06 PM PDT 24	Aug 12 08:32:41 PM PDT 24	15070314444 ps
T184	/workspace/coverage/default/2.chip_sw_lc_ctrl_rand_to_scrap.612707778			Aug 12 07:24:36 PM PDT 24	Aug 12 07:30:15 PM PDT 24	4287462254 ps
T410	/workspace/coverage/default/1.chip_sw_kmac_app_rom.4256410547			Aug 12 07:17:05 PM PDT 24	Aug 12 07:20:17 PM PDT 24	2556995000 ps
T985	/workspace/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.633907143			Aug 12 07:09:42 PM PDT 24	Aug 12 07:21:53 PM PDT 24	4166935726 ps
T986	/workspace/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.1032344650			Aug 12 07:32:26 PM PDT 24	Aug 12 08:15:11 PM PDT 24	25152064752 ps
T987	/workspace/coverage/default/2.chip_sw_entropy_src_smoketest.1442318139			Aug 12 07:31:56 PM PDT 24	Aug 12 07:41:49 PM PDT 24	3327083976 ps
T398	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.2732245022			Aug 12 07:15:14 PM PDT 24	Aug 12 08:50:26 PM PDT 24	23488473200 ps
T140	/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1557080804			Aug 12 07:18:33 PM PDT 24	Aug 12 07:26:37 PM PDT 24	5274822200 ps
T254	/workspace/coverage/default/1.chip_sw_rv_timer_irq.499753530			Aug 12 07:14:10 PM PDT 24	Aug 12 07:18:12 PM PDT 24	3036118812 ps
T289	/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.1179799221			Aug 12 07:10:30 PM PDT 24	Aug 12 07:20:48 PM PDT 24	3765705724 ps
T73	/workspace/coverage/default/0.chip_jtag_mem_access.480298966			Aug 12 07:01:08 PM PDT 24	Aug 12 07:18:48 PM PDT 24	13473702312 ps
T235	/workspace/coverage/default/1.chip_sw_flash_init.3660780580			Aug 12 07:11:52 PM PDT 24	Aug 12 07:52:39 PM PDT 24	17885083712 ps
T361	/workspace/coverage/default/0.chip_sw_pattgen_ios.2517713962			Aug 12 07:07:31 PM PDT 24	Aug 12 07:11:26 PM PDT 24	3467308266 ps
T988	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.874398607			Aug 12 07:16:52 PM PDT 24	Aug 12 08:15:46 PM PDT 24	15998227768 ps
T119	/workspace/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.3288012626			Aug 12 07:23:11 PM PDT 24	Aug 12 10:46:06 PM PDT 24	83832861238 ps
T989	/workspace/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg0.3268649682			Aug 12 07:11:04 PM PDT 24	Aug 12 07:17:36 PM PDT 24	3591289750 ps
T246	/workspace/coverage/default/70.chip_sw_all_escalation_resets.2430176476			Aug 12 07:40:35 PM PDT 24	Aug 12 07:52:13 PM PDT 24	5460579368 ps
T271	/workspace/coverage/default/75.chip_sw_all_escalation_resets.3850410967			Aug 12 07:41:01 PM PDT 24	Aug 12 07:51:52 PM PDT 24	4952295370 ps
T272	/workspace/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.1338861576			Aug 12 07:14:37 PM PDT 24	Aug 12 07:21:08 PM PDT 24	4231363382 ps
T273	/workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.978987234			Aug 12 07:43:34 PM PDT 24	Aug 12 07:48:52 PM PDT 24	4119462386 ps
T274	/workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.3798296635			Aug 12 07:41:27 PM PDT 24	Aug 12 07:46:39 PM PDT 24	3606018324 ps
T228	/workspace/coverage/default/1.chip_sw_keymgr_sideload_kmac.1028261549			Aug 12 07:18:10 PM PDT 24	Aug 12 07:43:30 PM PDT 24	7800113468 ps
T275	/workspace/coverage/default/2.chip_sw_clkmgr_smoketest.1911161246			Aug 12 07:29:56 PM PDT 24	Aug 12 07:34:58 PM PDT 24	2866731190 ps
T23	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_outputs.3721443533			Aug 12 07:13:23 PM PDT 24	Aug 12 07:20:10 PM PDT 24	3457358608 ps
T276	/workspace/coverage/default/1.chip_sw_flash_scrambling_smoketest.2679623695			Aug 12 07:27:11 PM PDT 24	Aug 12 07:31:37 PM PDT 24	3380775812 ps
T277	/workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.148653854			Aug 12 07:37:10 PM PDT 24	Aug 12 07:43:32 PM PDT 24	3772957896 ps
T250	/workspace/coverage/default/99.chip_sw_all_escalation_resets.2616100611			Aug 12 07:41:40 PM PDT 24	Aug 12 07:50:32 PM PDT 24	5151825008 ps
T128	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.2737751463			Aug 12 07:18:19 PM PDT 24	Aug 12 07:29:22 PM PDT 24	4887485560 ps
T345	/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.2130977729			Aug 12 07:34:04 PM PDT 24	Aug 12 07:46:25 PM PDT 24	4701146310 ps
T990	/workspace/coverage/default/0.chip_sw_rv_plic_smoketest.2564003652			Aug 12 07:11:58 PM PDT 24	Aug 12 07:17:01 PM PDT 24	2756129032 ps
T315	/workspace/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2074295471			Aug 12 07:20:16 PM PDT 24	Aug 12 07:31:16 PM PDT 24	4847509722 ps
T185	/workspace/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.928275648			Aug 12 07:07:45 PM PDT 24	Aug 12 07:10:02 PM PDT 24	2279631562 ps
T155	/workspace/coverage/default/0.chip_sw_sensor_ctrl_status.203644677			Aug 12 07:09:43 PM PDT 24	Aug 12 07:14:57 PM PDT 24	3167718691 ps
T991	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_power_glitch_reset.430380446			Aug 12 07:07:57 PM PDT 24	Aug 12 07:15:22 PM PDT 24	5996473344 ps
T24	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.4111786125			Aug 12 07:09:08 PM PDT 24	Aug 12 08:03:58 PM PDT 24	20803044185 ps
T240	/workspace/coverage/default/2.chip_sw_flash_init.1926170939			Aug 12 07:22:33 PM PDT 24	Aug 12 08:02:18 PM PDT 24	27086774553 ps
T992	/workspace/coverage/default/1.chip_sw_flash_ctrl_write_clear.2106971501			Aug 12 07:20:53 PM PDT 24	Aug 12 07:26:15 PM PDT 24	3266146536 ps
T383	/workspace/coverage/default/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.3443999236			Aug 12 07:19:29 PM PDT 24	Aug 12 07:27:08 PM PDT 24	6426310836 ps
T797	/workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.3483109965			Aug 12 07:35:43 PM PDT 24	Aug 12 07:42:06 PM PDT 24	4186217416 ps
T861	/workspace/coverage/default/87.chip_sw_all_escalation_resets.3925774675			Aug 12 07:41:29 PM PDT 24	Aug 12 07:52:23 PM PDT 24	5083101406 ps
T826	/workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.2621965159			Aug 12 07:37:11 PM PDT 24	Aug 12 07:44:58 PM PDT 24	4264325382 ps
T459	/workspace/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.3561489454			Aug 12 07:28:12 PM PDT 24	Aug 12 07:43:31 PM PDT 24	6488498834 ps
T993	/workspace/coverage/default/2.chip_sw_flash_ctrl_mem_protection.887476025			Aug 12 07:31:11 PM PDT 24	Aug 12 07:50:10 PM PDT 24	5391656360 ps
T802	/workspace/coverage/default/9.chip_sw_all_escalation_resets.4229040617			Aug 12 07:33:45 PM PDT 24	Aug 12 07:48:28 PM PDT 24	5288342120 ps
T363	/workspace/coverage/default/2.chip_sw_flash_crash_alert.2422691839			Aug 12 07:28:50 PM PDT 24	Aug 12 07:42:18 PM PDT 24	5807718136 ps
T357	/workspace/coverage/default/2.chip_sival_flash_info_access.933198389			Aug 12 07:26:58 PM PDT 24	Aug 12 07:31:29 PM PDT 24	2345584428 ps
T994	/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_power_glitch_reset.112691358			Aug 12 07:24:58 PM PDT 24	Aug 12 07:34:51 PM PDT 24	5186238484 ps
T815	/workspace/coverage/default/41.chip_sw_all_escalation_resets.3255361994			Aug 12 07:37:45 PM PDT 24	Aug 12 07:48:36 PM PDT 24	5620520586 ps
T211	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_outputs.1314012200			Aug 12 07:29:00 PM PDT 24	Aug 12 07:34:49 PM PDT 24	3219865432 ps
T995	/workspace/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.66834440			Aug 12 07:26:10 PM PDT 24	Aug 12 07:33:21 PM PDT 24	7264261096 ps
T870	/workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.2179113094			Aug 12 07:32:28 PM PDT 24	Aug 12 07:38:58 PM PDT 24	3786747600 ps
T353	/workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.2573799338			Aug 12 07:23:24 PM PDT 24	Aug 12 07:34:25 PM PDT 24	3773282859 ps
T48	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.2154410976			Aug 12 07:17:48 PM PDT 24	Aug 12 08:45:44 PM PDT 24	23665717850 ps
T788	/workspace/coverage/default/0.rom_e2e_jtag_inject_rma.3516640490			Aug 12 07:09:41 PM PDT 24	Aug 12 07:54:27 PM PDT 24	21524863711 ps
T836	/workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.2654781414			Aug 12 07:35:02 PM PDT 24	Aug 12 07:40:28 PM PDT 24	4490682400 ps
T134	/workspace/coverage/default/2.chip_sw_edn_auto_mode.2970591500			Aug 12 07:28:55 PM PDT 24	Aug 12 07:52:34 PM PDT 24	5273750210 ps
T871	/workspace/coverage/default/62.chip_sw_all_escalation_resets.778575803			Aug 12 07:38:04 PM PDT 24	Aug 12 07:48:06 PM PDT 24	4460040260 ps
T120	/workspace/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.3308952492			Aug 12 07:29:38 PM PDT 24	Aug 13 12:39:51 AM PDT 24	143210333584 ps
T162	/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.1271548597			Aug 12 07:28:52 PM PDT 24	Aug 12 08:18:06 PM PDT 24	24430294870 ps
T996	/workspace/coverage/default/7.chip_sw_lc_ctrl_transition.3464655684			Aug 12 07:32:42 PM PDT 24	Aug 12 07:43:24 PM PDT 24	7791306453 ps
T163	/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en.349663894			Aug 12 07:14:30 PM PDT 24	Aug 12 08:16:01 PM PDT 24	18887039984 ps
T49	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.2773458528			Aug 12 07:14:19 PM PDT 24	Aug 12 08:27:49 PM PDT 24	15196100875 ps
T368	/workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en_reduced_freq.2124799816			Aug 12 07:29:32 PM PDT 24	Aug 12 07:35:20 PM PDT 24	3425552242 ps
T997	/workspace/coverage/default/0.chip_sw_example_rom.557920459			Aug 12 07:08:18 PM PDT 24	Aug 12 07:10:19 PM PDT 24	1907215282 ps
T279	/workspace/coverage/default/2.rom_volatile_raw_unlock.1335299217			Aug 12 07:29:49 PM PDT 24	Aug 12 07:31:36 PM PDT 24	2676550202 ps
T822	/workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.1031144356			Aug 12 07:39:06 PM PDT 24	Aug 12 07:46:18 PM PDT 24	4218865516 ps
T374	/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.911778681			Aug 12 07:09:46 PM PDT 24	Aug 12 07:35:45 PM PDT 24	12999789000 ps
T794	/workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.970408908			Aug 12 07:37:29 PM PDT 24	Aug 12 07:44:10 PM PDT 24	3070335446 ps
T876	/workspace/coverage/default/74.chip_sw_all_escalation_resets.889968404			Aug 12 07:39:49 PM PDT 24	Aug 12 07:49:47 PM PDT 24	4341963120 ps
T879	/workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.1120945283			Aug 12 07:35:24 PM PDT 24	Aug 12 07:40:40 PM PDT 24	3649909736 ps
T998	/workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.3654259772			Aug 12 07:10:16 PM PDT 24	Aug 12 07:14:28 PM PDT 24	3083486140 ps
T280	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.777430764			Aug 12 07:15:42 PM PDT 24	Aug 12 08:14:08 PM PDT 24	14844366404 ps
T460	/workspace/coverage/default/0.chip_sw_kmac_entropy.3499655640			Aug 12 07:07:39 PM PDT 24	Aug 12 07:11:56 PM PDT 24	2478498776 ps
T767	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.3720855408			Aug 12 07:08:05 PM PDT 24	Aug 12 07:12:26 PM PDT 24	2899900176 ps
T999	/workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.1847593308			Aug 12 07:29:57 PM PDT 24	Aug 12 07:49:01 PM PDT 24	7930989442 ps
T118	/workspace/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3885142528			Aug 12 07:14:54 PM PDT 24	Aug 12 07:27:25 PM PDT 24	19977650600 ps
T19	/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.768881432			Aug 12 07:23:57 PM PDT 24	Aug 12 07:49:55 PM PDT 24	21869449876 ps
T828	/workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.3142047968			Aug 12 07:35:50 PM PDT 24	Aug 12 07:42:46 PM PDT 24	4047504756 ps
T281	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.1516550183			Aug 12 07:16:58 PM PDT 24	Aug 12 08:23:22 PM PDT 24	14133856236 ps
T798	/workspace/coverage/default/40.chip_sw_all_escalation_resets.845231593			Aug 12 07:37:35 PM PDT 24	Aug 12 07:48:51 PM PDT 24	5490795790 ps
T1000	/workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.1064813354			Aug 12 07:14:16 PM PDT 24	Aug 12 07:21:24 PM PDT 24	3215359572 ps
T1001	/workspace/coverage/default/1.rom_e2e_static_critical.3928777842			Aug 12 07:25:46 PM PDT 24	Aug 12 08:26:00 PM PDT 24	16895699320 ps
T1002	/workspace/coverage/default/0.chip_sw_sram_ctrl_smoketest.3839395703			Aug 12 07:14:09 PM PDT 24	Aug 12 07:17:35 PM PDT 24	3084154466 ps
T745	/workspace/coverage/default/8.chip_sw_csrng_edn_concurrency.162840415			Aug 12 07:33:26 PM PDT 24	Aug 12 09:25:32 PM PDT 24	34132483416 ps
T1003	/workspace/coverage/default/12.chip_sw_lc_ctrl_transition.1053681000			Aug 12 07:34:15 PM PDT 24	Aug 12 07:52:53 PM PDT 24	9736348492 ps
T164	/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.1336616618			Aug 12 07:12:46 PM PDT 24	Aug 12 08:07:56 PM PDT 24	16881504228 ps
T1004	/workspace/coverage/default/1.chip_sw_hmac_enc_idle.1933378828			Aug 12 07:18:25 PM PDT 24	Aug 12 07:21:58 PM PDT 24	2721239480 ps
T752	/workspace/coverage/default/3.chip_tap_straps_dev.1062495877			Aug 12 07:31:29 PM PDT 24	Aug 12 07:58:20 PM PDT 24	15765120117 ps
T1005	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_dev.182812320			Aug 12 07:14:19 PM PDT 24	Aug 12 08:11:48 PM PDT 24	15535610544 ps