Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.rom_ctrl__regs_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	145600	1			T79	44		T80	87		T81	6
values[2]	4517	1			T80	3		T251	2		T462	1
values[3]	2316	1			T565	28		T556	50		T554	52
values[4]	1703	1			T565	17		T556	30		T554	45
values[5]	1433	1			T565	14		T556	34		T554	20
values[6]	1125	1			T565	25		T556	44		T554	7
values[7]	903	1			T565	20		T556	27		T554	1
values[8]	746	1			T565	18		T556	28		T760	1
values[9]	628	1			T565	29		T556	18		T760	1
values[10]	574	1			T565	27		T556	31		T760	1
values[11]	500	1			T565	30		T556	31		T760	1
values[12]	407	1			T565	20		T556	17		T760	1
values[13]	384	1			T565	22		T556	19		T760	1
values[14]	357	1			T565	22		T556	12		T760	1
values[15]	305	1			T565	25		T760	1		T910	1
values[16]	287	1			T565	25		T760	1		T910	3
values[17]	273	1			T565	30		T760	1		T910	2
values[18]	223	1			T565	18		T760	1		T910	3
values[19]	230	1			T565	18		T760	1		T910	2
values[20]	252	1			T565	14		T760	1		T910	2
values[21]	243	1			T565	7		T760	1		T910	3
values[22]	218	1			T565	1		T760	1		T910	1
values[23]	251	1			T760	1		T910	2		T480	4
values[24]	267	1			T760	1		T910	1		T480	6
values[25]	268	1			T760	1		T910	2		T480	3
values[26]	269	1			T760	1		T910	2		T480	5
values[27]	255	1			T760	1		T910	2		T480	5
values[28]	187	1			T760	1		T910	2		T480	10
values[29]	181	1			T760	1		T910	2		T480	8
values[30]	161	1			T760	1		T910	2		T480	5
values[31]	144	1			T760	1		T910	1		T480	4
values[32]	117	1			T760	1		T910	1		T480	3
values[33]	133	1			T760	1		T910	4		T480	2
values[34]	119	1			T760	1		T910	2		T480	12
values[35]	127	1			T760	1		T910	2		T480	7
values[36]	124	1			T760	1		T910	2		T480	9
values[37]	108	1			T760	1		T910	3		T480	11
values[38]	115	1			T760	1		T910	1		T480	6
values[39]	136	1			T760	1		T910	1		T480	3
values[40]	143	1			T760	1		T910	3		T480	5
values[41]	132	1			T760	1		T910	1		T480	4
values[42]	141	1			T760	1		T910	2		T480	7
values[43]	107	1			T760	1		T910	1		T480	13
values[44]	81	1			T760	1		T910	1		T480	5
values[45]	69	1			T760	1		T910	2		T480	5
values[46]	67	1			T760	1		T910	1		T480	5
values[47]	83	1			T760	1		T910	3		T480	10
values[48]	97	1			T760	1		T910	3		T480	6
values[49]	88	1			T760	1		T910	3		T480	7
values[50]	65	1			T760	1		T910	3		T480	4
values[51]	71	1			T760	1		T910	4		T480	4
values[52]	76	1			T760	1		T910	3		T480	4
values[53]	90	1			T760	1		T910	5		T480	7
values[54]	85	1			T760	1		T910	4		T480	4
values[55]	86	1			T760	1		T910	1		T480	8
values[56]	82	1			T760	1		T910	1		T480	2
values[57]	83	1			T760	1		T910	1		T480	4
values[58]	81	1			T760	1		T910	5		T480	7
values[59]	64	1			T760	1		T910	1		T480	7
values[60]	63	1			T760	1		T910	2		T480	4
values[61]	57	1			T760	1		T910	2		T480	3
values[62]	66	1			T760	1		T910	2		T480	4
values[63]	73	1			T760	1		T910	1		T480	3
values[64]	69	1			T760	1		T910	3		T480	6
values[65]	60	1			T760	1		T910	2		T480	8
values[66]	53	1			T760	1		T910	1		T480	5
values[67]	56	1			T760	1		T910	1		T480	5
values[68]	54	1			T760	1		T910	1		T480	5
values[69]	59	1			T760	1		T910	4		T480	3
values[70]	73	1			T760	1		T910	5		T480	4
values[71]	78	1			T760	1		T910	5		T480	6
values[72]	73	1			T760	1		T910	8		T480	6
values[73]	77	1			T760	1		T910	6		T480	4
values[74]	72	1			T760	1		T910	5		T480	4
values[75]	73	1			T760	1		T910	10		T480	6
values[76]	75	1			T760	1		T910	11		T480	6
values[77]	62	1			T760	1		T910	4		T480	3
values[78]	66	1			T760	1		T910	1		T480	2
values[79]	72	1			T760	1		T910	1		T480	2
values[80]	95	1			T760	1		T910	5		T480	10
values[81]	70	1			T760	1		T910	1		T480	8
values[82]	78	1			T760	1		T910	4		T480	3
values[83]	74	1			T760	1		T910	4		T480	5
values[84]	82	1			T760	1		T910	5		T480	9
values[85]	79	1			T760	1		T910	4		T480	5
values[86]	84	1			T760	1		T910	8		T480	3
values[87]	78	1			T760	1		T910	2		T480	8
values[88]	75	1			T760	1		T910	3		T480	8
values[89]	93	1			T760	1		T910	6		T480	7
values[90]	105	1			T760	1		T910	13		T480	8
values[91]	111	1			T760	1		T910	5		T480	10
values[92]	102	1			T760	1		T910	7		T480	7
values[93]	101	1			T760	1		T910	6		T480	6
values[94]	82	1			T760	2		T910	4		T480	6
values[95]	84	1			T760	1		T910	6		T480	11
values[96]	93	1			T760	1		T910	1		T480	10
values[97]	98	1			T760	1		T910	3		T480	5
values[98]	103	1			T760	1		T910	2		T480	12
values[99]	95	1			T760	1		T910	1		T480	9
values[100]	94	1			T760	1		T910	3		T480	4
values[101]	81	1			T760	1		T910	1		T480	8
values[102]	89	1			T760	1		T910	3		T480	11
values[103]	89	1			T760	1		T910	5		T480	4
values[104]	120	1			T760	1		T910	7		T480	7
values[105]	114	1			T760	1		T910	2		T480	11
values[106]	89	1			T760	1		T910	3		T480	5
values[107]	92	1			T760	1		T910	1		T480	11
values[108]	88	1			T760	1		T910	3		T480	12
values[109]	107	1			T760	1		T910	1		T480	13
values[110]	100	1			T760	1		T910	3		T480	6
values[111]	84	1			T760	1		T910	4		T480	5
values[112]	97	1			T760	1		T910	3		T480	10
values[113]	122	1			T760	3		T910	5		T480	6
values[114]	110	1			T760	4		T910	5		T480	11
values[115]	103	1			T760	2		T910	2		T480	11
values[116]	108	1			T760	3		T910	5		T480	12
values[117]	102	1			T760	3		T910	3		T480	14
values[118]	136	1			T760	1		T910	5		T480	20
values[119]	125	1			T760	1		T910	3		T480	8
values[120]	120	1			T760	3		T910	4		T480	8
values[121]	102	1			T760	3		T910	3		T480	6
values[122]	129	1			T760	5		T910	2		T480	13
values[123]	139	1			T760	3		T910	12		T480	13
values[124]	221	1			T760	3		T910	17		T480	14
values[125]	470	1			T760	3		T910	41		T480	41
values[126]	1011	1			T760	12		T910	70		T480	78
values[127]	3057	1			T760	94		T910	23		T480	39
values[128]	5295	1			T760	199		T910	3		T480	1